1 files changed, 109 insertions, 2 deletions

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index be252abe8985..599e490cf62c 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -38,6 +38,8 @@
 #define  TG3PCI_DEVICE_TIGON3_2          0x1645 /* BCM5701 */
 #define  TG3PCI_DEVICE_TIGON3_3          0x1646 /* BCM5702 */
 #define  TG3PCI_DEVICE_TIGON3_4          0x1647 /* BCM5703 */
+#define  TG3PCI_DEVICE_TIGON3_5761S      0x1688
+#define  TG3PCI_DEVICE_TIGON3_5761SE     0x1689
 #define TG3PCI_COMMAND                  0x00000004
 #define TG3PCI_STATUS                   0x00000006
 #define TG3PCI_CCREVID                  0x00000008
@@ -325,6 +327,7 @@
 #define  MAC_MODE_TDE_ENABLE             0x00200000
 #define  MAC_MODE_RDE_ENABLE             0x00400000
 #define  MAC_MODE_FHDE_ENABLE            0x00800000
+#define  MAC_MODE_KEEP_FRAME_IN_WOL      0x01000000
 #define  MAC_MODE_APE_RX_EN              0x08000000
 #define  MAC_MODE_APE_TX_EN              0x10000000
 #define MAC_STATUS                      0x00000404
@@ -414,6 +417,7 @@
 #define  MI_COM_DATA_MASK                0x0000ffff
 #define MAC_MI_STAT                     0x00000450
 #define  MAC_MI_STAT_LNKSTAT_ATTN_ENAB   0x00000001
+#define  MAC_MI_STAT_10MBPS_MODE         0x00000002
 #define MAC_MI_MODE                     0x00000454
 #define  MAC_MI_MODE_CLK_10MHZ           0x00000001
 #define  MAC_MI_MODE_SHORT_PREAMBLE      0x00000002
@@ -539,6 +543,100 @@
 #define  MAC_PHYCFG1_TXC_DRV             0x20000000
 #define MAC_PHYCFG2                     0x000005a4
 #define  MAC_PHYCFG2_INBAND_ENABLE       0x00000001
+#define  MAC_PHYCFG2_EMODE_MASK_MASK     0x000001c0
+#define  MAC_PHYCFG2_EMODE_MASK_AC131    0x000000c0
+#define  MAC_PHYCFG2_EMODE_MASK_50610    0x00000100
+#define  MAC_PHYCFG2_EMODE_MASK_RT8211   0x00000000
+#define  MAC_PHYCFG2_EMODE_MASK_RT8201   0x000001c0
+#define  MAC_PHYCFG2_EMODE_COMP_MASK     0x00000e00
+#define  MAC_PHYCFG2_EMODE_COMP_AC131    0x00000600
+#define  MAC_PHYCFG2_EMODE_COMP_50610    0x00000400
+#define  MAC_PHYCFG2_EMODE_COMP_RT8211   0x00000800
+#define  MAC_PHYCFG2_EMODE_COMP_RT8201   0x00000000
+#define  MAC_PHYCFG2_FMODE_MASK_MASK     0x00007000
+#define  MAC_PHYCFG2_FMODE_MASK_AC131    0x00006000
+#define  MAC_PHYCFG2_FMODE_MASK_50610    0x00004000
+#define  MAC_PHYCFG2_FMODE_MASK_RT8211   0x00000000
+#define  MAC_PHYCFG2_FMODE_MASK_RT8201   0x00007000
+#define  MAC_PHYCFG2_FMODE_COMP_MASK     0x00038000
+#define  MAC_PHYCFG2_FMODE_COMP_AC131    0x00030000
+#define  MAC_PHYCFG2_FMODE_COMP_50610    0x00008000
+#define  MAC_PHYCFG2_FMODE_COMP_RT8211   0x00038000
+#define  MAC_PHYCFG2_FMODE_COMP_RT8201   0x00000000
+#define  MAC_PHYCFG2_GMODE_MASK_MASK     0x001c0000
+#define  MAC_PHYCFG2_GMODE_MASK_AC131    0x001c0000
+#define  MAC_PHYCFG2_GMODE_MASK_50610    0x00100000
+#define  MAC_PHYCFG2_GMODE_MASK_RT8211   0x00000000
+#define  MAC_PHYCFG2_GMODE_MASK_RT8201   0x001c0000
+#define  MAC_PHYCFG2_GMODE_COMP_MASK     0x00e00000
+#define  MAC_PHYCFG2_GMODE_COMP_AC131    0x00e00000
+#define  MAC_PHYCFG2_GMODE_COMP_50610    0x00000000
+#define  MAC_PHYCFG2_GMODE_COMP_RT8211   0x00200000
+#define  MAC_PHYCFG2_GMODE_COMP_RT8201   0x00000000
+#define  MAC_PHYCFG2_ACT_MASK_MASK       0x03000000
+#define  MAC_PHYCFG2_ACT_MASK_AC131      0x03000000
+#define  MAC_PHYCFG2_ACT_MASK_50610      0x01000000
+#define  MAC_PHYCFG2_ACT_MASK_RT8211     0x03000000
+#define  MAC_PHYCFG2_ACT_MASK_RT8201     0x01000000
+#define  MAC_PHYCFG2_ACT_COMP_MASK       0x0c000000
+#define  MAC_PHYCFG2_ACT_COMP_AC131      0x00000000
+#define  MAC_PHYCFG2_ACT_COMP_50610      0x00000000
+#define  MAC_PHYCFG2_ACT_COMP_RT8211     0x00000000
+#define  MAC_PHYCFG2_ACT_COMP_RT8201     0x08000000
+#define  MAC_PHYCFG2_QUAL_MASK_MASK      0x30000000
+#define  MAC_PHYCFG2_QUAL_MASK_AC131     0x30000000
+#define  MAC_PHYCFG2_QUAL_MASK_50610     0x30000000
+#define  MAC_PHYCFG2_QUAL_MASK_RT8211    0x30000000
+#define  MAC_PHYCFG2_QUAL_MASK_RT8201    0x30000000
+#define  MAC_PHYCFG2_QUAL_COMP_MASK      0xc0000000
+#define  MAC_PHYCFG2_QUAL_COMP_AC131     0x00000000
+#define  MAC_PHYCFG2_QUAL_COMP_50610     0x00000000
+#define  MAC_PHYCFG2_QUAL_COMP_RT8211    0x00000000
+#define  MAC_PHYCFG2_QUAL_COMP_RT8201    0x00000000
+#define MAC_PHYCFG2_50610_LED_MODES \
+        (MAC_PHYCFG2_EMODE_MASK_50610 | \
+         MAC_PHYCFG2_EMODE_COMP_50610 | \
+         MAC_PHYCFG2_FMODE_MASK_50610 | \
+         MAC_PHYCFG2_FMODE_COMP_50610 | \
+         MAC_PHYCFG2_GMODE_MASK_50610 | \
+         MAC_PHYCFG2_GMODE_COMP_50610 | \
+         MAC_PHYCFG2_ACT_MASK_50610 | \
+         MAC_PHYCFG2_ACT_COMP_50610 | \
+         MAC_PHYCFG2_QUAL_MASK_50610 | \
+         MAC_PHYCFG2_QUAL_COMP_50610)
+#define MAC_PHYCFG2_AC131_LED_MODES \
+        (MAC_PHYCFG2_EMODE_MASK_AC131 | \
+         MAC_PHYCFG2_EMODE_COMP_AC131 | \
+         MAC_PHYCFG2_FMODE_MASK_AC131 | \
+         MAC_PHYCFG2_FMODE_COMP_AC131 | \
+         MAC_PHYCFG2_GMODE_MASK_AC131 | \
+         MAC_PHYCFG2_GMODE_COMP_AC131 | \
+         MAC_PHYCFG2_ACT_MASK_AC131 | \
+         MAC_PHYCFG2_ACT_COMP_AC131 | \
+         MAC_PHYCFG2_QUAL_MASK_AC131 | \
+         MAC_PHYCFG2_QUAL_COMP_AC131)
+#define MAC_PHYCFG2_RTL8211C_LED_MODES \
+        (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
+         MAC_PHYCFG2_EMODE_COMP_RT8211 | \
+         MAC_PHYCFG2_FMODE_MASK_RT8211 | \
+         MAC_PHYCFG2_FMODE_COMP_RT8211 | \
+         MAC_PHYCFG2_GMODE_MASK_RT8211 | \
+         MAC_PHYCFG2_GMODE_COMP_RT8211 | \
+         MAC_PHYCFG2_ACT_MASK_RT8211 | \
+         MAC_PHYCFG2_ACT_COMP_RT8211 | \
+         MAC_PHYCFG2_QUAL_MASK_RT8211 | \
+         MAC_PHYCFG2_QUAL_COMP_RT8211)
+#define MAC_PHYCFG2_RTL8201E_LED_MODES \
+        (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
+         MAC_PHYCFG2_EMODE_COMP_RT8201 | \
+         MAC_PHYCFG2_FMODE_MASK_RT8201 | \
+         MAC_PHYCFG2_FMODE_COMP_RT8201 | \
+         MAC_PHYCFG2_GMODE_MASK_RT8201 | \
+         MAC_PHYCFG2_GMODE_COMP_RT8201 | \
+         MAC_PHYCFG2_ACT_MASK_RT8201 | \
+         MAC_PHYCFG2_ACT_COMP_RT8201 | \
+         MAC_PHYCFG2_QUAL_MASK_RT8201 | \
+         MAC_PHYCFG2_QUAL_COMP_RT8201)
 #define MAC_EXT_RGMII_MODE              0x000005a8
 #define  MAC_RGMII_MODE_TX_ENABLE        0x00000001
 #define  MAC_RGMII_MODE_TX_LOWPWR        0x00000002
@@ -1792,6 +1890,11 @@
 
 #define MII_TG3_AUX_CTRL                0x18 /* auxilliary control register */
 
+#define MII_TG3_AUXCTL_PCTL_100TX_LPWR  0x0010
+#define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
+#define MII_TG3_AUXCTL_PCTL_VREG_11V    0x0180
+#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL   0x0002
+
 #define MII_TG3_AUXCTL_MISC_WREN        0x8000
 #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
 #define MII_TG3_AUXCTL_MISC_RDSEL_MISC  0x7000
@@ -2507,7 +2610,6 @@ struct tg3 {
         u32                             tg3_flags3;
 #define TG3_FLG3_NO_NVRAM_ADDR_TRANS    0x00000001
 #define TG3_FLG3_ENABLE_APE             0x00000002
-#define TG3_FLG3_5761_5784_AX_FIXES     0x00000004
 #define TG3_FLG3_5701_DMA_BUG           0x00000008
 #define TG3_FLG3_USE_PHYLIB             0x00000010
 #define TG3_FLG3_MDIOBUS_INITED         0x00000020
@@ -2588,7 +2690,12 @@ struct tg3 {
 #define PHY_REV_BCM5411_X0              0x1 /* Found on Netgear GA302T */
 #define TG3_PHY_ID_BCM50610             0x143bd60
 #define TG3_PHY_ID_BCMAC131             0x143bc70
-
+#define TG3_PHY_ID_RTL8211C             0x001cc910
+#define TG3_PHY_ID_RTL8201E             0x00008200
+#define TG3_PHY_OUI_MASK                0xfffffc00
+#define TG3_PHY_OUI_1                   0x00206000
+#define TG3_PHY_OUI_2                   0x0143bc00
+#define TG3_PHY_OUI_3                   0x03625c00
 
         u32                             led_ctrl;
         u32                             phy_otp;