diff options
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r-- | drivers/net/tg3.h | 73 |
1 files changed, 57 insertions, 16 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index bab7940158e6..453a34fb72b9 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -46,10 +46,9 @@ | |||
46 | #define TG3PCI_DEVICE_TIGON3_57788 0x1691 | 46 | #define TG3PCI_DEVICE_TIGON3_57788 0x1691 |
47 | #define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */ | 47 | #define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */ |
48 | #define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */ | 48 | #define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */ |
49 | #define TG3PCI_DEVICE_TIGON3_5717C 0x1655 | 49 | #define TG3PCI_DEVICE_TIGON3_5717 0x1655 |
50 | #define TG3PCI_DEVICE_TIGON3_5717S 0x1656 | 50 | #define TG3PCI_DEVICE_TIGON3_5718 0x1656 |
51 | #define TG3PCI_DEVICE_TIGON3_5718C 0x1665 | 51 | #define TG3PCI_DEVICE_TIGON3_5724 0x165c |
52 | #define TG3PCI_DEVICE_TIGON3_5718S 0x1666 | ||
53 | /* 0x04 --> 0x64 unused */ | 52 | /* 0x04 --> 0x64 unused */ |
54 | #define TG3PCI_MSI_DATA 0x00000064 | 53 | #define TG3PCI_MSI_DATA 0x00000064 |
55 | /* 0x66 --> 0x68 unused */ | 54 | /* 0x66 --> 0x68 unused */ |
@@ -103,6 +102,7 @@ | |||
103 | #define CHIPREV_ID_5906_A1 0xc001 | 102 | #define CHIPREV_ID_5906_A1 0xc001 |
104 | #define CHIPREV_ID_57780_A0 0x57780000 | 103 | #define CHIPREV_ID_57780_A0 0x57780000 |
105 | #define CHIPREV_ID_57780_A1 0x57780001 | 104 | #define CHIPREV_ID_57780_A1 0x57780001 |
105 | #define CHIPREV_ID_5717_A0 0x05717000 | ||
106 | #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) | 106 | #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) |
107 | #define ASIC_REV_5700 0x07 | 107 | #define ASIC_REV_5700 0x07 |
108 | #define ASIC_REV_5701 0x00 | 108 | #define ASIC_REV_5701 0x00 |
@@ -141,8 +141,7 @@ | |||
141 | #define METAL_REV_B1 0x01 | 141 | #define METAL_REV_B1 0x01 |
142 | #define METAL_REV_B2 0x02 | 142 | #define METAL_REV_B2 0x02 |
143 | #define TG3PCI_DMA_RW_CTRL 0x0000006c | 143 | #define TG3PCI_DMA_RW_CTRL 0x0000006c |
144 | #define DMA_RWCTRL_MIN_DMA 0x000000ff | 144 | #define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001 |
145 | #define DMA_RWCTRL_MIN_DMA_SHIFT 0 | ||
146 | #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700 | 145 | #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700 |
147 | #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000 | 146 | #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000 |
148 | #define DMA_RWCTRL_READ_BNDRY_16 0x00000100 | 147 | #define DMA_RWCTRL_READ_BNDRY_16 0x00000100 |
@@ -242,7 +241,11 @@ | |||
242 | #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */ | 241 | #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */ |
243 | #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */ | 242 | #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */ |
244 | #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */ | 243 | #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */ |
244 | #define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \ | ||
245 | TG3_64BIT_REG_LOW) | ||
245 | #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */ | 246 | #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */ |
247 | #define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \ | ||
248 | TG3_64BIT_REG_LOW) | ||
246 | #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */ | 249 | #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */ |
247 | #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */ | 250 | #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */ |
248 | #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */ | 251 | #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */ |
@@ -1264,8 +1267,9 @@ | |||
1264 | #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080 | 1267 | #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080 |
1265 | #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100 | 1268 | #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100 |
1266 | #define WDMAC_MODE_LNGREAD_ENAB 0x00000200 | 1269 | #define WDMAC_MODE_LNGREAD_ENAB 0x00000200 |
1267 | #define WDMAC_MODE_RX_ACCEL 0x00000400 | 1270 | #define WDMAC_MODE_RX_ACCEL 0x00000400 |
1268 | #define WDMAC_MODE_STATUS_TAG_FIX 0x20000000 | 1271 | #define WDMAC_MODE_STATUS_TAG_FIX 0x20000000 |
1272 | #define WDMAC_MODE_BURST_ALL_DATA 0xc0000000 | ||
1269 | #define WDMAC_STATUS 0x00004c04 | 1273 | #define WDMAC_STATUS 0x00004c04 |
1270 | #define WDMAC_STATUS_TGTABORT 0x00000004 | 1274 | #define WDMAC_STATUS_TGTABORT 0x00000004 |
1271 | #define WDMAC_STATUS_MSTABORT 0x00000008 | 1275 | #define WDMAC_STATUS_MSTABORT 0x00000008 |
@@ -1953,10 +1957,34 @@ | |||
1953 | #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 | 1957 | #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 |
1954 | #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 | 1958 | #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 |
1955 | 1959 | ||
1960 | |||
1956 | /* Currently this is fixed. */ | 1961 | /* Currently this is fixed. */ |
1957 | #define PHY_ADDR 0x01 | 1962 | #define TG3_PHY_PCIE_ADDR 0x00 |
1963 | #define TG3_PHY_MII_ADDR 0x01 | ||
1964 | |||
1965 | |||
1966 | /*** Tigon3 specific PHY PCIE registers. ***/ | ||
1967 | |||
1968 | #define TG3_PCIEPHY_BLOCK_ADDR 0x1f | ||
1969 | #define TG3_PCIEPHY_XGXS_BLK1 0x0801 | ||
1970 | #define TG3_PCIEPHY_TXB_BLK 0x0861 | ||
1971 | #define TG3_PCIEPHY_BLOCK_SHIFT 4 | ||
1958 | 1972 | ||
1959 | /* Tigon3 specific PHY MII registers. */ | 1973 | /* TG3_PCIEPHY_TXB_BLK */ |
1974 | #define TG3_PCIEPHY_TX0CTRL1 0x15 | ||
1975 | #define TG3_PCIEPHY_TX0CTRL1_TXOCM 0x0003 | ||
1976 | #define TG3_PCIEPHY_TX0CTRL1_RDCTL 0x0008 | ||
1977 | #define TG3_PCIEPHY_TX0CTRL1_TXCMV 0x0030 | ||
1978 | #define TG3_PCIEPHY_TX0CTRL1_TKSEL 0x0040 | ||
1979 | #define TG3_PCIEPHY_TX0CTRL1_NB_EN 0x0400 | ||
1980 | |||
1981 | /* TG3_PCIEPHY_XGXS_BLK1 */ | ||
1982 | #define TG3_PCIEPHY_PWRMGMT4 0x1a | ||
1983 | #define TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN 0x0038 | ||
1984 | #define TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN 0x4000 | ||
1985 | |||
1986 | |||
1987 | /*** Tigon3 specific PHY MII registers. ***/ | ||
1960 | #define TG3_BMCR_SPEED1000 0x0040 | 1988 | #define TG3_BMCR_SPEED1000 0x0040 |
1961 | 1989 | ||
1962 | #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */ | 1990 | #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */ |
@@ -2055,6 +2083,9 @@ | |||
2055 | #define MII_TG3_FET_SHDW_MISCCTRL 0x10 | 2083 | #define MII_TG3_FET_SHDW_MISCCTRL 0x10 |
2056 | #define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000 | 2084 | #define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000 |
2057 | 2085 | ||
2086 | #define MII_TG3_FET_SHDW_AUXMODE4 0x1a | ||
2087 | #define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008 | ||
2088 | |||
2058 | #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b | 2089 | #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b |
2059 | #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020 | 2090 | #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020 |
2060 | 2091 | ||
@@ -2542,8 +2573,10 @@ struct tg3_ethtool_stats { | |||
2542 | }; | 2573 | }; |
2543 | 2574 | ||
2544 | struct tg3_rx_prodring_set { | 2575 | struct tg3_rx_prodring_set { |
2545 | u32 rx_std_ptr; | 2576 | u32 rx_std_prod_idx; |
2546 | u32 rx_jmb_ptr; | 2577 | u32 rx_std_cons_idx; |
2578 | u32 rx_jmb_prod_idx; | ||
2579 | u32 rx_jmb_cons_idx; | ||
2547 | struct tg3_rx_buffer_desc *rx_std; | 2580 | struct tg3_rx_buffer_desc *rx_std; |
2548 | struct tg3_ext_rx_buffer_desc *rx_jmb; | 2581 | struct tg3_ext_rx_buffer_desc *rx_jmb; |
2549 | struct ring_info *rx_std_buffers; | 2582 | struct ring_info *rx_std_buffers; |
@@ -2571,6 +2604,7 @@ struct tg3_napi { | |||
2571 | u32 consmbox; | 2604 | u32 consmbox; |
2572 | u32 rx_rcb_ptr; | 2605 | u32 rx_rcb_ptr; |
2573 | u16 *rx_rcb_prod_idx; | 2606 | u16 *rx_rcb_prod_idx; |
2607 | struct tg3_rx_prodring_set *prodring; | ||
2574 | 2608 | ||
2575 | struct tg3_rx_buffer_desc *rx_rcb; | 2609 | struct tg3_rx_buffer_desc *rx_rcb; |
2576 | struct tg3_tx_buffer_desc *tx_ring; | 2610 | struct tg3_tx_buffer_desc *tx_ring; |
@@ -2654,7 +2688,7 @@ struct tg3 { | |||
2654 | struct vlan_group *vlgrp; | 2688 | struct vlan_group *vlgrp; |
2655 | #endif | 2689 | #endif |
2656 | 2690 | ||
2657 | struct tg3_rx_prodring_set prodring[1]; | 2691 | struct tg3_rx_prodring_set prodring[TG3_IRQ_MAX_VECS - 1]; |
2658 | 2692 | ||
2659 | 2693 | ||
2660 | /* begin "everything else" cacheline(s) section */ | 2694 | /* begin "everything else" cacheline(s) section */ |
@@ -2725,7 +2759,7 @@ struct tg3 { | |||
2725 | #define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000 | 2759 | #define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000 |
2726 | #define TG3_FLG2_5705_PLUS 0x00040000 | 2760 | #define TG3_FLG2_5705_PLUS 0x00040000 |
2727 | #define TG3_FLG2_5750_PLUS 0x00080000 | 2761 | #define TG3_FLG2_5750_PLUS 0x00080000 |
2728 | #define TG3_FLG2_PROTECTED_NVRAM 0x00100000 | 2762 | #define TG3_FLG2_HW_TSO_3 0x00100000 |
2729 | #define TG3_FLG2_USING_MSI 0x00200000 | 2763 | #define TG3_FLG2_USING_MSI 0x00200000 |
2730 | #define TG3_FLG2_USING_MSIX 0x00400000 | 2764 | #define TG3_FLG2_USING_MSIX 0x00400000 |
2731 | #define TG3_FLG2_USING_MSI_OR_MSIX (TG3_FLG2_USING_MSI | \ | 2765 | #define TG3_FLG2_USING_MSI_OR_MSIX (TG3_FLG2_USING_MSI | \ |
@@ -2737,7 +2771,9 @@ struct tg3 { | |||
2737 | #define TG3_FLG2_ICH_WORKAROUND 0x02000000 | 2771 | #define TG3_FLG2_ICH_WORKAROUND 0x02000000 |
2738 | #define TG3_FLG2_5780_CLASS 0x04000000 | 2772 | #define TG3_FLG2_5780_CLASS 0x04000000 |
2739 | #define TG3_FLG2_HW_TSO_2 0x08000000 | 2773 | #define TG3_FLG2_HW_TSO_2 0x08000000 |
2740 | #define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2) | 2774 | #define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | \ |
2775 | TG3_FLG2_HW_TSO_2 | \ | ||
2776 | TG3_FLG2_HW_TSO_3) | ||
2741 | #define TG3_FLG2_1SHOT_MSI 0x10000000 | 2777 | #define TG3_FLG2_1SHOT_MSI 0x10000000 |
2742 | #define TG3_FLG2_PHY_JITTER_BUG 0x20000000 | 2778 | #define TG3_FLG2_PHY_JITTER_BUG 0x20000000 |
2743 | #define TG3_FLG2_NO_FWARE_REPORTED 0x40000000 | 2779 | #define TG3_FLG2_NO_FWARE_REPORTED 0x40000000 |
@@ -2745,6 +2781,7 @@ struct tg3 { | |||
2745 | u32 tg3_flags3; | 2781 | u32 tg3_flags3; |
2746 | #define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001 | 2782 | #define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001 |
2747 | #define TG3_FLG3_ENABLE_APE 0x00000002 | 2783 | #define TG3_FLG3_ENABLE_APE 0x00000002 |
2784 | #define TG3_FLG3_PROTECTED_NVRAM 0x00000004 | ||
2748 | #define TG3_FLG3_5701_DMA_BUG 0x00000008 | 2785 | #define TG3_FLG3_5701_DMA_BUG 0x00000008 |
2749 | #define TG3_FLG3_USE_PHYLIB 0x00000010 | 2786 | #define TG3_FLG3_USE_PHYLIB 0x00000010 |
2750 | #define TG3_FLG3_MDIOBUS_INITED 0x00000020 | 2787 | #define TG3_FLG3_MDIOBUS_INITED 0x00000020 |
@@ -2756,9 +2793,11 @@ struct tg3 { | |||
2756 | #define TG3_FLG3_PHY_ENABLE_APD 0x00001000 | 2793 | #define TG3_FLG3_PHY_ENABLE_APD 0x00001000 |
2757 | #define TG3_FLG3_5755_PLUS 0x00002000 | 2794 | #define TG3_FLG3_5755_PLUS 0x00002000 |
2758 | #define TG3_FLG3_NO_NVRAM 0x00004000 | 2795 | #define TG3_FLG3_NO_NVRAM 0x00004000 |
2759 | #define TG3_FLG3_TOGGLE_10_100_L1PLLPD 0x00008000 | ||
2760 | #define TG3_FLG3_PHY_IS_FET 0x00010000 | 2796 | #define TG3_FLG3_PHY_IS_FET 0x00010000 |
2761 | #define TG3_FLG3_ENABLE_RSS 0x00020000 | 2797 | #define TG3_FLG3_ENABLE_RSS 0x00020000 |
2798 | #define TG3_FLG3_4G_DMA_BNDRY_BUG 0x00080000 | ||
2799 | #define TG3_FLG3_40BIT_DMA_LIMIT_BUG 0x00100000 | ||
2800 | #define TG3_FLG3_SHORT_DMA_BUG 0x00200000 | ||
2762 | 2801 | ||
2763 | struct timer_list timer; | 2802 | struct timer_list timer; |
2764 | u16 timer_counter; | 2803 | u16 timer_counter; |
@@ -2825,6 +2864,7 @@ struct tg3 { | |||
2825 | #define PHY_ID_BCM5756 0xbc050ed0 | 2864 | #define PHY_ID_BCM5756 0xbc050ed0 |
2826 | #define PHY_ID_BCM5784 0xbc050fa0 | 2865 | #define PHY_ID_BCM5784 0xbc050fa0 |
2827 | #define PHY_ID_BCM5761 0xbc050fd0 | 2866 | #define PHY_ID_BCM5761 0xbc050fd0 |
2867 | #define PHY_ID_BCM5717 0x5c0d8a00 | ||
2828 | #define PHY_ID_BCM5906 0xdc00ac40 | 2868 | #define PHY_ID_BCM5906 0xdc00ac40 |
2829 | #define PHY_ID_BCM8002 0x60010140 | 2869 | #define PHY_ID_BCM8002 0x60010140 |
2830 | #define PHY_ID_INVALID 0xffffffff | 2870 | #define PHY_ID_INVALID 0xffffffff |
@@ -2834,6 +2874,7 @@ struct tg3 { | |||
2834 | #define PHY_REV_BCM5401_C0 0x6 | 2874 | #define PHY_REV_BCM5401_C0 0x6 |
2835 | #define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */ | 2875 | #define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */ |
2836 | #define TG3_PHY_ID_BCM50610 0x143bd60 | 2876 | #define TG3_PHY_ID_BCM50610 0x143bd60 |
2877 | #define TG3_PHY_ID_BCM50610M 0x143bd70 | ||
2837 | #define TG3_PHY_ID_BCMAC131 0x143bc70 | 2878 | #define TG3_PHY_ID_BCMAC131 0x143bc70 |
2838 | #define TG3_PHY_ID_RTL8211C 0x001cc910 | 2879 | #define TG3_PHY_ID_RTL8211C 0x001cc910 |
2839 | #define TG3_PHY_ID_RTL8201E 0x00008200 | 2880 | #define TG3_PHY_ID_RTL8201E 0x00008200 |
@@ -2865,7 +2906,7 @@ struct tg3 { | |||
2865 | (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \ | 2906 | (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \ |
2866 | (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \ | 2907 | (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \ |
2867 | (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \ | 2908 | (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \ |
2868 | (X) == PHY_ID_BCM8002) | 2909 | (X) == PHY_ID_BCM5717 || (X) == PHY_ID_BCM8002) |
2869 | 2910 | ||
2870 | struct tg3_hw_stats *hw_stats; | 2911 | struct tg3_hw_stats *hw_stats; |
2871 | dma_addr_t stats_mapping; | 2912 | dma_addr_t stats_mapping; |