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Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c32
1 files changed, 25 insertions, 7 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index e03d1ae50c3e..88829eb9568e 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -69,8 +69,8 @@
69 69
70#define DRV_MODULE_NAME "tg3" 70#define DRV_MODULE_NAME "tg3"
71#define PFX DRV_MODULE_NAME ": " 71#define PFX DRV_MODULE_NAME ": "
72#define DRV_MODULE_VERSION "3.52" 72#define DRV_MODULE_VERSION "3.53"
73#define DRV_MODULE_RELDATE "Mar 06, 2006" 73#define DRV_MODULE_RELDATE "Mar 22, 2006"
74 74
75#define TG3_DEF_MAC_MODE 0 75#define TG3_DEF_MAC_MODE 0
76#define TG3_DEF_RX_MODE 0 76#define TG3_DEF_RX_MODE 0
@@ -1148,6 +1148,19 @@ static int tg3_halt_cpu(struct tg3 *, u32);
1148static int tg3_nvram_lock(struct tg3 *); 1148static int tg3_nvram_lock(struct tg3 *);
1149static void tg3_nvram_unlock(struct tg3 *); 1149static void tg3_nvram_unlock(struct tg3 *);
1150 1150
1151static void tg3_power_down_phy(struct tg3 *tp)
1152{
1153 /* The PHY should not be powered down on some chips because
1154 * of bugs.
1155 */
1156 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1157 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1158 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1159 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1160 return;
1161 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1162}
1163
1151static int tg3_set_power_state(struct tg3 *tp, pci_power_t state) 1164static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1152{ 1165{
1153 u32 misc_host_ctrl; 1166 u32 misc_host_ctrl;
@@ -1327,8 +1340,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1327 tg3_writephy(tp, MII_TG3_EXT_CTRL, 1340 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1328 MII_TG3_EXT_CTRL_FORCE_LED_OFF); 1341 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1329 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2); 1342 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1330 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) 1343 tg3_power_down_phy(tp);
1331 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1332 } 1344 }
1333 } 1345 }
1334 1346
@@ -9436,12 +9448,18 @@ static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9436 return NULL; 9448 return NULL;
9437} 9449}
9438 9450
9439/* Since this function may be called in D3-hot power state during
9440 * tg3_init_one(), only config cycles are allowed.
9441 */
9442static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) 9451static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9443{ 9452{
9444 u32 val; 9453 u32 val;
9454 u16 pmcsr;
9455
9456 /* On some early chips the SRAM cannot be accessed in D3hot state,
9457 * so need make sure we're in D0.
9458 */
9459 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9460 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9461 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9462 msleep(1);
9445 9463
9446 /* Make sure register accesses (indirect or otherwise) 9464 /* Make sure register accesses (indirect or otherwise)
9447 * will function correctly. 9465 * will function correctly.