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-rw-r--r--drivers/net/tg3.c170
1 files changed, 132 insertions, 38 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index f2d1dafde087..caf4102b54ce 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -69,8 +69,8 @@
69 69
70#define DRV_MODULE_NAME "tg3" 70#define DRV_MODULE_NAME "tg3"
71#define PFX DRV_MODULE_NAME ": " 71#define PFX DRV_MODULE_NAME ": "
72#define DRV_MODULE_VERSION "3.48" 72#define DRV_MODULE_VERSION "3.49"
73#define DRV_MODULE_RELDATE "Jan 16, 2006" 73#define DRV_MODULE_RELDATE "Feb 2, 2006"
74 74
75#define TG3_DEF_MAC_MODE 0 75#define TG3_DEF_MAC_MODE 0
76#define TG3_DEF_RX_MODE 0 76#define TG3_DEF_RX_MODE 0
@@ -3482,6 +3482,17 @@ static void tg3_reset_task(void *_data)
3482 struct tg3 *tp = _data; 3482 struct tg3 *tp = _data;
3483 unsigned int restart_timer; 3483 unsigned int restart_timer;
3484 3484
3485 tg3_full_lock(tp, 0);
3486 tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3487
3488 if (!netif_running(tp->dev)) {
3489 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3490 tg3_full_unlock(tp);
3491 return;
3492 }
3493
3494 tg3_full_unlock(tp);
3495
3485 tg3_netif_stop(tp); 3496 tg3_netif_stop(tp);
3486 3497
3487 tg3_full_lock(tp, 1); 3498 tg3_full_lock(tp, 1);
@@ -3494,10 +3505,12 @@ static void tg3_reset_task(void *_data)
3494 3505
3495 tg3_netif_start(tp); 3506 tg3_netif_start(tp);
3496 3507
3497 tg3_full_unlock(tp);
3498
3499 if (restart_timer) 3508 if (restart_timer)
3500 mod_timer(&tp->timer, jiffies + 1); 3509 mod_timer(&tp->timer, jiffies + 1);
3510
3511 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3512
3513 tg3_full_unlock(tp);
3501} 3514}
3502 3515
3503static void tg3_tx_timeout(struct net_device *dev) 3516static void tg3_tx_timeout(struct net_device *dev)
@@ -3519,9 +3532,23 @@ static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3519 (base + len + 8 < base)); 3532 (base + len + 8 < base));
3520} 3533}
3521 3534
3535/* Test for DMA addresses > 40-bit */
3536static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3537 int len)
3538{
3539#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3540 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
3541 return (((u64) mapping + len) > DMA_40BIT_MASK);
3542 return 0;
3543#else
3544 return 0;
3545#endif
3546}
3547
3522static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32); 3548static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3523 3549
3524static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb, 3550/* Workaround 4GB and 40-bit hardware DMA bugs. */
3551static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3525 u32 last_plus_one, u32 *start, 3552 u32 last_plus_one, u32 *start,
3526 u32 base_flags, u32 mss) 3553 u32 base_flags, u32 mss)
3527{ 3554{
@@ -3729,6 +3756,9 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3729 if (tg3_4g_overflow_test(mapping, len)) 3756 if (tg3_4g_overflow_test(mapping, len))
3730 would_hit_hwbug = 1; 3757 would_hit_hwbug = 1;
3731 3758
3759 if (tg3_40bit_overflow_test(tp, mapping, len))
3760 would_hit_hwbug = 1;
3761
3732 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) 3762 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3733 tg3_set_txd(tp, entry, mapping, len, 3763 tg3_set_txd(tp, entry, mapping, len,
3734 base_flags, (i == last)|(mss << 1)); 3764 base_flags, (i == last)|(mss << 1));
@@ -3750,7 +3780,7 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3750 /* If the workaround fails due to memory/mapping 3780 /* If the workaround fails due to memory/mapping
3751 * failure, silently drop this packet. 3781 * failure, silently drop this packet.
3752 */ 3782 */
3753 if (tigon3_4gb_hwbug_workaround(tp, skb, last_plus_one, 3783 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
3754 &start, base_flags, mss)) 3784 &start, base_flags, mss))
3755 goto out_unlock; 3785 goto out_unlock;
3756 3786
@@ -6786,6 +6816,13 @@ static int tg3_close(struct net_device *dev)
6786{ 6816{
6787 struct tg3 *tp = netdev_priv(dev); 6817 struct tg3 *tp = netdev_priv(dev);
6788 6818
6819 /* Calling flush_scheduled_work() may deadlock because
6820 * linkwatch_event() may be on the workqueue and it will try to get
6821 * the rtnl_lock which we are holding.
6822 */
6823 while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
6824 msleep(1);
6825
6789 netif_stop_queue(dev); 6826 netif_stop_queue(dev);
6790 6827
6791 del_timer_sync(&tp->timer); 6828 del_timer_sync(&tp->timer);
@@ -9388,6 +9425,15 @@ static int __devinit tg3_is_sun_570X(struct tg3 *tp)
9388 return 0; 9425 return 0;
9389 if (venid == PCI_VENDOR_ID_SUN) 9426 if (venid == PCI_VENDOR_ID_SUN)
9390 return 1; 9427 return 1;
9428
9429 /* TG3 chips onboard the SunBlade-2500 don't have the
9430 * subsystem-vendor-id set to PCI_VENDOR_ID_SUN but they
9431 * are distinguishable from non-Sun variants by being
9432 * named "network" by the firmware. Non-Sun cards will
9433 * show up as being named "ethernet".
9434 */
9435 if (!strcmp(pcp->prom_name, "network"))
9436 return 1;
9391 } 9437 }
9392 return 0; 9438 return 0;
9393} 9439}
@@ -9506,12 +9552,36 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
9506 } 9552 }
9507 } 9553 }
9508 9554
9509 /* Find msi capability. */ 9555 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
9556 * DMA addresses > 40-bit. This bridge may have other additional
9557 * 57xx devices behind it in some 4-port NIC designs for example.
9558 * Any tg3 device found behind the bridge will also need the 40-bit
9559 * DMA workaround.
9560 */
9510 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || 9561 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
9511 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { 9562 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
9512 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS; 9563 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
9564 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
9513 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); 9565 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
9514 } 9566 }
9567 else {
9568 struct pci_dev *bridge = NULL;
9569
9570 do {
9571 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
9572 PCI_DEVICE_ID_SERVERWORKS_EPB,
9573 bridge);
9574 if (bridge && bridge->subordinate &&
9575 (bridge->subordinate->number <=
9576 tp->pdev->bus->number) &&
9577 (bridge->subordinate->subordinate >=
9578 tp->pdev->bus->number)) {
9579 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
9580 pci_dev_put(bridge);
9581 break;
9582 }
9583 } while (bridge);
9584 }
9515 9585
9516 /* Initialize misc host control in PCI block. */ 9586 /* Initialize misc host control in PCI block. */
9517 tp->misc_host_ctrl |= (misc_ctrl_reg & 9587 tp->misc_host_ctrl |= (misc_ctrl_reg &
@@ -10257,7 +10327,14 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
10257 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { 10327 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
10258 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); 10328 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
10259 10329
10260 if (ccval == 0x6 || ccval == 0x7) 10330 /* If the 5704 is behind the EPB bridge, we can
10331 * do the less restrictive ONE_DMA workaround for
10332 * better performance.
10333 */
10334 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
10335 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10336 tp->dma_rwctrl |= 0x8000;
10337 else if (ccval == 0x6 || ccval == 0x7)
10261 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; 10338 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
10262 10339
10263 /* Set bit 23 to enable PCIX hw bug fix */ 10340 /* Set bit 23 to enable PCIX hw bug fix */
@@ -10497,8 +10574,6 @@ static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
10497 strcat(str, "66MHz"); 10574 strcat(str, "66MHz");
10498 else if (clock_ctrl == 6) 10575 else if (clock_ctrl == 6)
10499 strcat(str, "100MHz"); 10576 strcat(str, "100MHz");
10500 else if (clock_ctrl == 7)
10501 strcat(str, "133MHz");
10502 } else { 10577 } else {
10503 strcpy(str, "PCI:"); 10578 strcpy(str, "PCI:");
10504 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) 10579 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
@@ -10579,8 +10654,9 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
10579 unsigned long tg3reg_base, tg3reg_len; 10654 unsigned long tg3reg_base, tg3reg_len;
10580 struct net_device *dev; 10655 struct net_device *dev;
10581 struct tg3 *tp; 10656 struct tg3 *tp;
10582 int i, err, pci_using_dac, pm_cap; 10657 int i, err, pm_cap;
10583 char str[40]; 10658 char str[40];
10659 u64 dma_mask, persist_dma_mask;
10584 10660
10585 if (tg3_version_printed++ == 0) 10661 if (tg3_version_printed++ == 0)
10586 printk(KERN_INFO "%s", version); 10662 printk(KERN_INFO "%s", version);
@@ -10617,26 +10693,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
10617 goto err_out_free_res; 10693 goto err_out_free_res;
10618 } 10694 }
10619 10695
10620 /* Configure DMA attributes. */
10621 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
10622 if (!err) {
10623 pci_using_dac = 1;
10624 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
10625 if (err < 0) {
10626 printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
10627 "for consistent allocations\n");
10628 goto err_out_free_res;
10629 }
10630 } else {
10631 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
10632 if (err) {
10633 printk(KERN_ERR PFX "No usable DMA configuration, "
10634 "aborting.\n");
10635 goto err_out_free_res;
10636 }
10637 pci_using_dac = 0;
10638 }
10639
10640 tg3reg_base = pci_resource_start(pdev, 0); 10696 tg3reg_base = pci_resource_start(pdev, 0);
10641 tg3reg_len = pci_resource_len(pdev, 0); 10697 tg3reg_len = pci_resource_len(pdev, 0);
10642 10698
@@ -10650,8 +10706,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
10650 SET_MODULE_OWNER(dev); 10706 SET_MODULE_OWNER(dev);
10651 SET_NETDEV_DEV(dev, &pdev->dev); 10707 SET_NETDEV_DEV(dev, &pdev->dev);
10652 10708
10653 if (pci_using_dac)
10654 dev->features |= NETIF_F_HIGHDMA;
10655 dev->features |= NETIF_F_LLTX; 10709 dev->features |= NETIF_F_LLTX;
10656#if TG3_VLAN_TAG_USED 10710#if TG3_VLAN_TAG_USED
10657 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; 10711 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
@@ -10736,6 +10790,45 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
10736 goto err_out_iounmap; 10790 goto err_out_iounmap;
10737 } 10791 }
10738 10792
10793 /* The EPB bridge inside 5714, 5715, and 5780 and any
10794 * device behind the EPB cannot support DMA addresses > 40-bit.
10795 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
10796 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
10797 * do DMA address check in tg3_start_xmit().
10798 */
10799 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
10800 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
10801 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
10802 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
10803#ifdef CONFIG_HIGHMEM
10804 dma_mask = DMA_64BIT_MASK;
10805#endif
10806 } else
10807 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
10808
10809 /* Configure DMA attributes. */
10810 if (dma_mask > DMA_32BIT_MASK) {
10811 err = pci_set_dma_mask(pdev, dma_mask);
10812 if (!err) {
10813 dev->features |= NETIF_F_HIGHDMA;
10814 err = pci_set_consistent_dma_mask(pdev,
10815 persist_dma_mask);
10816 if (err < 0) {
10817 printk(KERN_ERR PFX "Unable to obtain 64 bit "
10818 "DMA for consistent allocations\n");
10819 goto err_out_iounmap;
10820 }
10821 }
10822 }
10823 if (err || dma_mask == DMA_32BIT_MASK) {
10824 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
10825 if (err) {
10826 printk(KERN_ERR PFX "No usable DMA configuration, "
10827 "aborting.\n");
10828 goto err_out_iounmap;
10829 }
10830 }
10831
10739 tg3_init_bufmgr_config(tp); 10832 tg3_init_bufmgr_config(tp);
10740 10833
10741#if TG3_TSO_SUPPORT != 0 10834#if TG3_TSO_SUPPORT != 0
@@ -10804,9 +10897,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
10804 } else 10897 } else
10805 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS; 10898 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10806 10899
10807 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
10808 dev->features &= ~NETIF_F_HIGHDMA;
10809
10810 /* flow control autonegotiation is default behavior */ 10900 /* flow control autonegotiation is default behavior */
10811 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; 10901 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10812 10902
@@ -10850,8 +10940,10 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
10850 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0, 10940 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
10851 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0, 10941 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
10852 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0); 10942 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
10853 printk(KERN_INFO "%s: dma_rwctrl[%08x]\n", 10943 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
10854 dev->name, tp->dma_rwctrl); 10944 dev->name, tp->dma_rwctrl,
10945 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
10946 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
10855 10947
10856 return 0; 10948 return 0;
10857 10949
@@ -10880,6 +10972,7 @@ static void __devexit tg3_remove_one(struct pci_dev *pdev)
10880 if (dev) { 10972 if (dev) {
10881 struct tg3 *tp = netdev_priv(dev); 10973 struct tg3 *tp = netdev_priv(dev);
10882 10974
10975 flush_scheduled_work();
10883 unregister_netdev(dev); 10976 unregister_netdev(dev);
10884 if (tp->regs) { 10977 if (tp->regs) {
10885 iounmap(tp->regs); 10978 iounmap(tp->regs);
@@ -10901,6 +10994,7 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
10901 if (!netif_running(dev)) 10994 if (!netif_running(dev))
10902 return 0; 10995 return 0;
10903 10996
10997 flush_scheduled_work();
10904 tg3_netif_stop(tp); 10998 tg3_netif_stop(tp);
10905 10999
10906 del_timer_sync(&tp->timer); 11000 del_timer_sync(&tp->timer);