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path: root/drivers/net/tg3.c
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Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c91
1 files changed, 56 insertions, 35 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index f845837e4aa5..8b21f1ddf543 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -4351,7 +4351,7 @@ static void tg3_tx(struct tg3_napi *tnapi)
4351 struct netdev_queue *txq; 4351 struct netdev_queue *txq;
4352 int index = tnapi - tp->napi; 4352 int index = tnapi - tp->napi;
4353 4353
4354 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) 4354 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4355 index--; 4355 index--;
4356 4356
4357 txq = netdev_get_tx_queue(tp->dev, index); 4357 txq = netdev_get_tx_queue(tp->dev, index);
@@ -5435,7 +5435,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5435 5435
5436 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 5436 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5437 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; 5437 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5438 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) 5438 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5439 tnapi++; 5439 tnapi++;
5440 5440
5441 /* We are running in BH disabled context with netif_tx_lock 5441 /* We are running in BH disabled context with netif_tx_lock
@@ -5639,7 +5639,7 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5639 5639
5640 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 5640 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5641 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; 5641 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5642 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) 5642 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5643 tnapi++; 5643 tnapi++;
5644 5644
5645 /* We are running in BH disabled context with netif_tx_lock 5645 /* We are running in BH disabled context with netif_tx_lock
@@ -6278,6 +6278,24 @@ static int tg3_alloc_consistent(struct tg3 *tp)
6278 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); 6278 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6279 sblk = tnapi->hw_status; 6279 sblk = tnapi->hw_status;
6280 6280
6281 /* If multivector TSS is enabled, vector 0 does not handle
6282 * tx interrupts. Don't allocate any resources for it.
6283 */
6284 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6285 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6286 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6287 TG3_TX_RING_SIZE,
6288 GFP_KERNEL);
6289 if (!tnapi->tx_buffers)
6290 goto err_out;
6291
6292 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6293 TG3_TX_RING_BYTES,
6294 &tnapi->tx_desc_mapping);
6295 if (!tnapi->tx_ring)
6296 goto err_out;
6297 }
6298
6281 /* 6299 /*
6282 * When RSS is enabled, the status block format changes 6300 * When RSS is enabled, the status block format changes
6283 * slightly. The "rx_jumbo_consumer", "reserved", 6301 * slightly. The "rx_jumbo_consumer", "reserved",
@@ -6318,17 +6336,6 @@ static int tg3_alloc_consistent(struct tg3 *tp)
6318 goto err_out; 6336 goto err_out;
6319 6337
6320 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); 6338 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6321
6322 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6323 TG3_TX_RING_SIZE, GFP_KERNEL);
6324 if (!tnapi->tx_buffers)
6325 goto err_out;
6326
6327 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6328 TG3_TX_RING_BYTES,
6329 &tnapi->tx_desc_mapping);
6330 if (!tnapi->tx_ring)
6331 goto err_out;
6332 } 6339 }
6333 6340
6334 return 0; 6341 return 0;
@@ -7316,19 +7323,21 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7316{ 7323{
7317 int i; 7324 int i;
7318 7325
7319 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) { 7326 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7320 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); 7327 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7321 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); 7328 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7322 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); 7329 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7323
7324 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7325 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7326 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7327 } else { 7330 } else {
7328 tw32(HOSTCC_TXCOL_TICKS, 0); 7331 tw32(HOSTCC_TXCOL_TICKS, 0);
7329 tw32(HOSTCC_TXMAX_FRAMES, 0); 7332 tw32(HOSTCC_TXMAX_FRAMES, 0);
7330 tw32(HOSTCC_TXCOAL_MAXF_INT, 0); 7333 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7334 }
7331 7335
7336 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7337 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7338 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7339 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7340 } else {
7332 tw32(HOSTCC_RXCOL_TICKS, 0); 7341 tw32(HOSTCC_RXCOL_TICKS, 0);
7333 tw32(HOSTCC_RXMAX_FRAMES, 0); 7342 tw32(HOSTCC_RXMAX_FRAMES, 0);
7334 tw32(HOSTCC_RXCOAL_MAXF_INT, 0); 7343 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
@@ -7351,25 +7360,31 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7351 7360
7352 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; 7361 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7353 tw32(reg, ec->rx_coalesce_usecs); 7362 tw32(reg, ec->rx_coalesce_usecs);
7354 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7355 tw32(reg, ec->tx_coalesce_usecs);
7356 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; 7363 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7357 tw32(reg, ec->rx_max_coalesced_frames); 7364 tw32(reg, ec->rx_max_coalesced_frames);
7358 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7359 tw32(reg, ec->tx_max_coalesced_frames);
7360 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; 7365 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7361 tw32(reg, ec->rx_max_coalesced_frames_irq); 7366 tw32(reg, ec->rx_max_coalesced_frames_irq);
7362 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; 7367
7363 tw32(reg, ec->tx_max_coalesced_frames_irq); 7368 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7369 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7370 tw32(reg, ec->tx_coalesce_usecs);
7371 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7372 tw32(reg, ec->tx_max_coalesced_frames);
7373 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7374 tw32(reg, ec->tx_max_coalesced_frames_irq);
7375 }
7364 } 7376 }
7365 7377
7366 for (; i < tp->irq_max - 1; i++) { 7378 for (; i < tp->irq_max - 1; i++) {
7367 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); 7379 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7368 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7369 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); 7380 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7370 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7371 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); 7381 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7372 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); 7382
7383 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7384 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7385 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7386 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7387 }
7373 } 7388 }
7374} 7389}
7375 7390
@@ -7470,17 +7485,19 @@ static void tg3_rings_reset(struct tg3 *tp)
7470 /* Clear status block in ram. */ 7485 /* Clear status block in ram. */
7471 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); 7486 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7472 7487
7473 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, 7488 if (tnapi->tx_ring) {
7474 (TG3_TX_RING_SIZE << 7489 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7475 BDINFO_FLAGS_MAXLEN_SHIFT), 7490 (TG3_TX_RING_SIZE <<
7476 NIC_SRAM_TX_BUFFER_DESC); 7491 BDINFO_FLAGS_MAXLEN_SHIFT),
7492 NIC_SRAM_TX_BUFFER_DESC);
7493 txrcb += TG3_BDINFO_SIZE;
7494 }
7477 7495
7478 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, 7496 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7479 (TG3_RX_RCB_RING_SIZE(tp) << 7497 (TG3_RX_RCB_RING_SIZE(tp) <<
7480 BDINFO_FLAGS_MAXLEN_SHIFT), 0); 7498 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7481 7499
7482 stblk += 8; 7500 stblk += 8;
7483 txrcb += TG3_BDINFO_SIZE;
7484 rxrcb += TG3_BDINFO_SIZE; 7501 rxrcb += TG3_BDINFO_SIZE;
7485 } 7502 }
7486} 7503}
@@ -8023,7 +8040,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8023 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) 8040 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8024 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); 8041 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8025 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; 8042 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8026 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) 8043 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8027 val |= SNDBDI_MODE_MULTI_TXQ_EN; 8044 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8028 tw32(SNDBDI_MODE, val); 8045 tw32(SNDBDI_MODE, val);
8029 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); 8046 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
@@ -8631,7 +8648,11 @@ static bool tg3_enable_msix(struct tg3 *tp)
8631 for (i = 0; i < tp->irq_max; i++) 8648 for (i = 0; i < tp->irq_max; i++)
8632 tp->napi[i].irq_vec = msix_ent[i].vector; 8649 tp->napi[i].irq_vec = msix_ent[i].vector;
8633 8650
8634 tp->dev->real_num_tx_queues = tp->irq_cnt - 1; 8651 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8652 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8653 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8654 } else
8655 tp->dev->real_num_tx_queues = 1;
8635 8656
8636 return true; 8657 return true;
8637} 8658}