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path: root/drivers/net/tg3.c
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Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 606703cf9618..5e74a19e7c12 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -92,7 +92,7 @@
92/* hardware minimum and maximum for a single frame's data payload */ 92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60 93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \ 94#define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500) 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
96 96
97/* These numbers seem to be hard coded in the NIC firmware somehow. 97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place 98 * You can't change the ring sizes, but you can change where you place
@@ -1921,7 +1921,7 @@ out:
1921 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { 1921 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1922 /* Cannot do read-modify-write on 5401 */ 1922 /* Cannot do read-modify-write on 5401 */
1923 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); 1923 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1924 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) { 1924 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1925 u32 phy_reg; 1925 u32 phy_reg;
1926 1926
1927 /* Set bit 14 with read-modify-write to preserve other bits */ 1927 /* Set bit 14 with read-modify-write to preserve other bits */
@@ -1933,7 +1933,7 @@ out:
1933 /* Set phy register 0x10 bit 0 to high fifo elasticity to support 1933 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1934 * jumbo frames transmission. 1934 * jumbo frames transmission.
1935 */ 1935 */
1936 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) { 1936 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1937 u32 phy_reg; 1937 u32 phy_reg;
1938 1938
1939 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg)) 1939 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
@@ -6975,7 +6975,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6975 /* Program the jumbo buffer descriptor ring control 6975 /* Program the jumbo buffer descriptor ring control
6976 * blocks on those devices that have them. 6976 * blocks on those devices that have them.
6977 */ 6977 */
6978 if ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) && 6978 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6979 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { 6979 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6980 /* Setup replenish threshold. */ 6980 /* Setup replenish threshold. */
6981 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8); 6981 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
@@ -12034,7 +12034,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12034 12034
12035 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || 12035 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12036 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) 12036 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12037 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE; 12037 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12038 12038
12039 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, 12039 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12040 &pci_state_reg); 12040 &pci_state_reg);