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path: root/drivers/net/tg3.c
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Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c21
1 files changed, 16 insertions, 5 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 4f9fbe268ec9..482b7df55247 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -595,7 +595,8 @@ static void tg3_switch_clocks(struct tg3 *tp)
595 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); 595 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
596 u32 orig_clock_ctrl; 596 u32 orig_clock_ctrl;
597 597
598 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) 598 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
599 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
599 return; 600 return;
600 601
601 orig_clock_ctrl = clock_ctrl; 602 orig_clock_ctrl = clock_ctrl;
@@ -1400,6 +1401,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1400 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | 1401 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1401 CLOCK_CTRL_PWRDOWN_PLL133, 40); 1402 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1402 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || 1403 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1404 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
1403 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) { 1405 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1404 /* do nothing */ 1406 /* do nothing */
1405 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && 1407 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
@@ -6147,11 +6149,13 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6147 /* This works around an issue with Athlon chipsets on 6149 /* This works around an issue with Athlon chipsets on
6148 * B3 tigon3 silicon. This bit has no effect on any 6150 * B3 tigon3 silicon. This bit has no effect on any
6149 * other revision. But do not set this on PCI Express 6151 * other revision. But do not set this on PCI Express
6150 * chips. 6152 * chips and don't even touch the clocks if the CPMU is present.
6151 */ 6153 */
6152 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) 6154 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6153 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; 6155 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6154 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); 6156 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6157 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6158 }
6155 6159
6156 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && 6160 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6157 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { 6161 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
@@ -10527,6 +10531,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10527 10531
10528 tp->pci_chip_rev_id = (misc_ctrl_reg >> 10532 tp->pci_chip_rev_id = (misc_ctrl_reg >>
10529 MISC_HOST_CTRL_CHIPREV_SHIFT); 10533 MISC_HOST_CTRL_CHIPREV_SHIFT);
10534 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
10535 u32 prod_id_asic_rev;
10536
10537 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
10538 &prod_id_asic_rev);
10539 tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
10540 }
10530 10541
10531 /* Wrong chip ID in 5752 A0. This code can be removed later 10542 /* Wrong chip ID in 5752 A0. This code can be removed later
10532 * as A0 is not in production. 10543 * as A0 is not in production.