diff options
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r-- | drivers/net/tg3.c | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 1e0c9e0dc394..3200c9c5ff5e 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -9581,6 +9581,81 @@ static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) | |||
9581 | } | 9581 | } |
9582 | } | 9582 | } |
9583 | 9583 | ||
9584 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) | ||
9585 | { | ||
9586 | u32 nvcfg1, protect = 0; | ||
9587 | |||
9588 | nvcfg1 = tr32(NVRAM_CFG1); | ||
9589 | |||
9590 | /* NVRAM protection for TPM */ | ||
9591 | if (nvcfg1 & (1 << 27)) { | ||
9592 | tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM; | ||
9593 | protect = 1; | ||
9594 | } | ||
9595 | |||
9596 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | ||
9597 | switch (nvcfg1) { | ||
9598 | case FLASH_5761VENDOR_ATMEL_ADB021D: | ||
9599 | case FLASH_5761VENDOR_ATMEL_ADB041D: | ||
9600 | case FLASH_5761VENDOR_ATMEL_ADB081D: | ||
9601 | case FLASH_5761VENDOR_ATMEL_ADB161D: | ||
9602 | case FLASH_5761VENDOR_ATMEL_MDB021D: | ||
9603 | case FLASH_5761VENDOR_ATMEL_MDB041D: | ||
9604 | case FLASH_5761VENDOR_ATMEL_MDB081D: | ||
9605 | case FLASH_5761VENDOR_ATMEL_MDB161D: | ||
9606 | tp->nvram_jedecnum = JEDEC_ATMEL; | ||
9607 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | ||
9608 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | ||
9609 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | ||
9610 | tp->nvram_pagesize = 256; | ||
9611 | break; | ||
9612 | case FLASH_5761VENDOR_ST_A_M45PE20: | ||
9613 | case FLASH_5761VENDOR_ST_A_M45PE40: | ||
9614 | case FLASH_5761VENDOR_ST_A_M45PE80: | ||
9615 | case FLASH_5761VENDOR_ST_A_M45PE16: | ||
9616 | case FLASH_5761VENDOR_ST_M_M45PE20: | ||
9617 | case FLASH_5761VENDOR_ST_M_M45PE40: | ||
9618 | case FLASH_5761VENDOR_ST_M_M45PE80: | ||
9619 | case FLASH_5761VENDOR_ST_M_M45PE16: | ||
9620 | tp->nvram_jedecnum = JEDEC_ST; | ||
9621 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | ||
9622 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | ||
9623 | tp->nvram_pagesize = 256; | ||
9624 | break; | ||
9625 | } | ||
9626 | |||
9627 | if (protect) { | ||
9628 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | ||
9629 | } else { | ||
9630 | switch (nvcfg1) { | ||
9631 | case FLASH_5761VENDOR_ATMEL_ADB161D: | ||
9632 | case FLASH_5761VENDOR_ATMEL_MDB161D: | ||
9633 | case FLASH_5761VENDOR_ST_A_M45PE16: | ||
9634 | case FLASH_5761VENDOR_ST_M_M45PE16: | ||
9635 | tp->nvram_size = 0x100000; | ||
9636 | break; | ||
9637 | case FLASH_5761VENDOR_ATMEL_ADB081D: | ||
9638 | case FLASH_5761VENDOR_ATMEL_MDB081D: | ||
9639 | case FLASH_5761VENDOR_ST_A_M45PE80: | ||
9640 | case FLASH_5761VENDOR_ST_M_M45PE80: | ||
9641 | tp->nvram_size = 0x80000; | ||
9642 | break; | ||
9643 | case FLASH_5761VENDOR_ATMEL_ADB041D: | ||
9644 | case FLASH_5761VENDOR_ATMEL_MDB041D: | ||
9645 | case FLASH_5761VENDOR_ST_A_M45PE40: | ||
9646 | case FLASH_5761VENDOR_ST_M_M45PE40: | ||
9647 | tp->nvram_size = 0x40000; | ||
9648 | break; | ||
9649 | case FLASH_5761VENDOR_ATMEL_ADB021D: | ||
9650 | case FLASH_5761VENDOR_ATMEL_MDB021D: | ||
9651 | case FLASH_5761VENDOR_ST_A_M45PE20: | ||
9652 | case FLASH_5761VENDOR_ST_M_M45PE20: | ||
9653 | tp->nvram_size = 0x20000; | ||
9654 | break; | ||
9655 | } | ||
9656 | } | ||
9657 | } | ||
9658 | |||
9584 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) | 9659 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) |
9585 | { | 9660 | { |
9586 | tp->nvram_jedecnum = JEDEC_ATMEL; | 9661 | tp->nvram_jedecnum = JEDEC_ATMEL; |
@@ -9623,6 +9698,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp) | |||
9623 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | 9698 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
9624 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) | 9699 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) |
9625 | tg3_get_5787_nvram_info(tp); | 9700 | tg3_get_5787_nvram_info(tp); |
9701 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | ||
9702 | tg3_get_5761_nvram_info(tp); | ||
9626 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | 9703 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
9627 | tg3_get_5906_nvram_info(tp); | 9704 | tg3_get_5906_nvram_info(tp); |
9628 | else | 9705 | else |
@@ -9700,6 +9777,7 @@ static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |||
9700 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | 9777 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && |
9701 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | 9778 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && |
9702 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | 9779 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && |
9780 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | ||
9703 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | 9781 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
9704 | 9782 | ||
9705 | addr = ((addr / tp->nvram_pagesize) << | 9783 | addr = ((addr / tp->nvram_pagesize) << |
@@ -9714,6 +9792,7 @@ static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |||
9714 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | 9792 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && |
9715 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | 9793 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && |
9716 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | 9794 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && |
9795 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | ||
9717 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | 9796 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
9718 | 9797 | ||
9719 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | 9798 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * |