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-rw-r--r--drivers/net/tg3.c679
1 files changed, 248 insertions, 431 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 22cf1c446de3..460a0c22b318 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -67,8 +67,8 @@
67#include "tg3.h" 67#include "tg3.h"
68 68
69#define DRV_MODULE_NAME "tg3" 69#define DRV_MODULE_NAME "tg3"
70#define DRV_MODULE_VERSION "3.108" 70#define DRV_MODULE_VERSION "3.109"
71#define DRV_MODULE_RELDATE "February 17, 2010" 71#define DRV_MODULE_RELDATE "April 2, 2010"
72 72
73#define TG3_DEF_MAC_MODE 0 73#define TG3_DEF_MAC_MODE 0
74#define TG3_DEF_RX_MODE 0 74#define TG3_DEF_RX_MODE 0
@@ -101,7 +101,7 @@
101#define TG3_DEF_RX_RING_PENDING 200 101#define TG3_DEF_RX_RING_PENDING 200
102#define TG3_RX_JUMBO_RING_SIZE 256 102#define TG3_RX_JUMBO_RING_SIZE 256
103#define TG3_DEF_RX_JUMBO_RING_PENDING 100 103#define TG3_DEF_RX_JUMBO_RING_PENDING 100
104#define TG3_RSS_INDIR_TBL_SIZE 128 104#define TG3_RSS_INDIR_TBL_SIZE 128
105 105
106/* Do not place this n-ring entries value into the tp struct itself, 106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et 107 * we really want to expose these constants to GCC so that modulo et
@@ -142,6 +142,8 @@
142#define TG3_RX_JMB_BUFF_RING_SIZE \ 142#define TG3_RX_JMB_BUFF_RING_SIZE \
143 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE) 143 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
144 144
145#define TG3_RSS_MIN_NUM_MSIX_VECS 2
146
145/* minimum number of free TX descriptors required to wake up TX process */ 147/* minimum number of free TX descriptors required to wake up TX process */
146#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) 148#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
147 149
@@ -152,6 +154,8 @@
152 154
153#define TG3_NUM_TEST 6 155#define TG3_NUM_TEST 6
154 156
157#define TG3_FW_UPDATE_TIMEOUT_SEC 5
158
155#define FIRMWARE_TG3 "tigon/tg3.bin" 159#define FIRMWARE_TG3 "tigon/tg3.bin"
156#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" 160#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
157#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" 161#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
@@ -167,8 +171,6 @@ MODULE_FIRMWARE(FIRMWARE_TG3);
167MODULE_FIRMWARE(FIRMWARE_TG3TSO); 171MODULE_FIRMWARE(FIRMWARE_TG3TSO);
168MODULE_FIRMWARE(FIRMWARE_TG3TSO5); 172MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
169 173
170#define TG3_RSS_MIN_NUM_MSIX_VECS 2
171
172static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ 174static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
173module_param(tg3_debug, int, 0); 175module_param(tg3_debug, int, 0);
174MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); 176MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
@@ -496,16 +498,16 @@ static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
496 writel(val, tp->regs + off + GRCMBOX_BASE); 498 writel(val, tp->regs + off + GRCMBOX_BASE);
497} 499}
498 500
499#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) 501#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
500#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) 502#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
501#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) 503#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
502#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) 504#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
503#define tr32_mailbox(reg) tp->read32_mbox(tp, reg) 505#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
504 506
505#define tw32(reg,val) tp->write32(tp, reg, val) 507#define tw32(reg, val) tp->write32(tp, reg, val)
506#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0) 508#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
507#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us)) 509#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
508#define tr32(reg) tp->read32(tp, reg) 510#define tr32(reg) tp->read32(tp, reg)
509 511
510static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) 512static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
511{ 513{
@@ -579,11 +581,11 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
579 return 0; 581 return 0;
580 582
581 switch (locknum) { 583 switch (locknum) {
582 case TG3_APE_LOCK_GRC: 584 case TG3_APE_LOCK_GRC:
583 case TG3_APE_LOCK_MEM: 585 case TG3_APE_LOCK_MEM:
584 break; 586 break;
585 default: 587 default:
586 return -EINVAL; 588 return -EINVAL;
587 } 589 }
588 590
589 off = 4 * locknum; 591 off = 4 * locknum;
@@ -617,11 +619,11 @@ static void tg3_ape_unlock(struct tg3 *tp, int locknum)
617 return; 619 return;
618 620
619 switch (locknum) { 621 switch (locknum) {
620 case TG3_APE_LOCK_GRC: 622 case TG3_APE_LOCK_GRC:
621 case TG3_APE_LOCK_MEM: 623 case TG3_APE_LOCK_MEM:
622 break; 624 break;
623 default: 625 default:
624 return; 626 return;
625 } 627 }
626 628
627 off = 4 * locknum; 629 off = 4 * locknum;
@@ -651,6 +653,7 @@ static void tg3_enable_ints(struct tg3 *tp)
651 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; 653 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
652 for (i = 0; i < tp->irq_cnt; i++) { 654 for (i = 0; i < tp->irq_cnt; i++) {
653 struct tg3_napi *tnapi = &tp->napi[i]; 655 struct tg3_napi *tnapi = &tp->napi[i];
656
654 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); 657 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
655 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) 658 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
656 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); 659 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
@@ -1098,7 +1101,7 @@ static int tg3_mdio_init(struct tg3 *tp)
1098 1101
1099 i = mdiobus_register(tp->mdio_bus); 1102 i = mdiobus_register(tp->mdio_bus);
1100 if (i) { 1103 if (i) {
1101 netdev_warn(tp->dev, "mdiobus_reg failed (0x%x)\n", i); 1104 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1102 mdiobus_free(tp->mdio_bus); 1105 mdiobus_free(tp->mdio_bus);
1103 return i; 1106 return i;
1104 } 1107 }
@@ -1106,7 +1109,7 @@ static int tg3_mdio_init(struct tg3 *tp)
1106 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; 1109 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1107 1110
1108 if (!phydev || !phydev->drv) { 1111 if (!phydev || !phydev->drv) {
1109 netdev_warn(tp->dev, "No PHY devices\n"); 1112 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1110 mdiobus_unregister(tp->mdio_bus); 1113 mdiobus_unregister(tp->mdio_bus);
1111 mdiobus_free(tp->mdio_bus); 1114 mdiobus_free(tp->mdio_bus);
1112 return -ENODEV; 1115 return -ENODEV;
@@ -1437,7 +1440,7 @@ static void tg3_adjust_link(struct net_device *dev)
1437 phydev->speed != tp->link_config.active_speed || 1440 phydev->speed != tp->link_config.active_speed ||
1438 phydev->duplex != tp->link_config.active_duplex || 1441 phydev->duplex != tp->link_config.active_duplex ||
1439 oldflowctrl != tp->link_config.active_flowctrl) 1442 oldflowctrl != tp->link_config.active_flowctrl)
1440 linkmesg = 1; 1443 linkmesg = 1;
1441 1444
1442 tp->link_config.active_speed = phydev->speed; 1445 tp->link_config.active_speed = phydev->speed;
1443 tp->link_config.active_duplex = phydev->duplex; 1446 tp->link_config.active_duplex = phydev->duplex;
@@ -1464,7 +1467,7 @@ static int tg3_phy_init(struct tg3 *tp)
1464 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, 1467 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1465 phydev->dev_flags, phydev->interface); 1468 phydev->dev_flags, phydev->interface);
1466 if (IS_ERR(phydev)) { 1469 if (IS_ERR(phydev)) {
1467 netdev_err(tp->dev, "Could not attach to PHY\n"); 1470 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1468 return PTR_ERR(phydev); 1471 return PTR_ERR(phydev);
1469 } 1472 }
1470 1473
@@ -1855,8 +1858,7 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1855 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { 1858 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1856 /* Set Extended packet length bit for jumbo frames */ 1859 /* Set Extended packet length bit for jumbo frames */
1857 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400); 1860 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1858 } 1861 } else {
1859 else {
1860 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); 1862 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1861 } 1863 }
1862 1864
@@ -1974,8 +1976,7 @@ out:
1974 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f); 1976 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1975 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2); 1977 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1976 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); 1978 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1977 } 1979 } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1978 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1979 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); 1980 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1980 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); 1981 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1981 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) { 1982 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
@@ -2007,8 +2008,8 @@ out:
2007 u32 phy_reg; 2008 u32 phy_reg;
2008 2009
2009 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg)) 2010 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2010 tg3_writephy(tp, MII_TG3_EXT_CTRL, 2011 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2011 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC); 2012 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2012 } 2013 }
2013 2014
2014 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 2015 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
@@ -3425,7 +3426,7 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3425 ap->rxconfig = rx_cfg_reg; 3426 ap->rxconfig = rx_cfg_reg;
3426 ret = ANEG_OK; 3427 ret = ANEG_OK;
3427 3428
3428 switch(ap->state) { 3429 switch (ap->state) {
3429 case ANEG_STATE_UNKNOWN: 3430 case ANEG_STATE_UNKNOWN:
3430 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) 3431 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3431 ap->state = ANEG_STATE_AN_ENABLE; 3432 ap->state = ANEG_STATE_AN_ENABLE;
@@ -3463,11 +3464,10 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3463 /* fallthru */ 3464 /* fallthru */
3464 case ANEG_STATE_RESTART: 3465 case ANEG_STATE_RESTART:
3465 delta = ap->cur_time - ap->link_time; 3466 delta = ap->cur_time - ap->link_time;
3466 if (delta > ANEG_STATE_SETTLE_TIME) { 3467 if (delta > ANEG_STATE_SETTLE_TIME)
3467 ap->state = ANEG_STATE_ABILITY_DETECT_INIT; 3468 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3468 } else { 3469 else
3469 ret = ANEG_TIMER_ENAB; 3470 ret = ANEG_TIMER_ENAB;
3470 }
3471 break; 3471 break;
3472 3472
3473 case ANEG_STATE_DISABLE_LINK_OK: 3473 case ANEG_STATE_DISABLE_LINK_OK:
@@ -3491,9 +3491,8 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3491 break; 3491 break;
3492 3492
3493 case ANEG_STATE_ABILITY_DETECT: 3493 case ANEG_STATE_ABILITY_DETECT:
3494 if (ap->ability_match != 0 && ap->rxconfig != 0) { 3494 if (ap->ability_match != 0 && ap->rxconfig != 0)
3495 ap->state = ANEG_STATE_ACK_DETECT_INIT; 3495 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3496 }
3497 break; 3496 break;
3498 3497
3499 case ANEG_STATE_ACK_DETECT_INIT: 3498 case ANEG_STATE_ACK_DETECT_INIT:
@@ -4171,9 +4170,9 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4171 current_duplex = DUPLEX_FULL; 4170 current_duplex = DUPLEX_FULL;
4172 else 4171 else
4173 current_duplex = DUPLEX_HALF; 4172 current_duplex = DUPLEX_HALF;
4174 } 4173 } else {
4175 else
4176 current_link_up = 0; 4174 current_link_up = 0;
4175 }
4177 } 4176 }
4178 } 4177 }
4179 4178
@@ -4211,6 +4210,7 @@ static void tg3_serdes_parallel_detect(struct tg3 *tp)
4211 tp->serdes_counter--; 4210 tp->serdes_counter--;
4212 return; 4211 return;
4213 } 4212 }
4213
4214 if (!netif_carrier_ok(tp->dev) && 4214 if (!netif_carrier_ok(tp->dev) &&
4215 (tp->link_config.autoneg == AUTONEG_ENABLE)) { 4215 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4216 u32 bmcr; 4216 u32 bmcr;
@@ -4240,10 +4240,9 @@ static void tg3_serdes_parallel_detect(struct tg3 *tp)
4240 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT; 4240 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4241 } 4241 }
4242 } 4242 }
4243 } 4243 } else if (netif_carrier_ok(tp->dev) &&
4244 else if (netif_carrier_ok(tp->dev) && 4244 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4245 (tp->link_config.autoneg == AUTONEG_ENABLE) && 4245 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4246 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4247 u32 phy2; 4246 u32 phy2;
4248 4247
4249 /* Select expansion interrupt status register */ 4248 /* Select expansion interrupt status register */
@@ -4266,13 +4265,12 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4266{ 4265{
4267 int err; 4266 int err;
4268 4267
4269 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { 4268 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
4270 err = tg3_setup_fiber_phy(tp, force_reset); 4269 err = tg3_setup_fiber_phy(tp, force_reset);
4271 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { 4270 else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
4272 err = tg3_setup_fiber_mii_phy(tp, force_reset); 4271 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4273 } else { 4272 else
4274 err = tg3_setup_copper_phy(tp, force_reset); 4273 err = tg3_setup_copper_phy(tp, force_reset);
4275 }
4276 4274
4277 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { 4275 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4278 u32 val, scale; 4276 u32 val, scale;
@@ -4335,8 +4333,11 @@ static void tg3_tx_recover(struct tg3 *tp)
4335 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || 4333 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4336 tp->write32_tx_mbox == tg3_write_indirect_mbox); 4334 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4337 4335
4338 netdev_warn(tp->dev, "The system may be re-ordering memory-mapped I/O cycles to the network device, attempting to recover\n" 4336 netdev_warn(tp->dev,
4339 "Please report the problem to the driver maintainer and include system chipset information.\n"); 4337 "The system may be re-ordering memory-mapped I/O "
4338 "cycles to the network device, attempting to recover. "
4339 "Please report the problem to the driver maintainer "
4340 "and include system chipset information.\n");
4340 4341
4341 spin_lock(&tp->lock); 4342 spin_lock(&tp->lock);
4342 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING; 4343 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
@@ -4516,8 +4517,8 @@ static void tg3_recycle_rx(struct tg3_napi *tnapi,
4516 struct tg3 *tp = tnapi->tp; 4517 struct tg3 *tp = tnapi->tp;
4517 struct tg3_rx_buffer_desc *src_desc, *dest_desc; 4518 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4518 struct ring_info *src_map, *dest_map; 4519 struct ring_info *src_map, *dest_map;
4519 int dest_idx;
4520 struct tg3_rx_prodring_set *spr = &tp->prodring[0]; 4520 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4521 int dest_idx;
4521 4522
4522 switch (opaque_key) { 4523 switch (opaque_key) {
4523 case RXD_OPAQUE_RING_STD: 4524 case RXD_OPAQUE_RING_STD:
@@ -4978,7 +4979,7 @@ static int tg3_poll_msix(struct napi_struct *napi, int budget)
4978 if (unlikely(work_done >= budget)) 4979 if (unlikely(work_done >= budget))
4979 break; 4980 break;
4980 4981
4981 /* tp->last_tag is used in tg3_restart_ints() below 4982 /* tp->last_tag is used in tg3_int_reenable() below
4982 * to tell the hw how much work has been processed, 4983 * to tell the hw how much work has been processed,
4983 * so we must read it before checking for more work. 4984 * so we must read it before checking for more work.
4984 */ 4985 */
@@ -4987,8 +4988,8 @@ static int tg3_poll_msix(struct napi_struct *napi, int budget)
4987 rmb(); 4988 rmb();
4988 4989
4989 /* check for RX/TX work to do */ 4990 /* check for RX/TX work to do */
4990 if (sblk->idx[0].tx_consumer == tnapi->tx_cons && 4991 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4991 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) { 4992 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
4992 napi_complete(napi); 4993 napi_complete(napi);
4993 /* Reenable interrupts. */ 4994 /* Reenable interrupts. */
4994 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); 4995 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
@@ -5260,7 +5261,8 @@ static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5260 5261
5261 err = tg3_init_hw(tp, reset_phy); 5262 err = tg3_init_hw(tp, reset_phy);
5262 if (err) { 5263 if (err) {
5263 netdev_err(tp->dev, "Failed to re-initialize device, aborting\n"); 5264 netdev_err(tp->dev,
5265 "Failed to re-initialize device, aborting\n");
5264 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 5266 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5265 tg3_full_unlock(tp); 5267 tg3_full_unlock(tp);
5266 del_timer_sync(&tp->timer); 5268 del_timer_sync(&tp->timer);
@@ -5492,7 +5494,6 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5492 struct netdev_queue *txq; 5494 struct netdev_queue *txq;
5493 unsigned int i, last; 5495 unsigned int i, last;
5494 5496
5495
5496 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 5497 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5497 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; 5498 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5498 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) 5499 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
@@ -5508,7 +5509,8 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5508 netif_tx_stop_queue(txq); 5509 netif_tx_stop_queue(txq);
5509 5510
5510 /* This is a hard error, log it. */ 5511 /* This is a hard error, log it. */
5511 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 5512 netdev_err(dev,
5513 "BUG! Tx Ring full when queue awake!\n");
5512 } 5514 }
5513 return NETDEV_TX_BUSY; 5515 return NETDEV_TX_BUSY;
5514 } 5516 }
@@ -5552,9 +5554,10 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5552 5554
5553 tcp_hdr(skb)->check = 0; 5555 tcp_hdr(skb)->check = 0;
5554 5556
5555 } 5557 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5556 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5557 base_flags |= TXD_FLAG_TCPUDP_CSUM; 5558 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5559 }
5560
5558#if TG3_VLAN_TAG_USED 5561#if TG3_VLAN_TAG_USED
5559 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb)) 5562 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5560 base_flags |= (TXD_FLAG_VLAN | 5563 base_flags |= (TXD_FLAG_VLAN |
@@ -5695,7 +5698,6 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5695 struct netdev_queue *txq; 5698 struct netdev_queue *txq;
5696 unsigned int i, last; 5699 unsigned int i, last;
5697 5700
5698
5699 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 5701 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5700 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; 5702 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5701 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) 5703 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
@@ -5711,7 +5713,8 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5711 netif_tx_stop_queue(txq); 5713 netif_tx_stop_queue(txq);
5712 5714
5713 /* This is a hard error, log it. */ 5715 /* This is a hard error, log it. */
5714 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 5716 netdev_err(dev,
5717 "BUG! Tx Ring full when queue awake!\n");
5715 } 5718 }
5716 return NETDEV_TX_BUSY; 5719 return NETDEV_TX_BUSY;
5717 } 5720 }
@@ -5924,9 +5927,9 @@ static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5924 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { 5927 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5925 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; 5928 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5926 ethtool_op_set_tso(dev, 0); 5929 ethtool_op_set_tso(dev, 0);
5927 } 5930 } else {
5928 else
5929 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; 5931 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5932 }
5930 } else { 5933 } else {
5931 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) 5934 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5932 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; 5935 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
@@ -6007,7 +6010,7 @@ static void tg3_rx_prodring_free(struct tg3 *tp,
6007 } 6010 }
6008} 6011}
6009 6012
6010/* Initialize tx/rx rings for packet processing. 6013/* Initialize rx rings for packet processing.
6011 * 6014 *
6012 * The chip has been shut down and the driver detached from 6015 * The chip has been shut down and the driver detached from
6013 * the networking, so no interrupts or new tx packets will 6016 * the networking, so no interrupts or new tx packets will
@@ -6058,8 +6061,10 @@ static int tg3_rx_prodring_alloc(struct tg3 *tp,
6058 /* Now allocate fresh SKBs for each rx ring. */ 6061 /* Now allocate fresh SKBs for each rx ring. */
6059 for (i = 0; i < tp->rx_pending; i++) { 6062 for (i = 0; i < tp->rx_pending; i++) {
6060 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) { 6063 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6061 netdev_warn(tp->dev, "Using a smaller RX standard ring, only %d out of %d buffers were allocated successfully\n", 6064 netdev_warn(tp->dev,
6062 i, tp->rx_pending); 6065 "Using a smaller RX standard ring. Only "
6066 "%d out of %d buffers were allocated "
6067 "successfully\n", i, tp->rx_pending);
6063 if (i == 0) 6068 if (i == 0)
6064 goto initfail; 6069 goto initfail;
6065 tp->rx_pending = i; 6070 tp->rx_pending = i;
@@ -6088,8 +6093,10 @@ static int tg3_rx_prodring_alloc(struct tg3 *tp,
6088 6093
6089 for (i = 0; i < tp->rx_jumbo_pending; i++) { 6094 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6090 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) { 6095 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6091 netdev_warn(tp->dev, "Using a smaller RX jumbo ring, only %d out of %d buffers were allocated successfully\n", 6096 netdev_warn(tp->dev,
6092 i, tp->rx_jumbo_pending); 6097 "Using a smaller RX jumbo ring. Only %d "
6098 "out of %d buffers were allocated "
6099 "successfully\n", i, tp->rx_jumbo_pending);
6093 if (i == 0) 6100 if (i == 0)
6094 goto initfail; 6101 goto initfail;
6095 tp->rx_jumbo_pending = i; 6102 tp->rx_jumbo_pending = i;
@@ -6433,8 +6440,9 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int
6433 } 6440 }
6434 6441
6435 if (i == MAX_WAIT_CNT && !silent) { 6442 if (i == MAX_WAIT_CNT && !silent) {
6436 pr_err("tg3_stop_block timed out, ofs=%lx enable_bit=%x\n", 6443 dev_err(&tp->pdev->dev,
6437 ofs, enable_bit); 6444 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6445 ofs, enable_bit);
6438 return -ENODEV; 6446 return -ENODEV;
6439 } 6447 }
6440 6448
@@ -6480,8 +6488,9 @@ static int tg3_abort_hw(struct tg3 *tp, int silent)
6480 break; 6488 break;
6481 } 6489 }
6482 if (i >= MAX_WAIT_CNT) { 6490 if (i >= MAX_WAIT_CNT) {
6483 netdev_err(tp->dev, "%s timed out, TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n", 6491 dev_err(&tp->pdev->dev,
6484 __func__, tr32(MAC_TX_MODE)); 6492 "%s timed out, TX_MODE_ENABLE will not clear "
6493 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6485 err |= -ENODEV; 6494 err |= -ENODEV;
6486 } 6495 }
6487 6496
@@ -6551,35 +6560,35 @@ static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6551 return; 6560 return;
6552 6561
6553 switch (kind) { 6562 switch (kind) {
6554 case RESET_KIND_INIT: 6563 case RESET_KIND_INIT:
6555 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 6564 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6556 APE_HOST_SEG_SIG_MAGIC); 6565 APE_HOST_SEG_SIG_MAGIC);
6557 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, 6566 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6558 APE_HOST_SEG_LEN_MAGIC); 6567 APE_HOST_SEG_LEN_MAGIC);
6559 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); 6568 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6560 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); 6569 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6561 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, 6570 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6562 APE_HOST_DRIVER_ID_MAGIC); 6571 APE_HOST_DRIVER_ID_MAGIC);
6563 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, 6572 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6564 APE_HOST_BEHAV_NO_PHYLOCK); 6573 APE_HOST_BEHAV_NO_PHYLOCK);
6565 6574
6566 event = APE_EVENT_STATUS_STATE_START; 6575 event = APE_EVENT_STATUS_STATE_START;
6567 break; 6576 break;
6568 case RESET_KIND_SHUTDOWN: 6577 case RESET_KIND_SHUTDOWN:
6569 /* With the interface we are currently using, 6578 /* With the interface we are currently using,
6570 * APE does not track driver state. Wiping 6579 * APE does not track driver state. Wiping
6571 * out the HOST SEGMENT SIGNATURE forces 6580 * out the HOST SEGMENT SIGNATURE forces
6572 * the APE to assume OS absent status. 6581 * the APE to assume OS absent status.
6573 */ 6582 */
6574 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); 6583 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6575 6584
6576 event = APE_EVENT_STATUS_STATE_UNLOAD; 6585 event = APE_EVENT_STATUS_STATE_UNLOAD;
6577 break; 6586 break;
6578 case RESET_KIND_SUSPEND: 6587 case RESET_KIND_SUSPEND:
6579 event = APE_EVENT_STATUS_STATE_SUSPEND; 6588 event = APE_EVENT_STATUS_STATE_SUSPEND;
6580 break; 6589 break;
6581 default: 6590 default:
6582 return; 6591 return;
6583 } 6592 }
6584 6593
6585 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; 6594 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
@@ -7156,7 +7165,8 @@ static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_b
7156 7165
7157 if (cpu_base == TX_CPU_BASE && 7166 if (cpu_base == TX_CPU_BASE &&
7158 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 7167 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7159 netdev_err(tp->dev, "%s: Trying to load TX cpu firmware which is 5705\n", 7168 netdev_err(tp->dev,
7169 "%s: Trying to load TX cpu firmware which is 5705\n",
7160 __func__); 7170 __func__);
7161 return -EINVAL; 7171 return -EINVAL;
7162 } 7172 }
@@ -7236,7 +7246,8 @@ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7236 udelay(1000); 7246 udelay(1000);
7237 } 7247 }
7238 if (i >= 5) { 7248 if (i >= 5) {
7239 netdev_err(tp->dev, "tg3_load_firmware fails to set RX CPU PC, is %08x should be %08x\n", 7249 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7250 "should be %08x\n", __func__,
7240 tr32(RX_CPU_BASE + CPU_PC), info.fw_base); 7251 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7241 return -ENODEV; 7252 return -ENODEV;
7242 } 7253 }
@@ -7300,7 +7311,8 @@ static int tg3_load_tso_firmware(struct tg3 *tp)
7300 udelay(1000); 7311 udelay(1000);
7301 } 7312 }
7302 if (i >= 5) { 7313 if (i >= 5) {
7303 netdev_err(tp->dev, "%s fails to set CPU PC, is %08x should be %08x\n", 7314 netdev_err(tp->dev,
7315 "%s fails to set CPU PC, is %08x should be %08x\n",
7304 __func__, tr32(cpu_base + CPU_PC), info.fw_base); 7316 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7305 return -ENODEV; 7317 return -ENODEV;
7306 } 7318 }
@@ -7568,9 +7580,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7568 7580
7569 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); 7581 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7570 7582
7571 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) { 7583 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7572 tg3_abort_hw(tp, 1); 7584 tg3_abort_hw(tp, 1);
7573 }
7574 7585
7575 if (reset_phy) 7586 if (reset_phy)
7576 tg3_phy_reset(tp); 7587 tg3_phy_reset(tp);
@@ -7723,8 +7734,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7723 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); 7734 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7724 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); 7735 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7725 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); 7736 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7726 } 7737 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7727 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7728 int fw_len; 7738 int fw_len;
7729 7739
7730 fw_len = tp->fw_len; 7740 fw_len = tp->fw_len;
@@ -8476,8 +8486,8 @@ static void tg3_timer(unsigned long __opaque)
8476 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, 8486 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8477 FWCMD_NICDRV_ALIVE3); 8487 FWCMD_NICDRV_ALIVE3);
8478 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); 8488 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8479 /* 5 seconds timeout */ 8489 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8480 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5); 8490 TG3_FW_UPDATE_TIMEOUT_SEC);
8481 8491
8482 tg3_generate_fw_event(tp); 8492 tg3_generate_fw_event(tp);
8483 } 8493 }
@@ -8625,8 +8635,9 @@ static int tg3_test_msi(struct tg3 *tp)
8625 return err; 8635 return err;
8626 8636
8627 /* MSI test failed, go back to INTx mode */ 8637 /* MSI test failed, go back to INTx mode */
8628 netdev_warn(tp->dev, "No interrupt was generated using MSI, switching to INTx mode\n" 8638 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8629 "Please report this failure to the PCI maintainer and include system chipset information\n"); 8639 "to INTx mode. Please report this failure to the PCI "
8640 "maintainer and include system chipset information\n");
8630 8641
8631 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); 8642 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8632 8643
@@ -8738,7 +8749,8 @@ static void tg3_ints_init(struct tg3 *tp)
8738 /* All MSI supporting chips should support tagged 8749 /* All MSI supporting chips should support tagged
8739 * status. Assert that this is the case. 8750 * status. Assert that this is the case.
8740 */ 8751 */
8741 netdev_warn(tp->dev, "MSI without TAGGED? Not using MSI\n"); 8752 netdev_warn(tp->dev,
8753 "MSI without TAGGED_STATUS? Not using MSI\n");
8742 goto defcfg; 8754 goto defcfg;
8743 } 8755 }
8744 8756
@@ -8913,236 +8925,6 @@ err_out1:
8913 return err; 8925 return err;
8914} 8926}
8915 8927
8916#if 0
8917/*static*/ void tg3_dump_state(struct tg3 *tp)
8918{
8919 u32 val32, val32_2, val32_3, val32_4, val32_5;
8920 u16 val16;
8921 int i;
8922 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8923
8924 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8925 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8926 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8927 val16, val32);
8928
8929 /* MAC block */
8930 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8931 tr32(MAC_MODE), tr32(MAC_STATUS));
8932 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8933 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8934 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8935 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8936 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8937 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8938
8939 /* Send data initiator control block */
8940 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8941 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8942 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8943 tr32(SNDDATAI_STATSCTRL));
8944
8945 /* Send data completion control block */
8946 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8947
8948 /* Send BD ring selector block */
8949 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8950 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8951
8952 /* Send BD initiator control block */
8953 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8954 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8955
8956 /* Send BD completion control block */
8957 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8958
8959 /* Receive list placement control block */
8960 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8961 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8962 printk(" RCVLPC_STATSCTRL[%08x]\n",
8963 tr32(RCVLPC_STATSCTRL));
8964
8965 /* Receive data and receive BD initiator control block */
8966 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8967 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8968
8969 /* Receive data completion control block */
8970 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8971 tr32(RCVDCC_MODE));
8972
8973 /* Receive BD initiator control block */
8974 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8975 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8976
8977 /* Receive BD completion control block */
8978 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8979 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8980
8981 /* Receive list selector control block */
8982 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8983 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8984
8985 /* Mbuf cluster free block */
8986 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8987 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8988
8989 /* Host coalescing control block */
8990 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8991 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8992 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8993 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8994 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8995 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8996 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8997 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8998 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8999 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
9000 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
9001 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
9002
9003 /* Memory arbiter control block */
9004 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
9005 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
9006
9007 /* Buffer manager control block */
9008 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
9009 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
9010 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
9011 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
9012 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
9013 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
9014 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
9015 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
9016
9017 /* Read DMA control block */
9018 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
9019 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
9020
9021 /* Write DMA control block */
9022 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
9023 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
9024
9025 /* DMA completion block */
9026 printk("DEBUG: DMAC_MODE[%08x]\n",
9027 tr32(DMAC_MODE));
9028
9029 /* GRC block */
9030 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
9031 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
9032 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
9033 tr32(GRC_LOCAL_CTRL));
9034
9035 /* TG3_BDINFOs */
9036 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9037 tr32(RCVDBDI_JUMBO_BD + 0x0),
9038 tr32(RCVDBDI_JUMBO_BD + 0x4),
9039 tr32(RCVDBDI_JUMBO_BD + 0x8),
9040 tr32(RCVDBDI_JUMBO_BD + 0xc));
9041 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9042 tr32(RCVDBDI_STD_BD + 0x0),
9043 tr32(RCVDBDI_STD_BD + 0x4),
9044 tr32(RCVDBDI_STD_BD + 0x8),
9045 tr32(RCVDBDI_STD_BD + 0xc));
9046 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9047 tr32(RCVDBDI_MINI_BD + 0x0),
9048 tr32(RCVDBDI_MINI_BD + 0x4),
9049 tr32(RCVDBDI_MINI_BD + 0x8),
9050 tr32(RCVDBDI_MINI_BD + 0xc));
9051
9052 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9053 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9054 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9055 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9056 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9057 val32, val32_2, val32_3, val32_4);
9058
9059 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9060 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9061 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9062 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9063 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9064 val32, val32_2, val32_3, val32_4);
9065
9066 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9067 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9068 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9069 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9070 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9071 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9072 val32, val32_2, val32_3, val32_4, val32_5);
9073
9074 /* SW status block */
9075 printk(KERN_DEBUG
9076 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9077 sblk->status,
9078 sblk->status_tag,
9079 sblk->rx_jumbo_consumer,
9080 sblk->rx_consumer,
9081 sblk->rx_mini_consumer,
9082 sblk->idx[0].rx_producer,
9083 sblk->idx[0].tx_consumer);
9084
9085 /* SW statistics block */
9086 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9087 ((u32 *)tp->hw_stats)[0],
9088 ((u32 *)tp->hw_stats)[1],
9089 ((u32 *)tp->hw_stats)[2],
9090 ((u32 *)tp->hw_stats)[3]);
9091
9092 /* Mailboxes */
9093 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9094 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9095 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9096 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9097 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9098
9099 /* NIC side send descriptors. */
9100 for (i = 0; i < 6; i++) {
9101 unsigned long txd;
9102
9103 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9104 + (i * sizeof(struct tg3_tx_buffer_desc));
9105 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9106 i,
9107 readl(txd + 0x0), readl(txd + 0x4),
9108 readl(txd + 0x8), readl(txd + 0xc));
9109 }
9110
9111 /* NIC side RX descriptors. */
9112 for (i = 0; i < 6; i++) {
9113 unsigned long rxd;
9114
9115 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9116 + (i * sizeof(struct tg3_rx_buffer_desc));
9117 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9118 i,
9119 readl(rxd + 0x0), readl(rxd + 0x4),
9120 readl(rxd + 0x8), readl(rxd + 0xc));
9121 rxd += (4 * sizeof(u32));
9122 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9123 i,
9124 readl(rxd + 0x0), readl(rxd + 0x4),
9125 readl(rxd + 0x8), readl(rxd + 0xc));
9126 }
9127
9128 for (i = 0; i < 6; i++) {
9129 unsigned long rxd;
9130
9131 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9132 + (i * sizeof(struct tg3_rx_buffer_desc));
9133 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9134 i,
9135 readl(rxd + 0x0), readl(rxd + 0x4),
9136 readl(rxd + 0x8), readl(rxd + 0xc));
9137 rxd += (4 * sizeof(u32));
9138 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9139 i,
9140 readl(rxd + 0x0), readl(rxd + 0x4),
9141 readl(rxd + 0x8), readl(rxd + 0xc));
9142 }
9143}
9144#endif
9145
9146static struct net_device_stats *tg3_get_stats(struct net_device *); 8928static struct net_device_stats *tg3_get_stats(struct net_device *);
9147static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *); 8929static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9148 8930
@@ -9161,9 +8943,6 @@ static int tg3_close(struct net_device *dev)
9161 tg3_phy_stop(tp); 8943 tg3_phy_stop(tp);
9162 8944
9163 tg3_full_lock(tp, 1); 8945 tg3_full_lock(tp, 1);
9164#if 0
9165 tg3_dump_state(tp);
9166#endif
9167 8946
9168 tg3_disable_ints(tp); 8947 tg3_disable_ints(tp);
9169 8948
@@ -9405,9 +9184,8 @@ static inline u32 calc_crc(unsigned char *buf, int len)
9405 9184
9406 reg >>= 1; 9185 reg >>= 1;
9407 9186
9408 if (tmp) { 9187 if (tmp)
9409 reg ^= 0xedb88320; 9188 reg ^= 0xedb88320;
9410 }
9411 } 9189 }
9412 } 9190 }
9413 9191
@@ -9457,14 +9235,14 @@ static void __tg3_set_rx_mode(struct net_device *dev)
9457 tg3_set_multi (tp, 0); 9235 tg3_set_multi (tp, 0);
9458 } else { 9236 } else {
9459 /* Accept one or more multicast(s). */ 9237 /* Accept one or more multicast(s). */
9460 struct dev_mc_list *mclist; 9238 struct netdev_hw_addr *ha;
9461 u32 mc_filter[4] = { 0, }; 9239 u32 mc_filter[4] = { 0, };
9462 u32 regidx; 9240 u32 regidx;
9463 u32 bit; 9241 u32 bit;
9464 u32 crc; 9242 u32 crc;
9465 9243
9466 netdev_for_each_mc_addr(mclist, dev) { 9244 netdev_for_each_mc_addr(ha, dev) {
9467 crc = calc_crc (mclist->dmi_addr, ETH_ALEN); 9245 crc = calc_crc(ha->addr, ETH_ALEN);
9468 bit = ~crc & 0x7f; 9246 bit = ~crc & 0x7f;
9469 regidx = (bit & 0x60) >> 5; 9247 regidx = (bit & 0x60) >> 5;
9470 bit &= 0x1f; 9248 bit &= 0x1f;
@@ -9617,7 +9395,7 @@ static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
9617 memcpy(data, ((char*)&val) + b_offset, b_count); 9395 memcpy(data, ((char*)&val) + b_offset, b_count);
9618 len -= b_count; 9396 len -= b_count;
9619 offset += b_count; 9397 offset += b_count;
9620 eeprom->len += b_count; 9398 eeprom->len += b_count;
9621 } 9399 }
9622 9400
9623 /* read bytes upto the last 4 byte boundary */ 9401 /* read bytes upto the last 4 byte boundary */
@@ -10165,8 +9943,8 @@ static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10165 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { 9943 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10166 if (data != 0) 9944 if (data != 0)
10167 return -EINVAL; 9945 return -EINVAL;
10168 return 0; 9946 return 0;
10169 } 9947 }
10170 9948
10171 spin_lock_bh(&tp->lock); 9949 spin_lock_bh(&tp->lock);
10172 if (data) 9950 if (data)
@@ -10185,8 +9963,8 @@ static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10185 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { 9963 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10186 if (data != 0) 9964 if (data != 0)
10187 return -EINVAL; 9965 return -EINVAL;
10188 return 0; 9966 return 0;
10189 } 9967 }
10190 9968
10191 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) 9969 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10192 ethtool_op_set_tx_ipv6_csum(dev, data); 9970 ethtool_op_set_tx_ipv6_csum(dev, data);
@@ -10361,8 +10139,7 @@ static int tg3_test_nvram(struct tg3 *tp)
10361 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) 10139 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10362 parity[k++] = buf8[i] & msk; 10140 parity[k++] = buf8[i] & msk;
10363 i++; 10141 i++;
10364 } 10142 } else if (i == 16) {
10365 else if (i == 16) {
10366 int l; 10143 int l;
10367 u8 msk; 10144 u8 msk;
10368 10145
@@ -10460,7 +10237,7 @@ static int tg3_test_registers(struct tg3 *tp)
10460 { MAC_ADDR_0_HIGH, 0x0000, 10237 { MAC_ADDR_0_HIGH, 0x0000,
10461 0x00000000, 0x0000ffff }, 10238 0x00000000, 0x0000ffff },
10462 { MAC_ADDR_0_LOW, 0x0000, 10239 { MAC_ADDR_0_LOW, 0x0000,
10463 0x00000000, 0xffffffff }, 10240 0x00000000, 0xffffffff },
10464 { MAC_RX_MTU_SIZE, 0x0000, 10241 { MAC_RX_MTU_SIZE, 0x0000,
10465 0x00000000, 0x0000ffff }, 10242 0x00000000, 0x0000ffff },
10466 { MAC_TX_MODE, 0x0000, 10243 { MAC_TX_MODE, 0x0000,
@@ -10648,7 +10425,8 @@ static int tg3_test_registers(struct tg3 *tp)
10648 10425
10649out: 10426out:
10650 if (netif_msg_hw(tp)) 10427 if (netif_msg_hw(tp))
10651 pr_err("Register test failed at offset %x\n", offset); 10428 netdev_err(tp->dev,
10429 "Register test failed at offset %x\n", offset);
10652 tw32(offset, save_val); 10430 tw32(offset, save_val);
10653 return -EIO; 10431 return -EIO;
10654} 10432}
@@ -10824,9 +10602,9 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10824 MII_TG3_EXT_CTRL_LNK3_LED_MODE); 10602 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10825 } 10603 }
10826 tw32(MAC_MODE, mac_mode); 10604 tw32(MAC_MODE, mac_mode);
10827 } 10605 } else {
10828 else
10829 return -EINVAL; 10606 return -EINVAL;
10607 }
10830 10608
10831 err = -EIO; 10609 err = -EIO;
10832 10610
@@ -11082,7 +10860,7 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11082 return phy_mii_ioctl(phydev, data, cmd); 10860 return phy_mii_ioctl(phydev, data, cmd);
11083 } 10861 }
11084 10862
11085 switch(cmd) { 10863 switch (cmd) {
11086 case SIOCGMIIPHY: 10864 case SIOCGMIIPHY:
11087 data->phy_id = tp->phy_addr; 10865 data->phy_id = tp->phy_addr;
11088 10866
@@ -11775,7 +11553,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
11775 tp->tg3_flags |= TG3_FLAG_NVRAM; 11553 tp->tg3_flags |= TG3_FLAG_NVRAM;
11776 11554
11777 if (tg3_nvram_lock(tp)) { 11555 if (tg3_nvram_lock(tp)) {
11778 netdev_warn(tp->dev, "Cannot get nvram lock, %s failed\n", 11556 netdev_warn(tp->dev,
11557 "Cannot get nvram lock, %s failed\n",
11779 __func__); 11558 __func__);
11780 return; 11559 return;
11781 } 11560 }
@@ -11894,7 +11673,7 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11894 if (ret) 11673 if (ret)
11895 break; 11674 break;
11896 11675
11897 page_off = offset & pagemask; 11676 page_off = offset & pagemask;
11898 size = pagesize; 11677 size = pagesize;
11899 if (len < size) 11678 if (len < size)
11900 size = len; 11679 size = len;
@@ -11922,7 +11701,7 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11922 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | 11701 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11923 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; 11702 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11924 11703
11925 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) 11704 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11926 break; 11705 break;
11927 11706
11928 /* Issue another write enable to start the write. */ 11707 /* Issue another write enable to start the write. */
@@ -11976,7 +11755,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11976 memcpy(&data, buf + i, 4); 11755 memcpy(&data, buf + i, 4);
11977 tw32(NVRAM_WRDATA, be32_to_cpu(data)); 11756 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11978 11757
11979 page_off = offset % tp->nvram_pagesize; 11758 page_off = offset % tp->nvram_pagesize;
11980 11759
11981 phy_addr = tg3_nvram_phys_addr(tp, offset); 11760 phy_addr = tg3_nvram_phys_addr(tp, offset);
11982 11761
@@ -11984,7 +11763,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11984 11763
11985 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; 11764 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11986 11765
11987 if ((page_off == 0) || (i == 0)) 11766 if (page_off == 0 || i == 0)
11988 nvram_cmd |= NVRAM_CMD_FIRST; 11767 nvram_cmd |= NVRAM_CMD_FIRST;
11989 if (page_off == (tp->nvram_pagesize - 4)) 11768 if (page_off == (tp->nvram_pagesize - 4))
11990 nvram_cmd |= NVRAM_CMD_LAST; 11769 nvram_cmd |= NVRAM_CMD_LAST;
@@ -12027,8 +11806,7 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12027 11806
12028 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) { 11807 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12029 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); 11808 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12030 } 11809 } else {
12031 else {
12032 u32 grc_mode; 11810 u32 grc_mode;
12033 11811
12034 ret = tg3_nvram_lock(tp); 11812 ret = tg3_nvram_lock(tp);
@@ -12048,8 +11826,7 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12048 11826
12049 ret = tg3_nvram_write_block_buffered(tp, offset, len, 11827 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12050 buf); 11828 buf);
12051 } 11829 } else {
12052 else {
12053 ret = tg3_nvram_write_block_unbuffered(tp, offset, len, 11830 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12054 buf); 11831 buf);
12055 } 11832 }
@@ -12544,11 +12321,11 @@ skip_phy_reset:
12544 return err; 12321 return err;
12545} 12322}
12546 12323
12547static void __devinit tg3_read_partno(struct tg3 *tp) 12324static void __devinit tg3_read_vpd(struct tg3 *tp)
12548{ 12325{
12549 unsigned char vpd_data[TG3_NVM_VPD_LEN]; /* in little-endian format */ 12326 u8 vpd_data[TG3_NVM_VPD_LEN];
12550 unsigned int block_end, rosize, len; 12327 unsigned int block_end, rosize, len;
12551 int i = 0; 12328 int j, i = 0;
12552 u32 magic; 12329 u32 magic;
12553 12330
12554 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || 12331 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
@@ -12597,6 +12374,32 @@ static void __devinit tg3_read_partno(struct tg3 *tp)
12597 if (block_end > TG3_NVM_VPD_LEN) 12374 if (block_end > TG3_NVM_VPD_LEN)
12598 goto out_not_found; 12375 goto out_not_found;
12599 12376
12377 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12378 PCI_VPD_RO_KEYWORD_MFR_ID);
12379 if (j > 0) {
12380 len = pci_vpd_info_field_size(&vpd_data[j]);
12381
12382 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12383 if (j + len > block_end || len != 4 ||
12384 memcmp(&vpd_data[j], "1028", 4))
12385 goto partno;
12386
12387 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12388 PCI_VPD_RO_KEYWORD_VENDOR0);
12389 if (j < 0)
12390 goto partno;
12391
12392 len = pci_vpd_info_field_size(&vpd_data[j]);
12393
12394 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12395 if (j + len > block_end)
12396 goto partno;
12397
12398 memcpy(tp->fw_ver, &vpd_data[j], len);
12399 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12400 }
12401
12402partno:
12600 i = pci_vpd_find_info_keyword(vpd_data, i, rosize, 12403 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12601 PCI_VPD_RO_KEYWORD_PARTNO); 12404 PCI_VPD_RO_KEYWORD_PARTNO);
12602 if (i < 0) 12405 if (i < 0)
@@ -12666,7 +12469,7 @@ static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12666static void __devinit tg3_read_bc_ver(struct tg3 *tp) 12469static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12667{ 12470{
12668 u32 val, offset, start, ver_offset; 12471 u32 val, offset, start, ver_offset;
12669 int i; 12472 int i, dst_off;
12670 bool newver = false; 12473 bool newver = false;
12671 12474
12672 if (tg3_nvram_read(tp, 0xc, &offset) || 12475 if (tg3_nvram_read(tp, 0xc, &offset) ||
@@ -12686,8 +12489,11 @@ static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12686 newver = true; 12489 newver = true;
12687 } 12490 }
12688 12491
12492 dst_off = strlen(tp->fw_ver);
12493
12689 if (newver) { 12494 if (newver) {
12690 if (tg3_nvram_read(tp, offset + 8, &ver_offset)) 12495 if (TG3_VER_SIZE - dst_off < 16 ||
12496 tg3_nvram_read(tp, offset + 8, &ver_offset))
12691 return; 12497 return;
12692 12498
12693 offset = offset + ver_offset - start; 12499 offset = offset + ver_offset - start;
@@ -12696,7 +12502,7 @@ static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12696 if (tg3_nvram_read_be32(tp, offset + i, &v)) 12502 if (tg3_nvram_read_be32(tp, offset + i, &v))
12697 return; 12503 return;
12698 12504
12699 memcpy(tp->fw_ver + i, &v, sizeof(v)); 12505 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12700 } 12506 }
12701 } else { 12507 } else {
12702 u32 major, minor; 12508 u32 major, minor;
@@ -12707,7 +12513,8 @@ static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12707 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> 12513 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12708 TG3_NVM_BCVER_MAJSFT; 12514 TG3_NVM_BCVER_MAJSFT;
12709 minor = ver_offset & TG3_NVM_BCVER_MINMSK; 12515 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12710 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor); 12516 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12517 "v%d.%02d", major, minor);
12711 } 12518 }
12712} 12519}
12713 12520
@@ -12731,9 +12538,7 @@ static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12731{ 12538{
12732 u32 offset, major, minor, build; 12539 u32 offset, major, minor, build;
12733 12540
12734 tp->fw_ver[0] = 's'; 12541 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12735 tp->fw_ver[1] = 'b';
12736 tp->fw_ver[2] = '\0';
12737 12542
12738 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) 12543 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12739 return; 12544 return;
@@ -12770,11 +12575,14 @@ static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12770 if (minor > 99 || build > 26) 12575 if (minor > 99 || build > 26)
12771 return; 12576 return;
12772 12577
12773 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor); 12578 offset = strlen(tp->fw_ver);
12579 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12580 " v%d.%02d", major, minor);
12774 12581
12775 if (build > 0) { 12582 if (build > 0) {
12776 tp->fw_ver[8] = 'a' + build - 1; 12583 offset = strlen(tp->fw_ver);
12777 tp->fw_ver[9] = '\0'; 12584 if (offset < TG3_VER_SIZE - 1)
12585 tp->fw_ver[offset] = 'a' + build - 1;
12778 } 12586 }
12779} 12587}
12780 12588
@@ -12861,12 +12669,13 @@ static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12861static void __devinit tg3_read_fw_ver(struct tg3 *tp) 12669static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12862{ 12670{
12863 u32 val; 12671 u32 val;
12672 bool vpd_vers = false;
12864 12673
12865 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) { 12674 if (tp->fw_ver[0] != 0)
12866 tp->fw_ver[0] = 's'; 12675 vpd_vers = true;
12867 tp->fw_ver[1] = 'b';
12868 tp->fw_ver[2] = '\0';
12869 12676
12677 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12678 strcat(tp->fw_ver, "sb");
12870 return; 12679 return;
12871 } 12680 }
12872 12681
@@ -12883,11 +12692,12 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12883 return; 12692 return;
12884 12693
12885 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || 12694 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12886 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) 12695 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12887 return; 12696 goto done;
12888 12697
12889 tg3_read_mgmtfw_ver(tp); 12698 tg3_read_mgmtfw_ver(tp);
12890 12699
12700done:
12891 tp->fw_ver[TG3_VER_SIZE - 1] = 0; 12701 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12892} 12702}
12893 12703
@@ -12897,9 +12707,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12897{ 12707{
12898 static struct pci_device_id write_reorder_chipsets[] = { 12708 static struct pci_device_id write_reorder_chipsets[] = {
12899 { PCI_DEVICE(PCI_VENDOR_ID_AMD, 12709 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12900 PCI_DEVICE_ID_AMD_FE_GATE_700C) }, 12710 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12901 { PCI_DEVICE(PCI_VENDOR_ID_AMD, 12711 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12902 PCI_DEVICE_ID_AMD_8131_BRIDGE) }, 12712 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12903 { PCI_DEVICE(PCI_VENDOR_ID_VIA, 12713 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12904 PCI_DEVICE_ID_VIA_8385_0) }, 12714 PCI_DEVICE_ID_VIA_8385_0) },
12905 { }, 12715 { },
@@ -13065,8 +12875,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13065 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS; 12875 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13066 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; 12876 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13067 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); 12877 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13068 } 12878 } else {
13069 else {
13070 struct pci_dev *bridge = NULL; 12879 struct pci_dev *bridge = NULL;
13071 12880
13072 do { 12881 do {
@@ -13188,8 +12997,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13188 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG; 12997 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13189 12998
13190 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || 12999 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13191 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || 13000 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13192 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG)) 13001 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13193 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE; 13002 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13194 13003
13195 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, 13004 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
@@ -13223,7 +13032,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13223 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { 13032 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13224 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); 13033 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13225 if (!tp->pcix_cap) { 13034 if (!tp->pcix_cap) {
13226 pr_err("Cannot find PCI-X capability, aborting\n"); 13035 dev_err(&tp->pdev->dev,
13036 "Cannot find PCI-X capability, aborting\n");
13227 return -EIO; 13037 return -EIO;
13228 } 13038 }
13229 13039
@@ -13420,7 +13230,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13420 /* Force the chip into D0. */ 13230 /* Force the chip into D0. */
13421 err = tg3_set_power_state(tp, PCI_D0); 13231 err = tg3_set_power_state(tp, PCI_D0);
13422 if (err) { 13232 if (err) {
13423 pr_err("(%s) transition to D0 failed\n", pci_name(tp->pdev)); 13233 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13424 return err; 13234 return err;
13425 } 13235 }
13426 13236
@@ -13594,13 +13404,12 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13594 13404
13595 err = tg3_phy_probe(tp); 13405 err = tg3_phy_probe(tp);
13596 if (err) { 13406 if (err) {
13597 pr_err("(%s) phy probe failed, err %d\n", 13407 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13598 pci_name(tp->pdev), err);
13599 /* ... but do not return immediately ... */ 13408 /* ... but do not return immediately ... */
13600 tg3_mdio_fini(tp); 13409 tg3_mdio_fini(tp);
13601 } 13410 }
13602 13411
13603 tg3_read_partno(tp); 13412 tg3_read_vpd(tp);
13604 tg3_read_fw_ver(tp); 13413 tg3_read_fw_ver(tp);
13605 13414
13606 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { 13415 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
@@ -13964,11 +13773,10 @@ static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dm
13964 } 13773 }
13965 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); 13774 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13966 13775
13967 if (to_device) { 13776 if (to_device)
13968 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); 13777 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13969 } else { 13778 else
13970 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); 13779 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13971 }
13972 13780
13973 ret = -ENODEV; 13781 ret = -ENODEV;
13974 for (i = 0; i < 40; i++) { 13782 for (i = 0; i < 40; i++) {
@@ -14104,8 +13912,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
14104 /* Send the buffer to the chip. */ 13912 /* Send the buffer to the chip. */
14105 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); 13913 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14106 if (ret) { 13914 if (ret) {
14107 pr_err("tg3_test_dma() Write the buffer failed %d\n", 13915 dev_err(&tp->pdev->dev,
14108 ret); 13916 "%s: Buffer write failed. err = %d\n",
13917 __func__, ret);
14109 break; 13918 break;
14110 } 13919 }
14111 13920
@@ -14115,8 +13924,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
14115 u32 val; 13924 u32 val;
14116 tg3_read_mem(tp, 0x2100 + (i*4), &val); 13925 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14117 if (le32_to_cpu(val) != p[i]) { 13926 if (le32_to_cpu(val) != p[i]) {
14118 pr_err(" tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", 13927 dev_err(&tp->pdev->dev,
14119 val, i); 13928 "%s: Buffer corrupted on device! "
13929 "(%d != %d)\n", __func__, val, i);
14120 /* ret = -ENODEV here? */ 13930 /* ret = -ENODEV here? */
14121 } 13931 }
14122 p[i] = 0; 13932 p[i] = 0;
@@ -14125,9 +13935,8 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
14125 /* Now read it back. */ 13935 /* Now read it back. */
14126 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); 13936 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14127 if (ret) { 13937 if (ret) {
14128 pr_err("tg3_test_dma() Read the buffer failed %d\n", 13938 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14129 ret); 13939 "err = %d\n", __func__, ret);
14130
14131 break; 13940 break;
14132 } 13941 }
14133 13942
@@ -14143,8 +13952,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
14143 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); 13952 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14144 break; 13953 break;
14145 } else { 13954 } else {
14146 pr_err("tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", 13955 dev_err(&tp->pdev->dev,
14147 p[i], i); 13956 "%s: Buffer corrupted on read back! "
13957 "(%d != %d)\n", __func__, p[i], i);
14148 ret = -ENODEV; 13958 ret = -ENODEV;
14149 goto out; 13959 goto out;
14150 } 13960 }
@@ -14171,10 +13981,10 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
14171 if (pci_dev_present(dma_wait_state_chipsets)) { 13981 if (pci_dev_present(dma_wait_state_chipsets)) {
14172 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; 13982 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14173 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; 13983 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14174 } 13984 } else {
14175 else
14176 /* Safe to use the calculated DMA boundary. */ 13985 /* Safe to use the calculated DMA boundary. */
14177 tp->dma_rwctrl = saved_dma_rwctrl; 13986 tp->dma_rwctrl = saved_dma_rwctrl;
13987 }
14178 13988
14179 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); 13989 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14180 } 13990 }
@@ -14436,13 +14246,13 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14436 14246
14437 err = pci_enable_device(pdev); 14247 err = pci_enable_device(pdev);
14438 if (err) { 14248 if (err) {
14439 pr_err("Cannot enable PCI device, aborting\n"); 14249 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14440 return err; 14250 return err;
14441 } 14251 }
14442 14252
14443 err = pci_request_regions(pdev, DRV_MODULE_NAME); 14253 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14444 if (err) { 14254 if (err) {
14445 pr_err("Cannot obtain PCI resources, aborting\n"); 14255 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14446 goto err_out_disable_pdev; 14256 goto err_out_disable_pdev;
14447 } 14257 }
14448 14258
@@ -14451,14 +14261,15 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14451 /* Find power-management capability. */ 14261 /* Find power-management capability. */
14452 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 14262 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14453 if (pm_cap == 0) { 14263 if (pm_cap == 0) {
14454 pr_err("Cannot find PowerManagement capability, aborting\n"); 14264 dev_err(&pdev->dev,
14265 "Cannot find Power Management capability, aborting\n");
14455 err = -EIO; 14266 err = -EIO;
14456 goto err_out_free_res; 14267 goto err_out_free_res;
14457 } 14268 }
14458 14269
14459 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); 14270 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14460 if (!dev) { 14271 if (!dev) {
14461 pr_err("Etherdev alloc failed, aborting\n"); 14272 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14462 err = -ENOMEM; 14273 err = -ENOMEM;
14463 goto err_out_free_res; 14274 goto err_out_free_res;
14464 } 14275 }
@@ -14508,7 +14319,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14508 14319
14509 tp->regs = pci_ioremap_bar(pdev, BAR_0); 14320 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14510 if (!tp->regs) { 14321 if (!tp->regs) {
14511 netdev_err(dev, "Cannot map device registers, aborting\n"); 14322 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14512 err = -ENOMEM; 14323 err = -ENOMEM;
14513 goto err_out_free_dev; 14324 goto err_out_free_dev;
14514 } 14325 }
@@ -14524,7 +14335,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14524 14335
14525 err = tg3_get_invariants(tp); 14336 err = tg3_get_invariants(tp);
14526 if (err) { 14337 if (err) {
14527 netdev_err(dev, "Problem fetching invariants of chip, aborting\n"); 14338 dev_err(&pdev->dev,
14339 "Problem fetching invariants of chip, aborting\n");
14528 goto err_out_iounmap; 14340 goto err_out_iounmap;
14529 } 14341 }
14530 14342
@@ -14559,7 +14371,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14559 err = pci_set_consistent_dma_mask(pdev, 14371 err = pci_set_consistent_dma_mask(pdev,
14560 persist_dma_mask); 14372 persist_dma_mask);
14561 if (err < 0) { 14373 if (err < 0) {
14562 netdev_err(dev, "Unable to obtain 64 bit DMA for consistent allocations\n"); 14374 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14375 "DMA for consistent allocations\n");
14563 goto err_out_iounmap; 14376 goto err_out_iounmap;
14564 } 14377 }
14565 } 14378 }
@@ -14567,7 +14380,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14567 if (err || dma_mask == DMA_BIT_MASK(32)) { 14380 if (err || dma_mask == DMA_BIT_MASK(32)) {
14568 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 14381 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14569 if (err) { 14382 if (err) {
14570 netdev_err(dev, "No usable DMA configuration, aborting\n"); 14383 dev_err(&pdev->dev,
14384 "No usable DMA configuration, aborting\n");
14571 goto err_out_iounmap; 14385 goto err_out_iounmap;
14572 } 14386 }
14573 } 14387 }
@@ -14616,14 +14430,16 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14616 14430
14617 err = tg3_get_device_address(tp); 14431 err = tg3_get_device_address(tp);
14618 if (err) { 14432 if (err) {
14619 netdev_err(dev, "Could not obtain valid ethernet address, aborting\n"); 14433 dev_err(&pdev->dev,
14434 "Could not obtain valid ethernet address, aborting\n");
14620 goto err_out_iounmap; 14435 goto err_out_iounmap;
14621 } 14436 }
14622 14437
14623 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { 14438 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14624 tp->aperegs = pci_ioremap_bar(pdev, BAR_2); 14439 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14625 if (!tp->aperegs) { 14440 if (!tp->aperegs) {
14626 netdev_err(dev, "Cannot map APE registers, aborting\n"); 14441 dev_err(&pdev->dev,
14442 "Cannot map APE registers, aborting\n");
14627 err = -ENOMEM; 14443 err = -ENOMEM;
14628 goto err_out_iounmap; 14444 goto err_out_iounmap;
14629 } 14445 }
@@ -14647,7 +14463,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14647 14463
14648 err = tg3_test_dma(tp); 14464 err = tg3_test_dma(tp);
14649 if (err) { 14465 if (err) {
14650 netdev_err(dev, "DMA engine test failed, aborting\n"); 14466 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14651 goto err_out_apeunmap; 14467 goto err_out_apeunmap;
14652 } 14468 }
14653 14469
@@ -14708,7 +14524,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14708 14524
14709 err = register_netdev(dev); 14525 err = register_netdev(dev);
14710 if (err) { 14526 if (err) {
14711 netdev_err(dev, "Cannot register net device, aborting\n"); 14527 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14712 goto err_out_apeunmap; 14528 goto err_out_apeunmap;
14713 } 14529 }
14714 14530
@@ -14721,11 +14537,12 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14721 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) { 14537 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14722 struct phy_device *phydev; 14538 struct phy_device *phydev;
14723 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; 14539 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14724 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", 14540 netdev_info(dev,
14541 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14725 phydev->drv->name, dev_name(&phydev->dev)); 14542 phydev->drv->name, dev_name(&phydev->dev));
14726 } else 14543 } else
14727 netdev_info(dev, "attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n", 14544 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14728 tg3_phy_string(tp), 14545 "(WireSpeed[%d])\n", tg3_phy_string(tp),
14729 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" : 14546 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14730 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" : 14547 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14731 "10/100/1000Base-T")), 14548 "10/100/1000Base-T")),
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 04:07:57 -0500