aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/tg3.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c87
1 files changed, 32 insertions, 55 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 633c128a6228..d2439b85a790 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1982,8 +1982,6 @@ static void tg3_power_down_phy(struct tg3 *tp)
1982static int tg3_set_power_state(struct tg3 *tp, pci_power_t state) 1982static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1983{ 1983{
1984 u32 misc_host_ctrl; 1984 u32 misc_host_ctrl;
1985 u16 power_control, power_caps;
1986 int pm = tp->pm_cap;
1987 1985
1988 /* Make sure register accesses (indirect or otherwise) 1986 /* Make sure register accesses (indirect or otherwise)
1989 * will function correctly. 1987 * will function correctly.
@@ -1992,18 +1990,10 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1992 TG3PCI_MISC_HOST_CTRL, 1990 TG3PCI_MISC_HOST_CTRL,
1993 tp->misc_host_ctrl); 1991 tp->misc_host_ctrl);
1994 1992
1995 pci_read_config_word(tp->pdev,
1996 pm + PCI_PM_CTRL,
1997 &power_control);
1998 power_control |= PCI_PM_CTRL_PME_STATUS;
1999 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
2000 switch (state) { 1993 switch (state) {
2001 case PCI_D0: 1994 case PCI_D0:
2002 power_control |= 0; 1995 pci_enable_wake(tp->pdev, state, false);
2003 pci_write_config_word(tp->pdev, 1996 pci_set_power_state(tp->pdev, PCI_D0);
2004 pm + PCI_PM_CTRL,
2005 power_control);
2006 udelay(100); /* Delay after power state change */
2007 1997
2008 /* Switch out of Vaux if it is a NIC */ 1998 /* Switch out of Vaux if it is a NIC */
2009 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) 1999 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
@@ -2012,26 +2002,15 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2012 return 0; 2002 return 0;
2013 2003
2014 case PCI_D1: 2004 case PCI_D1:
2015 power_control |= 1;
2016 break;
2017
2018 case PCI_D2: 2005 case PCI_D2:
2019 power_control |= 2;
2020 break;
2021
2022 case PCI_D3hot: 2006 case PCI_D3hot:
2023 power_control |= 3;
2024 break; 2007 break;
2025 2008
2026 default: 2009 default:
2027 printk(KERN_WARNING PFX "%s: Invalid power state (%d) " 2010 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2028 "requested.\n", 2011 tp->dev->name, state);
2029 tp->dev->name, state);
2030 return -EINVAL; 2012 return -EINVAL;
2031 } 2013 }
2032
2033 power_control |= PCI_PM_CTRL_PME_ENABLE;
2034
2035 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); 2014 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2036 tw32(TG3PCI_MISC_HOST_CTRL, 2015 tw32(TG3PCI_MISC_HOST_CTRL,
2037 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); 2016 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
@@ -2109,8 +2088,6 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2109 WOL_DRV_WOL | 2088 WOL_DRV_WOL |
2110 WOL_SET_MAGIC_PKT); 2089 WOL_SET_MAGIC_PKT);
2111 2090
2112 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
2113
2114 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) { 2091 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
2115 u32 mac_mode; 2092 u32 mac_mode;
2116 2093
@@ -2143,8 +2120,8 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2143 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) 2120 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2144 tw32(MAC_LED_CTRL, tp->led_ctrl); 2121 tw32(MAC_LED_CTRL, tp->led_ctrl);
2145 2122
2146 if (((power_caps & PCI_PM_CAP_PME_D3cold) && 2123 if (pci_pme_capable(tp->pdev, state) &&
2147 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE))) 2124 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE))
2148 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; 2125 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2149 2126
2150 tw32_f(MAC_MODE, mac_mode); 2127 tw32_f(MAC_MODE, mac_mode);
@@ -2236,9 +2213,11 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2236 2213
2237 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); 2214 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2238 2215
2216 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
2217 pci_enable_wake(tp->pdev, state, true);
2218
2239 /* Finally, set the new power state. */ 2219 /* Finally, set the new power state. */
2240 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control); 2220 pci_set_power_state(tp->pdev, state);
2241 udelay(100); /* Delay after power state change */
2242 2221
2243 return 0; 2222 return 0;
2244} 2223}
@@ -7708,21 +7687,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7708 */ 7687 */
7709static int tg3_init_hw(struct tg3 *tp, int reset_phy) 7688static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7710{ 7689{
7711 int err;
7712
7713 /* Force the chip into D0. */
7714 err = tg3_set_power_state(tp, PCI_D0);
7715 if (err)
7716 goto out;
7717
7718 tg3_switch_clocks(tp); 7690 tg3_switch_clocks(tp);
7719 7691
7720 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); 7692 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7721 7693
7722 err = tg3_reset_hw(tp, reset_phy); 7694 return tg3_reset_hw(tp, reset_phy);
7723
7724out:
7725 return err;
7726} 7695}
7727 7696
7728#define TG3_STAT_ADD32(PSTAT, REG) \ 7697#define TG3_STAT_ADD32(PSTAT, REG) \
@@ -8037,13 +8006,11 @@ static int tg3_open(struct net_device *dev)
8037 8006
8038 netif_carrier_off(tp->dev); 8007 netif_carrier_off(tp->dev);
8039 8008
8040 tg3_full_lock(tp, 0);
8041
8042 err = tg3_set_power_state(tp, PCI_D0); 8009 err = tg3_set_power_state(tp, PCI_D0);
8043 if (err) { 8010 if (err)
8044 tg3_full_unlock(tp);
8045 return err; 8011 return err;
8046 } 8012
8013 tg3_full_lock(tp, 0);
8047 8014
8048 tg3_disable_ints(tp); 8015 tg3_disable_ints(tp);
8049 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; 8016 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
@@ -9065,7 +9032,8 @@ static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9065{ 9032{
9066 struct tg3 *tp = netdev_priv(dev); 9033 struct tg3 *tp = netdev_priv(dev);
9067 9034
9068 if (tp->tg3_flags & TG3_FLAG_WOL_CAP) 9035 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9036 device_can_wakeup(&tp->pdev->dev))
9069 wol->supported = WAKE_MAGIC; 9037 wol->supported = WAKE_MAGIC;
9070 else 9038 else
9071 wol->supported = 0; 9039 wol->supported = 0;
@@ -9078,18 +9046,22 @@ static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9078static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 9046static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9079{ 9047{
9080 struct tg3 *tp = netdev_priv(dev); 9048 struct tg3 *tp = netdev_priv(dev);
9049 struct device *dp = &tp->pdev->dev;
9081 9050
9082 if (wol->wolopts & ~WAKE_MAGIC) 9051 if (wol->wolopts & ~WAKE_MAGIC)
9083 return -EINVAL; 9052 return -EINVAL;
9084 if ((wol->wolopts & WAKE_MAGIC) && 9053 if ((wol->wolopts & WAKE_MAGIC) &&
9085 !(tp->tg3_flags & TG3_FLAG_WOL_CAP)) 9054 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9086 return -EINVAL; 9055 return -EINVAL;
9087 9056
9088 spin_lock_bh(&tp->lock); 9057 spin_lock_bh(&tp->lock);
9089 if (wol->wolopts & WAKE_MAGIC) 9058 if (wol->wolopts & WAKE_MAGIC) {
9090 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; 9059 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9091 else 9060 device_set_wakeup_enable(dp, true);
9061 } else {
9092 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE; 9062 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9063 device_set_wakeup_enable(dp, false);
9064 }
9093 spin_unlock_bh(&tp->lock); 9065 spin_unlock_bh(&tp->lock);
9094 9066
9095 return 0; 9067 return 0;
@@ -11296,7 +11268,8 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11296 if (val & VCPU_CFGSHDW_ASPM_DBNC) 11268 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11297 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; 11269 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11298 if ((val & VCPU_CFGSHDW_WOL_ENABLE) && 11270 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11299 (val & VCPU_CFGSHDW_WOL_MAGPKT)) 11271 (val & VCPU_CFGSHDW_WOL_MAGPKT) &&
11272 device_may_wakeup(&tp->pdev->dev))
11300 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; 11273 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11301 return; 11274 return;
11302 } 11275 }
@@ -11426,8 +11399,9 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11426 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) 11399 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11427 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP; 11400 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11428 11401
11429 if (tp->tg3_flags & TG3_FLAG_WOL_CAP && 11402 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11430 nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE) 11403 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE) &&
11404 device_may_wakeup(&tp->pdev->dev))
11431 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; 11405 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11432 11406
11433 if (cfg2 & (1 << 17)) 11407 if (cfg2 & (1 << 17))
@@ -13613,6 +13587,7 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13613{ 13587{
13614 struct net_device *dev = pci_get_drvdata(pdev); 13588 struct net_device *dev = pci_get_drvdata(pdev);
13615 struct tg3 *tp = netdev_priv(dev); 13589 struct tg3 *tp = netdev_priv(dev);
13590 pci_power_t target_state;
13616 int err; 13591 int err;
13617 13592
13618 /* PCI register 4 needs to be saved whether netif_running() or not. 13593 /* PCI register 4 needs to be saved whether netif_running() or not.
@@ -13641,7 +13616,9 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13641 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; 13616 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13642 tg3_full_unlock(tp); 13617 tg3_full_unlock(tp);
13643 13618
13644 err = tg3_set_power_state(tp, pci_choose_state(pdev, state)); 13619 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13620
13621 err = tg3_set_power_state(tp, target_state);
13645 if (err) { 13622 if (err) {
13646 int err2; 13623 int err2;
13647 13624