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-rw-r--r--drivers/net/tg3.c372
1 files changed, 239 insertions, 133 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index eb9f8f3638e1..e05849ee9000 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -54,6 +54,9 @@
54#include <asm/prom.h> 54#include <asm/prom.h>
55#endif 55#endif
56 56
57#define BAR_0 0
58#define BAR_2 2
59
57#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) 60#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
58#define TG3_VLAN_TAG_USED 1 61#define TG3_VLAN_TAG_USED 1
59#else 62#else
@@ -66,8 +69,8 @@
66 69
67#define DRV_MODULE_NAME "tg3" 70#define DRV_MODULE_NAME "tg3"
68#define PFX DRV_MODULE_NAME ": " 71#define PFX DRV_MODULE_NAME ": "
69#define DRV_MODULE_VERSION "3.94" 72#define DRV_MODULE_VERSION "3.95"
70#define DRV_MODULE_RELDATE "August 14, 2008" 73#define DRV_MODULE_RELDATE "November 3, 2008"
71 74
72#define TG3_DEF_MAC_MODE 0 75#define TG3_DEF_MAC_MODE 0
73#define TG3_DEF_RX_MODE 0 76#define TG3_DEF_RX_MODE 0
@@ -205,6 +208,8 @@ static struct pci_device_id tg3_pci_tbl[] = {
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, 208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, 209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, 210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)}, 213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
209 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, 214 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
210 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, 215 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
@@ -872,13 +877,48 @@ static int tg3_mdio_reset(struct mii_bus *bp)
872 return 0; 877 return 0;
873} 878}
874 879
875static void tg3_mdio_config(struct tg3 *tp) 880static void tg3_mdio_config_5785(struct tg3 *tp)
876{ 881{
877 u32 val; 882 u32 val;
883 struct phy_device *phydev;
884
885 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
886 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
887 case TG3_PHY_ID_BCM50610:
888 val = MAC_PHYCFG2_50610_LED_MODES;
889 break;
890 case TG3_PHY_ID_BCMAC131:
891 val = MAC_PHYCFG2_AC131_LED_MODES;
892 break;
893 case TG3_PHY_ID_RTL8211C:
894 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
895 break;
896 case TG3_PHY_ID_RTL8201E:
897 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
898 break;
899 default:
900 return;
901 }
902
903 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
904 tw32(MAC_PHYCFG2, val);
905
906 val = tr32(MAC_PHYCFG1);
907 val &= ~MAC_PHYCFG1_RGMII_INT;
908 tw32(MAC_PHYCFG1, val);
878 909
879 if (tp->mdio_bus->phy_map[PHY_ADDR]->interface !=
880 PHY_INTERFACE_MODE_RGMII)
881 return; 910 return;
911 }
912
913 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
914 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
915 MAC_PHYCFG2_FMODE_MASK_MASK |
916 MAC_PHYCFG2_GMODE_MASK_MASK |
917 MAC_PHYCFG2_ACT_MASK_MASK |
918 MAC_PHYCFG2_QUAL_MASK_MASK |
919 MAC_PHYCFG2_INBAND_ENABLE;
920
921 tw32(MAC_PHYCFG2, val);
882 922
883 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC | 923 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
884 MAC_PHYCFG1_RGMII_SND_STAT_EN); 924 MAC_PHYCFG1_RGMII_SND_STAT_EN);
@@ -890,11 +930,6 @@ static void tg3_mdio_config(struct tg3 *tp)
890 } 930 }
891 tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV); 931 tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
892 932
893 val = tr32(MAC_PHYCFG2) & ~(MAC_PHYCFG2_INBAND_ENABLE);
894 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
895 val |= MAC_PHYCFG2_INBAND_ENABLE;
896 tw32(MAC_PHYCFG2, val);
897
898 val = tr32(MAC_EXT_RGMII_MODE); 933 val = tr32(MAC_EXT_RGMII_MODE);
899 val &= ~(MAC_RGMII_MODE_RX_INT_B | 934 val &= ~(MAC_RGMII_MODE_RX_INT_B |
900 MAC_RGMII_MODE_RX_QUALITY | 935 MAC_RGMII_MODE_RX_QUALITY |
@@ -903,7 +938,7 @@ static void tg3_mdio_config(struct tg3 *tp)
903 MAC_RGMII_MODE_TX_ENABLE | 938 MAC_RGMII_MODE_TX_ENABLE |
904 MAC_RGMII_MODE_TX_LOWPWR | 939 MAC_RGMII_MODE_TX_LOWPWR |
905 MAC_RGMII_MODE_TX_RESET); 940 MAC_RGMII_MODE_TX_RESET);
906 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) { 941 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
907 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) 942 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
908 val |= MAC_RGMII_MODE_RX_INT_B | 943 val |= MAC_RGMII_MODE_RX_INT_B |
909 MAC_RGMII_MODE_RX_QUALITY | 944 MAC_RGMII_MODE_RX_QUALITY |
@@ -929,8 +964,9 @@ static void tg3_mdio_start(struct tg3 *tp)
929 tw32_f(MAC_MI_MODE, tp->mi_mode); 964 tw32_f(MAC_MI_MODE, tp->mi_mode);
930 udelay(80); 965 udelay(80);
931 966
932 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) 967 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
933 tg3_mdio_config(tp); 968 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
969 tg3_mdio_config_5785(tp);
934} 970}
935 971
936static void tg3_mdio_stop(struct tg3 *tp) 972static void tg3_mdio_stop(struct tg3 *tp)
@@ -984,29 +1020,41 @@ static int tg3_mdio_init(struct tg3 *tp)
984 if (i) { 1020 if (i) {
985 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n", 1021 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
986 tp->dev->name, i); 1022 tp->dev->name, i);
1023 mdiobus_free(tp->mdio_bus);
987 return i; 1024 return i;
988 } 1025 }
989 1026
990 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
991
992 phydev = tp->mdio_bus->phy_map[PHY_ADDR]; 1027 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
993 1028
994 switch (phydev->phy_id) { 1029 if (!phydev || !phydev->drv) {
1030 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1031 mdiobus_unregister(tp->mdio_bus);
1032 mdiobus_free(tp->mdio_bus);
1033 return -ENODEV;
1034 }
1035
1036 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
995 case TG3_PHY_ID_BCM50610: 1037 case TG3_PHY_ID_BCM50610:
996 phydev->interface = PHY_INTERFACE_MODE_RGMII;
997 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) 1038 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
998 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; 1039 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
999 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) 1040 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1000 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; 1041 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1001 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) 1042 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1002 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; 1043 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1044 /* fallthru */
1045 case TG3_PHY_ID_RTL8211C:
1046 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1003 break; 1047 break;
1048 case TG3_PHY_ID_RTL8201E:
1004 case TG3_PHY_ID_BCMAC131: 1049 case TG3_PHY_ID_BCMAC131:
1005 phydev->interface = PHY_INTERFACE_MODE_MII; 1050 phydev->interface = PHY_INTERFACE_MODE_MII;
1006 break; 1051 break;
1007 } 1052 }
1008 1053
1009 tg3_mdio_config(tp); 1054 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1055
1056 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1057 tg3_mdio_config_5785(tp);
1010 1058
1011 return 0; 1059 return 0;
1012} 1060}
@@ -1299,6 +1347,15 @@ static void tg3_adjust_link(struct net_device *dev)
1299 udelay(40); 1347 udelay(40);
1300 } 1348 }
1301 1349
1350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1351 if (phydev->speed == SPEED_10)
1352 tw32(MAC_MI_STAT,
1353 MAC_MI_STAT_10MBPS_MODE |
1354 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1355 else
1356 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1357 }
1358
1302 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) 1359 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1303 tw32(MAC_TX_LENGTHS, 1360 tw32(MAC_TX_LENGTHS,
1304 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | 1361 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
@@ -1339,25 +1396,34 @@ static int tg3_phy_init(struct tg3 *tp)
1339 phydev = tp->mdio_bus->phy_map[PHY_ADDR]; 1396 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1340 1397
1341 /* Attach the MAC to the PHY. */ 1398 /* Attach the MAC to the PHY. */
1342 phydev = phy_connect(tp->dev, phydev->dev.bus_id, tg3_adjust_link, 1399 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1343 phydev->dev_flags, phydev->interface); 1400 phydev->dev_flags, phydev->interface);
1344 if (IS_ERR(phydev)) { 1401 if (IS_ERR(phydev)) {
1345 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name); 1402 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1346 return PTR_ERR(phydev); 1403 return PTR_ERR(phydev);
1347 } 1404 }
1348 1405
1349 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1350
1351 /* Mask with MAC supported features. */ 1406 /* Mask with MAC supported features. */
1352 phydev->supported &= (PHY_GBIT_FEATURES | 1407 switch (phydev->interface) {
1353 SUPPORTED_Pause | 1408 case PHY_INTERFACE_MODE_GMII:
1354 SUPPORTED_Asym_Pause); 1409 case PHY_INTERFACE_MODE_RGMII:
1410 phydev->supported &= (PHY_GBIT_FEATURES |
1411 SUPPORTED_Pause |
1412 SUPPORTED_Asym_Pause);
1413 break;
1414 case PHY_INTERFACE_MODE_MII:
1415 phydev->supported &= (PHY_BASIC_FEATURES |
1416 SUPPORTED_Pause |
1417 SUPPORTED_Asym_Pause);
1418 break;
1419 default:
1420 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1421 return -EINVAL;
1422 }
1355 1423
1356 phydev->advertising = phydev->supported; 1424 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1357 1425
1358 printk(KERN_INFO 1426 phydev->advertising = phydev->supported;
1359 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
1360 tp->dev->name, phydev->drv->name, phydev->dev.bus_id);
1361 1427
1362 return 0; 1428 return 0;
1363} 1429}
@@ -1737,7 +1803,8 @@ static int tg3_phy_reset(struct tg3 *tp)
1737 tw32(TG3_CPMU_CTRL, cpmuctrl); 1803 tw32(TG3_CPMU_CTRL, cpmuctrl);
1738 } 1804 }
1739 1805
1740 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) { 1806 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1807 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1741 u32 val; 1808 u32 val;
1742 1809
1743 val = tr32(TG3_CPMU_LSPD_1000MB_CLK); 1810 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
@@ -1961,7 +2028,7 @@ static int tg3_halt_cpu(struct tg3 *, u32);
1961static int tg3_nvram_lock(struct tg3 *); 2028static int tg3_nvram_lock(struct tg3 *);
1962static void tg3_nvram_unlock(struct tg3 *); 2029static void tg3_nvram_unlock(struct tg3 *);
1963 2030
1964static void tg3_power_down_phy(struct tg3 *tp) 2031static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
1965{ 2032{
1966 u32 val; 2033 u32 val;
1967 2034
@@ -1984,10 +2051,15 @@ static void tg3_power_down_phy(struct tg3 *tp)
1984 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); 2051 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1985 udelay(40); 2052 udelay(40);
1986 return; 2053 return;
1987 } else if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { 2054 } else if (do_low_power) {
1988 tg3_writephy(tp, MII_TG3_EXT_CTRL, 2055 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1989 MII_TG3_EXT_CTRL_FORCE_LED_OFF); 2056 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1990 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2); 2057
2058 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2059 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2060 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2061 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2062 MII_TG3_AUXCTL_PCTL_VREG_11V);
1991 } 2063 }
1992 2064
1993 /* The PHY should not be powered down on some chips because 2065 /* The PHY should not be powered down on some chips because
@@ -1999,7 +2071,8 @@ static void tg3_power_down_phy(struct tg3 *tp)
1999 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))) 2071 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2000 return; 2072 return;
2001 2073
2002 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) { 2074 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2075 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2003 val = tr32(TG3_CPMU_LSPD_1000MB_CLK); 2076 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2004 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; 2077 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2005 val |= CPMU_LSPD_1000MB_MACCLK_12_5; 2078 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
@@ -2009,9 +2082,47 @@ static void tg3_power_down_phy(struct tg3 *tp)
2009 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); 2082 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2010} 2083}
2011 2084
2085/* tp->lock is held. */
2086static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2087{
2088 u32 addr_high, addr_low;
2089 int i;
2090
2091 addr_high = ((tp->dev->dev_addr[0] << 8) |
2092 tp->dev->dev_addr[1]);
2093 addr_low = ((tp->dev->dev_addr[2] << 24) |
2094 (tp->dev->dev_addr[3] << 16) |
2095 (tp->dev->dev_addr[4] << 8) |
2096 (tp->dev->dev_addr[5] << 0));
2097 for (i = 0; i < 4; i++) {
2098 if (i == 1 && skip_mac_1)
2099 continue;
2100 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2101 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2102 }
2103
2104 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2105 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2106 for (i = 0; i < 12; i++) {
2107 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2108 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2109 }
2110 }
2111
2112 addr_high = (tp->dev->dev_addr[0] +
2113 tp->dev->dev_addr[1] +
2114 tp->dev->dev_addr[2] +
2115 tp->dev->dev_addr[3] +
2116 tp->dev->dev_addr[4] +
2117 tp->dev->dev_addr[5]) &
2118 TX_BACKOFF_SEED_MASK;
2119 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2120}
2121
2012static int tg3_set_power_state(struct tg3 *tp, pci_power_t state) 2122static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2013{ 2123{
2014 u32 misc_host_ctrl; 2124 u32 misc_host_ctrl;
2125 bool device_should_wake, do_low_power;
2015 2126
2016 /* Make sure register accesses (indirect or otherwise) 2127 /* Make sure register accesses (indirect or otherwise)
2017 * will function correctly. 2128 * will function correctly.
@@ -2045,11 +2156,16 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2045 tw32(TG3PCI_MISC_HOST_CTRL, 2156 tw32(TG3PCI_MISC_HOST_CTRL,
2046 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); 2157 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2047 2158
2159 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2160 device_may_wakeup(&tp->pdev->dev) &&
2161 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2162
2048 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { 2163 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2164 do_low_power = false;
2049 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) && 2165 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2050 !tp->link_config.phy_is_low_power) { 2166 !tp->link_config.phy_is_low_power) {
2051 struct phy_device *phydev; 2167 struct phy_device *phydev;
2052 u32 advertising; 2168 u32 phyid, advertising;
2053 2169
2054 phydev = tp->mdio_bus->phy_map[PHY_ADDR]; 2170 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2055 2171
@@ -2066,7 +2182,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2066 ADVERTISED_10baseT_Half; 2182 ADVERTISED_10baseT_Half;
2067 2183
2068 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || 2184 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2069 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) { 2185 device_should_wake) {
2070 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) 2186 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2071 advertising |= 2187 advertising |=
2072 ADVERTISED_100baseT_Half | 2188 ADVERTISED_100baseT_Half |
@@ -2079,8 +2195,19 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2079 phydev->advertising = advertising; 2195 phydev->advertising = advertising;
2080 2196
2081 phy_start_aneg(phydev); 2197 phy_start_aneg(phydev);
2198
2199 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2200 if (phyid != TG3_PHY_ID_BCMAC131) {
2201 phyid &= TG3_PHY_OUI_MASK;
2202 if (phyid == TG3_PHY_OUI_1 &&
2203 phyid == TG3_PHY_OUI_2 &&
2204 phyid == TG3_PHY_OUI_3)
2205 do_low_power = true;
2206 }
2082 } 2207 }
2083 } else { 2208 } else {
2209 do_low_power = false;
2210
2084 if (tp->link_config.phy_is_low_power == 0) { 2211 if (tp->link_config.phy_is_low_power == 0) {
2085 tp->link_config.phy_is_low_power = 1; 2212 tp->link_config.phy_is_low_power = 1;
2086 tp->link_config.orig_speed = tp->link_config.speed; 2213 tp->link_config.orig_speed = tp->link_config.speed;
@@ -2096,6 +2223,8 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2096 } 2223 }
2097 } 2224 }
2098 2225
2226 __tg3_set_mac_addr(tp, 0);
2227
2099 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 2228 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2100 u32 val; 2229 u32 val;
2101 2230
@@ -2118,11 +2247,11 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2118 WOL_DRV_WOL | 2247 WOL_DRV_WOL |
2119 WOL_SET_MAGIC_PKT); 2248 WOL_SET_MAGIC_PKT);
2120 2249
2121 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) { 2250 if (device_should_wake) {
2122 u32 mac_mode; 2251 u32 mac_mode;
2123 2252
2124 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { 2253 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2125 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { 2254 if (do_low_power) {
2126 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a); 2255 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2127 udelay(40); 2256 udelay(40);
2128 } 2257 }
@@ -2150,9 +2279,12 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2150 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) 2279 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2151 tw32(MAC_LED_CTRL, tp->led_ctrl); 2280 tw32(MAC_LED_CTRL, tp->led_ctrl);
2152 2281
2153 if (pci_pme_capable(tp->pdev, state) && 2282 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2154 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) 2283 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2155 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; 2284 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2285 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2286 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2287 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2156 2288
2157 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { 2289 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2158 mac_mode |= tp->mac_mode & 2290 mac_mode |= tp->mac_mode &
@@ -2224,10 +2356,10 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2224 } 2356 }
2225 } 2357 }
2226 2358
2227 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) && 2359 if (!(device_should_wake) &&
2228 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && 2360 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
2229 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) 2361 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
2230 tg3_power_down_phy(tp); 2362 tg3_power_down_phy(tp, do_low_power);
2231 2363
2232 tg3_frob_aux_power(tp); 2364 tg3_frob_aux_power(tp);
2233 2365
@@ -2250,7 +2382,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2250 2382
2251 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); 2383 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2252 2384
2253 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) 2385 if (device_should_wake)
2254 pci_enable_wake(tp->pdev, state, true); 2386 pci_enable_wake(tp->pdev, state, true);
2255 2387
2256 /* Finally, set the new power state. */ 2388 /* Finally, set the new power state. */
@@ -3765,8 +3897,7 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3765 err = tg3_setup_copper_phy(tp, force_reset); 3897 err = tg3_setup_copper_phy(tp, force_reset);
3766 } 3898 }
3767 3899
3768 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 || 3900 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
3769 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
3770 u32 val, scale; 3901 u32 val, scale;
3771 3902
3772 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; 3903 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
@@ -4157,7 +4288,6 @@ static int tg3_rx(struct tg3 *tp, int budget)
4157#endif 4288#endif
4158 netif_receive_skb(skb); 4289 netif_receive_skb(skb);
4159 4290
4160 tp->dev->last_rx = jiffies;
4161 received++; 4291 received++;
4162 budget--; 4292 budget--;
4163 4293
@@ -5557,6 +5687,13 @@ static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5557 event = APE_EVENT_STATUS_STATE_START; 5687 event = APE_EVENT_STATUS_STATE_START;
5558 break; 5688 break;
5559 case RESET_KIND_SHUTDOWN: 5689 case RESET_KIND_SHUTDOWN:
5690 /* With the interface we are currently using,
5691 * APE does not track driver state. Wiping
5692 * out the HOST SEGMENT SIGNATURE forces
5693 * the APE to assume OS absent status.
5694 */
5695 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5696
5560 event = APE_EVENT_STATUS_STATE_UNLOAD; 5697 event = APE_EVENT_STATUS_STATE_UNLOAD;
5561 break; 5698 break;
5562 case RESET_KIND_SUSPEND: 5699 case RESET_KIND_SUSPEND:
@@ -5721,13 +5858,15 @@ static void tg3_restore_pci_state(struct tg3 *tp)
5721 5858
5722 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); 5859 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5723 5860
5724 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) 5861 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
5725 pcie_set_readrq(tp->pdev, 4096); 5862 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5726 else { 5863 pcie_set_readrq(tp->pdev, 4096);
5727 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, 5864 else {
5728 tp->pci_cacheline_sz); 5865 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5729 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, 5866 tp->pci_cacheline_sz);
5730 tp->pci_lat_timer); 5867 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5868 tp->pci_lat_timer);
5869 }
5731 } 5870 }
5732 5871
5733 /* Make sure PCI-X relaxed ordering bit is clear. */ 5872 /* Make sure PCI-X relaxed ordering bit is clear. */
@@ -5884,8 +6023,9 @@ static int tg3_chip_reset(struct tg3 *tp)
5884 pci_write_config_dword(tp->pdev, 0xc4, 6023 pci_write_config_dword(tp->pdev, 0xc4,
5885 cfg_val | (1 << 15)); 6024 cfg_val | (1 << 15));
5886 } 6025 }
5887 /* Set PCIE max payload size and clear error status. */ 6026 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
5888 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000); 6027 /* Set PCIE max payload size and clear error status. */
6028 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5889 } 6029 }
5890 6030
5891 tg3_restore_pci_state(tp); 6031 tg3_restore_pci_state(tp);
@@ -6883,43 +7023,6 @@ static int tg3_load_tso_firmware(struct tg3 *tp)
6883} 7023}
6884 7024
6885 7025
6886/* tp->lock is held. */
6887static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
6888{
6889 u32 addr_high, addr_low;
6890 int i;
6891
6892 addr_high = ((tp->dev->dev_addr[0] << 8) |
6893 tp->dev->dev_addr[1]);
6894 addr_low = ((tp->dev->dev_addr[2] << 24) |
6895 (tp->dev->dev_addr[3] << 16) |
6896 (tp->dev->dev_addr[4] << 8) |
6897 (tp->dev->dev_addr[5] << 0));
6898 for (i = 0; i < 4; i++) {
6899 if (i == 1 && skip_mac_1)
6900 continue;
6901 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6902 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6903 }
6904
6905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6907 for (i = 0; i < 12; i++) {
6908 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6909 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6910 }
6911 }
6912
6913 addr_high = (tp->dev->dev_addr[0] +
6914 tp->dev->dev_addr[1] +
6915 tp->dev->dev_addr[2] +
6916 tp->dev->dev_addr[3] +
6917 tp->dev->dev_addr[4] +
6918 tp->dev->dev_addr[5]) &
6919 TX_BACKOFF_SEED_MASK;
6920 tw32(MAC_TX_BACKOFF_SEED, addr_high);
6921}
6922
6923static int tg3_set_mac_addr(struct net_device *dev, void *p) 7026static int tg3_set_mac_addr(struct net_device *dev, void *p)
6924{ 7027{
6925 struct tg3 *tp = netdev_priv(dev); 7028 struct tg3 *tp = netdev_priv(dev);
@@ -7024,8 +7127,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7024 7127
7025 tg3_write_sig_legacy(tp, RESET_KIND_INIT); 7128 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7026 7129
7027 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 || 7130 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7028 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
7029 val = tr32(TG3_CPMU_CTRL); 7131 val = tr32(TG3_CPMU_CTRL);
7030 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); 7132 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7031 tw32(TG3_CPMU_CTRL, val); 7133 tw32(TG3_CPMU_CTRL, val);
@@ -7091,8 +7193,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7091 return err; 7193 return err;
7092 7194
7093 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && 7195 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7094 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 && 7196 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7095 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7096 /* This value is determined during the probe time DMA 7197 /* This value is determined during the probe time DMA
7097 * engine test, tg3_test_dma. 7198 * engine test, tg3_test_dma.
7098 */ 7199 */
@@ -9066,7 +9167,8 @@ static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9066 else 9167 else
9067 wol->supported = 0; 9168 wol->supported = 0;
9068 wol->wolopts = 0; 9169 wol->wolopts = 0;
9069 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) 9170 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9171 device_can_wakeup(&tp->pdev->dev))
9070 wol->wolopts = WAKE_MAGIC; 9172 wol->wolopts = WAKE_MAGIC;
9071 memset(&wol->sopass, 0, sizeof(wol->sopass)); 9173 memset(&wol->sopass, 0, sizeof(wol->sopass));
9072} 9174}
@@ -11299,7 +11401,7 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11299 (val & VCPU_CFGSHDW_WOL_MAGPKT) && 11401 (val & VCPU_CFGSHDW_WOL_MAGPKT) &&
11300 device_may_wakeup(&tp->pdev->dev)) 11402 device_may_wakeup(&tp->pdev->dev))
11301 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; 11403 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11302 return; 11404 goto done;
11303 } 11405 }
11304 11406
11305 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); 11407 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
@@ -11421,15 +11523,17 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11421 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) 11523 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11422 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; 11524 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11423 } 11525 }
11424 if (nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) 11526
11527 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11528 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11425 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE; 11529 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11530
11426 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES && 11531 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11427 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) 11532 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11428 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP; 11533 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11429 11534
11430 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && 11535 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11431 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE) && 11536 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11432 device_may_wakeup(&tp->pdev->dev))
11433 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; 11537 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11434 11538
11435 if (cfg2 & (1 << 17)) 11539 if (cfg2 & (1 << 17))
@@ -11455,6 +11559,10 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11455 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) 11559 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11456 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN; 11560 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11457 } 11561 }
11562done:
11563 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11564 device_set_wakeup_enable(&tp->pdev->dev,
11565 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11458} 11566}
11459 11567
11460static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) 11568static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
@@ -12091,7 +12199,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12091 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) 12199 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
12092 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2; 12200 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12093 } 12201 }
12094 } 12202 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12203 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12095 12204
12096 /* If we have an AMD 762 or VIA K8T800 chipset, write 12205 /* If we have an AMD 762 or VIA K8T800 chipset, write
12097 * reordering to the mailbox registers done by the host 12206 * reordering to the mailbox registers done by the host
@@ -12263,16 +12372,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12263 12372
12264 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 12373 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12265 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || 12374 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12266 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { 12375 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12267 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT; 12376 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12268 12377
12269 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
12270 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1 ||
12271 tp->pci_chip_rev_id == CHIPREV_ID_5761_A0 ||
12272 tp->pci_chip_rev_id == CHIPREV_ID_5761_A1)
12273 tp->tg3_flags3 |= TG3_FLG3_5761_5784_AX_FIXES;
12274 }
12275
12276 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state(). 12378 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12277 * GPIO1 driven high will bring 5700's external PHY out of reset. 12379 * GPIO1 driven high will bring 5700's external PHY out of reset.
12278 * It is also used as eeprom write protect on LOMs. 12380 * It is also used as eeprom write protect on LOMs.
@@ -13245,14 +13347,12 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
13245 const struct pci_device_id *ent) 13347 const struct pci_device_id *ent)
13246{ 13348{
13247 static int tg3_version_printed = 0; 13349 static int tg3_version_printed = 0;
13248 resource_size_t tg3reg_base; 13350 resource_size_t tg3reg_len;
13249 unsigned long tg3reg_len;
13250 struct net_device *dev; 13351 struct net_device *dev;
13251 struct tg3 *tp; 13352 struct tg3 *tp;
13252 int err, pm_cap; 13353 int err, pm_cap;
13253 char str[40]; 13354 char str[40];
13254 u64 dma_mask, persist_dma_mask; 13355 u64 dma_mask, persist_dma_mask;
13255 DECLARE_MAC_BUF(mac);
13256 13356
13257 if (tg3_version_printed++ == 0) 13357 if (tg3_version_printed++ == 0)
13258 printk(KERN_INFO "%s", version); 13358 printk(KERN_INFO "%s", version);
@@ -13264,7 +13364,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
13264 return err; 13364 return err;
13265 } 13365 }
13266 13366
13267 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 13367 if (!(pci_resource_flags(pdev, BAR_0) & IORESOURCE_MEM)) {
13268 printk(KERN_ERR PFX "Cannot find proper PCI device " 13368 printk(KERN_ERR PFX "Cannot find proper PCI device "
13269 "base address, aborting.\n"); 13369 "base address, aborting.\n");
13270 err = -ENODEV; 13370 err = -ENODEV;
@@ -13289,9 +13389,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
13289 goto err_out_free_res; 13389 goto err_out_free_res;
13290 } 13390 }
13291 13391
13292 tg3reg_base = pci_resource_start(pdev, 0);
13293 tg3reg_len = pci_resource_len(pdev, 0);
13294
13295 dev = alloc_etherdev(sizeof(*tp)); 13392 dev = alloc_etherdev(sizeof(*tp));
13296 if (!dev) { 13393 if (!dev) {
13297 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n"); 13394 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
@@ -13343,7 +13440,11 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
13343 spin_lock_init(&tp->indirect_lock); 13440 spin_lock_init(&tp->indirect_lock);
13344 INIT_WORK(&tp->reset_task, tg3_reset_task); 13441 INIT_WORK(&tp->reset_task, tg3_reset_task);
13345 13442
13346 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len); 13443 dev->mem_start = pci_resource_start(pdev, BAR_0);
13444 tg3reg_len = pci_resource_len(pdev, BAR_0);
13445 dev->mem_end = dev->mem_start + tg3reg_len;
13446
13447 tp->regs = ioremap_nocache(dev->mem_start, tg3reg_len);
13347 if (!tp->regs) { 13448 if (!tp->regs) {
13348 printk(KERN_ERR PFX "Cannot map device registers, " 13449 printk(KERN_ERR PFX "Cannot map device registers, "
13349 "aborting.\n"); 13450 "aborting.\n");
@@ -13466,17 +13567,14 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
13466 } 13567 }
13467 13568
13468 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { 13569 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13469 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 13570 if (!(pci_resource_flags(pdev, BAR_2) & IORESOURCE_MEM)) {
13470 printk(KERN_ERR PFX "Cannot find proper PCI device " 13571 printk(KERN_ERR PFX "Cannot find proper PCI device "
13471 "base address for APE, aborting.\n"); 13572 "base address for APE, aborting.\n");
13472 err = -ENODEV; 13573 err = -ENODEV;
13473 goto err_out_iounmap; 13574 goto err_out_iounmap;
13474 } 13575 }
13475 13576
13476 tg3reg_base = pci_resource_start(pdev, 2); 13577 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13477 tg3reg_len = pci_resource_len(pdev, 2);
13478
13479 tp->aperegs = ioremap_nocache(tg3reg_base, tg3reg_len);
13480 if (!tp->aperegs) { 13578 if (!tp->aperegs) {
13481 printk(KERN_ERR PFX "Cannot map APE registers, " 13579 printk(KERN_ERR PFX "Cannot map APE registers, "
13482 "aborting.\n"); 13580 "aborting.\n");
@@ -13535,26 +13633,34 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
13535 goto err_out_apeunmap; 13633 goto err_out_apeunmap;
13536 } 13634 }
13537 13635
13538 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] " 13636 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13539 "(%s) %s Ethernet %s\n",
13540 dev->name, 13637 dev->name,
13541 tp->board_part_number, 13638 tp->board_part_number,
13542 tp->pci_chip_rev_id, 13639 tp->pci_chip_rev_id,
13543 tg3_phy_string(tp),
13544 tg3_bus_string(tp, str), 13640 tg3_bus_string(tp, str),
13545 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" : 13641 dev->dev_addr);
13546 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13547 "10/100/1000Base-T")),
13548 print_mac(mac, dev->dev_addr));
13549 13642
13550 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] " 13643 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13551 "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n", 13644 printk(KERN_INFO
13645 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13646 tp->dev->name,
13647 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13648 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13649 else
13650 printk(KERN_INFO
13651 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13652 tp->dev->name, tg3_phy_string(tp),
13653 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13654 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13655 "10/100/1000Base-T")),
13656 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13657
13658 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13552 dev->name, 13659 dev->name,
13553 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0, 13660 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13554 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0, 13661 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13555 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0, 13662 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13556 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0, 13663 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13557 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
13558 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0); 13664 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13559 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n", 13665 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13560 dev->name, tp->dma_rwctrl, 13666 dev->name, tp->dma_rwctrl,
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-17 21:52:26 -0400