aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/tg3.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c67
1 files changed, 45 insertions, 22 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 327836b1014e..c20bb998e0e5 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -68,8 +68,8 @@
68 68
69#define DRV_MODULE_NAME "tg3" 69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": " 70#define PFX DRV_MODULE_NAME ": "
71#define DRV_MODULE_VERSION "3.66" 71#define DRV_MODULE_VERSION "3.69"
72#define DRV_MODULE_RELDATE "September 23, 2006" 72#define DRV_MODULE_RELDATE "November 15, 2006"
73 73
74#define TG3_DEF_MAC_MODE 0 74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0 75#define TG3_DEF_RX_MODE 0
@@ -129,7 +129,7 @@
129#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64) 129#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
130 130
131/* minimum number of free TX descriptors required to wake up TX process */ 131/* minimum number of free TX descriptors required to wake up TX process */
132#define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4) 132#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
133 133
134/* number of ETHTOOL_GSTATS u64's */ 134/* number of ETHTOOL_GSTATS u64's */
135#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64)) 135#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
@@ -3075,10 +3075,10 @@ static void tg3_tx(struct tg3 *tp)
3075 smp_mb(); 3075 smp_mb();
3076 3076
3077 if (unlikely(netif_queue_stopped(tp->dev) && 3077 if (unlikely(netif_queue_stopped(tp->dev) &&
3078 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH))) { 3078 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3079 netif_tx_lock(tp->dev); 3079 netif_tx_lock(tp->dev);
3080 if (netif_queue_stopped(tp->dev) && 3080 if (netif_queue_stopped(tp->dev) &&
3081 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH)) 3081 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3082 netif_wake_queue(tp->dev); 3082 netif_wake_queue(tp->dev);
3083 netif_tx_unlock(tp->dev); 3083 netif_tx_unlock(tp->dev);
3084 } 3084 }
@@ -3928,7 +3928,7 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3928 tp->tx_prod = entry; 3928 tp->tx_prod = entry;
3929 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) { 3929 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3930 netif_stop_queue(dev); 3930 netif_stop_queue(dev);
3931 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH) 3931 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3932 netif_wake_queue(tp->dev); 3932 netif_wake_queue(tp->dev);
3933 } 3933 }
3934 3934
@@ -4143,7 +4143,7 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4143 tp->tx_prod = entry; 4143 tp->tx_prod = entry;
4144 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) { 4144 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4145 netif_stop_queue(dev); 4145 netif_stop_queue(dev);
4146 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH) 4146 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4147 netif_wake_queue(tp->dev); 4147 netif_wake_queue(tp->dev);
4148 } 4148 }
4149 4149
@@ -4728,10 +4728,11 @@ static int tg3_poll_fw(struct tg3 *tp)
4728 u32 val; 4728 u32 val;
4729 4729
4730 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 4730 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4731 for (i = 0; i < 400; i++) { 4731 /* Wait up to 20ms for init done. */
4732 for (i = 0; i < 200; i++) {
4732 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) 4733 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4733 return 0; 4734 return 0;
4734 udelay(10); 4735 udelay(100);
4735 } 4736 }
4736 return -ENODEV; 4737 return -ENODEV;
4737 } 4738 }
@@ -6014,7 +6015,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6014 tg3_abort_hw(tp, 1); 6015 tg3_abort_hw(tp, 1);
6015 } 6016 }
6016 6017
6017 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) && reset_phy) 6018 if (reset_phy)
6018 tg3_phy_reset(tp); 6019 tg3_phy_reset(tp);
6019 6020
6020 err = tg3_chip_reset(tp); 6021 err = tg3_chip_reset(tp);
@@ -6574,7 +6575,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6574 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); 6575 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6575 } 6576 }
6576 6577
6577 err = tg3_setup_phy(tp, reset_phy); 6578 err = tg3_setup_phy(tp, 0);
6578 if (err) 6579 if (err)
6579 return err; 6580 return err;
6580 6581
@@ -6978,8 +6979,10 @@ static int tg3_open(struct net_device *dev)
6978 tg3_full_lock(tp, 0); 6979 tg3_full_lock(tp, 0);
6979 6980
6980 err = tg3_set_power_state(tp, PCI_D0); 6981 err = tg3_set_power_state(tp, PCI_D0);
6981 if (err) 6982 if (err) {
6983 tg3_full_unlock(tp);
6982 return err; 6984 return err;
6985 }
6983 6986
6984 tg3_disable_ints(tp); 6987 tg3_disable_ints(tp);
6985 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; 6988 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
@@ -8106,7 +8109,10 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e
8106 8109
8107 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) || 8110 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8108 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) || 8111 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8109 (ering->tx_pending > TG3_TX_RING_SIZE - 1)) 8112 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8113 (ering->tx_pending <= MAX_SKB_FRAGS) ||
8114 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG) &&
8115 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8110 return -EINVAL; 8116 return -EINVAL;
8111 8117
8112 if (netif_running(dev)) { 8118 if (netif_running(dev)) {
@@ -10209,7 +10215,7 @@ skip_phy_reset:
10209static void __devinit tg3_read_partno(struct tg3 *tp) 10215static void __devinit tg3_read_partno(struct tg3 *tp)
10210{ 10216{
10211 unsigned char vpd_data[256]; 10217 unsigned char vpd_data[256];
10212 int i; 10218 unsigned int i;
10213 u32 magic; 10219 u32 magic;
10214 10220
10215 if (tg3_nvram_read_swab(tp, 0x0, &magic)) 10221 if (tg3_nvram_read_swab(tp, 0x0, &magic))
@@ -10255,9 +10261,9 @@ static void __devinit tg3_read_partno(struct tg3 *tp)
10255 } 10261 }
10256 10262
10257 /* Now parse and find the part number. */ 10263 /* Now parse and find the part number. */
10258 for (i = 0; i < 256; ) { 10264 for (i = 0; i < 254; ) {
10259 unsigned char val = vpd_data[i]; 10265 unsigned char val = vpd_data[i];
10260 int block_end; 10266 unsigned int block_end;
10261 10267
10262 if (val == 0x82 || val == 0x91) { 10268 if (val == 0x82 || val == 0x91) {
10263 i = (i + 3 + 10269 i = (i + 3 +
@@ -10273,21 +10279,26 @@ static void __devinit tg3_read_partno(struct tg3 *tp)
10273 (vpd_data[i + 1] + 10279 (vpd_data[i + 1] +
10274 (vpd_data[i + 2] << 8))); 10280 (vpd_data[i + 2] << 8)));
10275 i += 3; 10281 i += 3;
10276 while (i < block_end) { 10282
10283 if (block_end > 256)
10284 goto out_not_found;
10285
10286 while (i < (block_end - 2)) {
10277 if (vpd_data[i + 0] == 'P' && 10287 if (vpd_data[i + 0] == 'P' &&
10278 vpd_data[i + 1] == 'N') { 10288 vpd_data[i + 1] == 'N') {
10279 int partno_len = vpd_data[i + 2]; 10289 int partno_len = vpd_data[i + 2];
10280 10290
10281 if (partno_len > 24) 10291 i += 3;
10292 if (partno_len > 24 || (partno_len + i) > 256)
10282 goto out_not_found; 10293 goto out_not_found;
10283 10294
10284 memcpy(tp->board_part_number, 10295 memcpy(tp->board_part_number,
10285 &vpd_data[i + 3], 10296 &vpd_data[i], partno_len);
10286 partno_len);
10287 10297
10288 /* Success. */ 10298 /* Success. */
10289 return; 10299 return;
10290 } 10300 }
10301 i += 3 + vpd_data[i + 2];
10291 } 10302 }
10292 10303
10293 /* Part number not found. */ 10304 /* Part number not found. */
@@ -10357,7 +10368,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10357 u32 pci_state_reg, grc_misc_cfg; 10368 u32 pci_state_reg, grc_misc_cfg;
10358 u32 val; 10369 u32 val;
10359 u16 pci_cmd; 10370 u16 pci_cmd;
10360 int err; 10371 int err, pcie_cap;
10361 10372
10362 /* Force memory write invalidate off. If we leave it on, 10373 /* Force memory write invalidate off. If we leave it on,
10363 * then on 5700_BX chips we have to enable a workaround. 10374 * then on 5700_BX chips we have to enable a workaround.
@@ -10532,8 +10543,19 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10532 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) 10543 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10533 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE; 10544 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10534 10545
10535 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0) 10546 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10547 if (pcie_cap != 0) {
10536 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; 10548 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10549 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10550 u16 lnkctl;
10551
10552 pci_read_config_word(tp->pdev,
10553 pcie_cap + PCI_EXP_LNKCTL,
10554 &lnkctl);
10555 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10556 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10557 }
10558 }
10537 10559
10538 /* If we have an AMD 762 or VIA K8T800 chipset, write 10560 /* If we have an AMD 762 or VIA K8T800 chipset, write
10539 * reordering to the mailbox registers done by the host 10561 * reordering to the mailbox registers done by the host
@@ -11800,6 +11822,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
11800 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || 11822 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11801 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || 11823 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11802 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 || 11824 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11825 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11803 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) { 11826 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11804 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; 11827 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11805 } else { 11828 } else {