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Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 76efb3feffbf..014dc2cfe4d6 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -64,8 +64,8 @@
64 64
65#define DRV_MODULE_NAME "tg3" 65#define DRV_MODULE_NAME "tg3"
66#define PFX DRV_MODULE_NAME ": " 66#define PFX DRV_MODULE_NAME ": "
67#define DRV_MODULE_VERSION "3.83" 67#define DRV_MODULE_VERSION "3.84"
68#define DRV_MODULE_RELDATE "October 10, 2007" 68#define DRV_MODULE_RELDATE "October 12, 2007"
69 69
70#define TG3_DEF_MAC_MODE 0 70#define TG3_DEF_MAC_MODE 0
71#define TG3_DEF_RX_MODE 0 71#define TG3_DEF_RX_MODE 0
@@ -5056,6 +5056,12 @@ static void tg3_restore_pci_state(struct tg3 *tp)
5056 5056
5057 pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd); 5057 pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);
5058 5058
5059 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5060 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5061 tp->pci_cacheline_sz);
5062 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5063 tp->pci_lat_timer);
5064 }
5059 /* Make sure PCI-X relaxed ordering bit is clear. */ 5065 /* Make sure PCI-X relaxed ordering bit is clear. */
5060 if (tp->pcix_cap) { 5066 if (tp->pcix_cap) {
5061 u16 pcix_cmd; 5067 u16 pcix_cmd;