diff options
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r-- | drivers/net/tg3.c | 86 |
1 files changed, 52 insertions, 34 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index e402f162eb81..538232586ee5 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -1605,7 +1605,7 @@ static void tg3_power_down_phy(struct tg3 *tp) | |||
1605 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | 1605 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); |
1606 | udelay(40); | 1606 | udelay(40); |
1607 | return; | 1607 | return; |
1608 | } else { | 1608 | } else if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { |
1609 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | 1609 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
1610 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | 1610 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); |
1611 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2); | 1611 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2); |
@@ -1687,18 +1687,22 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state) | |||
1687 | tw32(TG3PCI_MISC_HOST_CTRL, | 1687 | tw32(TG3PCI_MISC_HOST_CTRL, |
1688 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | 1688 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); |
1689 | 1689 | ||
1690 | if (tp->link_config.phy_is_low_power == 0) { | 1690 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
1691 | tp->link_config.phy_is_low_power = 1; | 1691 | tp->link_config.phy_is_low_power = 1; |
1692 | tp->link_config.orig_speed = tp->link_config.speed; | 1692 | } else { |
1693 | tp->link_config.orig_duplex = tp->link_config.duplex; | 1693 | if (tp->link_config.phy_is_low_power == 0) { |
1694 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | 1694 | tp->link_config.phy_is_low_power = 1; |
1695 | } | 1695 | tp->link_config.orig_speed = tp->link_config.speed; |
1696 | tp->link_config.orig_duplex = tp->link_config.duplex; | ||
1697 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | ||
1698 | } | ||
1696 | 1699 | ||
1697 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) { | 1700 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) { |
1698 | tp->link_config.speed = SPEED_10; | 1701 | tp->link_config.speed = SPEED_10; |
1699 | tp->link_config.duplex = DUPLEX_HALF; | 1702 | tp->link_config.duplex = DUPLEX_HALF; |
1700 | tp->link_config.autoneg = AUTONEG_ENABLE; | 1703 | tp->link_config.autoneg = AUTONEG_ENABLE; |
1701 | tg3_setup_phy(tp, 0); | 1704 | tg3_setup_phy(tp, 0); |
1705 | } | ||
1702 | } | 1706 | } |
1703 | 1707 | ||
1704 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 1708 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
@@ -1729,8 +1733,10 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state) | |||
1729 | u32 mac_mode; | 1733 | u32 mac_mode; |
1730 | 1734 | ||
1731 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { | 1735 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { |
1732 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a); | 1736 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { |
1733 | udelay(40); | 1737 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a); |
1738 | udelay(40); | ||
1739 | } | ||
1734 | 1740 | ||
1735 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) | 1741 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) |
1736 | mac_mode = MAC_MODE_PORT_MODE_GMII; | 1742 | mac_mode = MAC_MODE_PORT_MODE_GMII; |
@@ -3821,7 +3827,15 @@ static int tg3_poll_work(struct tg3 *tp, int work_done, int budget) | |||
3821 | sblk->status = SD_STATUS_UPDATED | | 3827 | sblk->status = SD_STATUS_UPDATED | |
3822 | (sblk->status & ~SD_STATUS_LINK_CHG); | 3828 | (sblk->status & ~SD_STATUS_LINK_CHG); |
3823 | spin_lock(&tp->lock); | 3829 | spin_lock(&tp->lock); |
3824 | tg3_setup_phy(tp, 0); | 3830 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
3831 | tw32_f(MAC_STATUS, | ||
3832 | (MAC_STATUS_SYNC_CHANGED | | ||
3833 | MAC_STATUS_CFG_CHANGED | | ||
3834 | MAC_STATUS_MI_COMPLETION | | ||
3835 | MAC_STATUS_LNKSTATE_CHANGED)); | ||
3836 | udelay(40); | ||
3837 | } else | ||
3838 | tg3_setup_phy(tp, 0); | ||
3825 | spin_unlock(&tp->lock); | 3839 | spin_unlock(&tp->lock); |
3826 | } | 3840 | } |
3827 | } | 3841 | } |
@@ -6602,7 +6616,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
6602 | tg3_abort_hw(tp, 1); | 6616 | tg3_abort_hw(tp, 1); |
6603 | } | 6617 | } |
6604 | 6618 | ||
6605 | if (reset_phy) | 6619 | if (reset_phy && |
6620 | !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) | ||
6606 | tg3_phy_reset(tp); | 6621 | tg3_phy_reset(tp); |
6607 | 6622 | ||
6608 | err = tg3_chip_reset(tp); | 6623 | err = tg3_chip_reset(tp); |
@@ -7153,13 +7168,6 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
7153 | tw32_f(MAC_RX_MODE, tp->rx_mode); | 7168 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
7154 | udelay(10); | 7169 | udelay(10); |
7155 | 7170 | ||
7156 | if (tp->link_config.phy_is_low_power) { | ||
7157 | tp->link_config.phy_is_low_power = 0; | ||
7158 | tp->link_config.speed = tp->link_config.orig_speed; | ||
7159 | tp->link_config.duplex = tp->link_config.orig_duplex; | ||
7160 | tp->link_config.autoneg = tp->link_config.orig_autoneg; | ||
7161 | } | ||
7162 | |||
7163 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; | 7171 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; |
7164 | tw32_f(MAC_MI_MODE, tp->mi_mode); | 7172 | tw32_f(MAC_MI_MODE, tp->mi_mode); |
7165 | udelay(80); | 7173 | udelay(80); |
@@ -7210,19 +7218,28 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
7210 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | 7218 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
7211 | } | 7219 | } |
7212 | 7220 | ||
7213 | err = tg3_setup_phy(tp, 0); | 7221 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { |
7214 | if (err) | 7222 | if (tp->link_config.phy_is_low_power) { |
7215 | return err; | 7223 | tp->link_config.phy_is_low_power = 0; |
7224 | tp->link_config.speed = tp->link_config.orig_speed; | ||
7225 | tp->link_config.duplex = tp->link_config.orig_duplex; | ||
7226 | tp->link_config.autoneg = tp->link_config.orig_autoneg; | ||
7227 | } | ||
7216 | 7228 | ||
7217 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && | 7229 | err = tg3_setup_phy(tp, 0); |
7218 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) { | 7230 | if (err) |
7219 | u32 tmp; | 7231 | return err; |
7220 | 7232 | ||
7221 | /* Clear CRC stats. */ | 7233 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && |
7222 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | 7234 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) { |
7223 | tg3_writephy(tp, MII_TG3_TEST1, | 7235 | u32 tmp; |
7224 | tmp | MII_TG3_TEST1_CRC_EN); | 7236 | |
7225 | tg3_readphy(tp, 0x14, &tmp); | 7237 | /* Clear CRC stats. */ |
7238 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | ||
7239 | tg3_writephy(tp, MII_TG3_TEST1, | ||
7240 | tmp | MII_TG3_TEST1_CRC_EN); | ||
7241 | tg3_readphy(tp, 0x14, &tmp); | ||
7242 | } | ||
7226 | } | 7243 | } |
7227 | } | 7244 | } |
7228 | 7245 | ||
@@ -9644,7 +9661,8 @@ static int tg3_test_loopback(struct tg3 *tp) | |||
9644 | tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER); | 9661 | tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER); |
9645 | } | 9662 | } |
9646 | 9663 | ||
9647 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { | 9664 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && |
9665 | !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { | ||
9648 | if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK)) | 9666 | if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK)) |
9649 | err |= TG3_PHY_LOOPBACK_FAILED; | 9667 | err |= TG3_PHY_LOOPBACK_FAILED; |
9650 | } | 9668 | } |