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path: root/drivers/net/tg3.c
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-rw-r--r--drivers/net/tg3.c266
1 files changed, 169 insertions, 97 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 1828a6bf8458..2fc9893d69e1 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -68,8 +68,8 @@
68 68
69#define DRV_MODULE_NAME "tg3" 69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": " 70#define PFX DRV_MODULE_NAME ": "
71#define DRV_MODULE_VERSION "3.43" 71#define DRV_MODULE_VERSION "3.47"
72#define DRV_MODULE_RELDATE "Oct 24, 2005" 72#define DRV_MODULE_RELDATE "Dec 28, 2005"
73 73
74#define TG3_DEF_MAC_MODE 0 74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0 75#define TG3_DEF_RX_MODE 0
@@ -341,6 +341,16 @@ static struct {
341 { "interrupt test (offline)" }, 341 { "interrupt test (offline)" },
342}; 342};
343 343
344static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
345{
346 writel(val, tp->regs + off);
347}
348
349static u32 tg3_read32(struct tg3 *tp, u32 off)
350{
351 return (readl(tp->regs + off));
352}
353
344static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) 354static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
345{ 355{
346 unsigned long flags; 356 unsigned long flags;
@@ -411,13 +421,29 @@ static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
411 return val; 421 return val;
412} 422}
413 423
414static void _tw32_flush(struct tg3 *tp, u32 off, u32 val) 424/* usec_wait specifies the wait time in usec when writing to certain registers
425 * where it is unsafe to read back the register without some delay.
426 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
427 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
428 */
429static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
415{ 430{
416 tp->write32(tp, off, val); 431 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
417 if (!(tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) && 432 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
418 !(tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) && 433 /* Non-posted methods */
419 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) 434 tp->write32(tp, off, val);
420 tp->read32(tp, off); /* flush */ 435 else {
436 /* Posted method */
437 tg3_write32(tp, off, val);
438 if (usec_wait)
439 udelay(usec_wait);
440 tp->read32(tp, off);
441 }
442 /* Wait again after the read for the posted method to guarantee that
443 * the wait time is met.
444 */
445 if (usec_wait)
446 udelay(usec_wait);
421} 447}
422 448
423static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) 449static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
@@ -438,16 +464,6 @@ static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
438 readl(mbox); 464 readl(mbox);
439} 465}
440 466
441static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
442{
443 writel(val, tp->regs + off);
444}
445
446static u32 tg3_read32(struct tg3 *tp, u32 off)
447{
448 return (readl(tp->regs + off));
449}
450
451#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) 467#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
452#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) 468#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
453#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) 469#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
@@ -455,7 +471,8 @@ static u32 tg3_read32(struct tg3 *tp, u32 off)
455#define tr32_mailbox(reg) tp->read32_mbox(tp, reg) 471#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
456 472
457#define tw32(reg,val) tp->write32(tp, reg, val) 473#define tw32(reg,val) tp->write32(tp, reg, val)
458#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val)) 474#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
475#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
459#define tr32(reg) tp->read32(tp, reg) 476#define tr32(reg) tp->read32(tp, reg)
460 477
461static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) 478static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
@@ -595,21 +612,19 @@ static void tg3_switch_clocks(struct tg3 *tp)
595 612
596 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { 613 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
597 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { 614 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
598 tw32_f(TG3PCI_CLOCK_CTRL, 615 tw32_wait_f(TG3PCI_CLOCK_CTRL,
599 clock_ctrl | CLOCK_CTRL_625_CORE); 616 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
600 udelay(40);
601 } 617 }
602 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { 618 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
603 tw32_f(TG3PCI_CLOCK_CTRL, 619 tw32_wait_f(TG3PCI_CLOCK_CTRL,
604 clock_ctrl | 620 clock_ctrl |
605 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK)); 621 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
606 udelay(40); 622 40);
607 tw32_f(TG3PCI_CLOCK_CTRL, 623 tw32_wait_f(TG3PCI_CLOCK_CTRL,
608 clock_ctrl | (CLOCK_CTRL_ALTCLK)); 624 clock_ctrl | (CLOCK_CTRL_ALTCLK),
609 udelay(40); 625 40);
610 } 626 }
611 tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl); 627 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
612 udelay(40);
613} 628}
614 629
615#define PHY_BUSY_LOOPS 5000 630#define PHY_BUSY_LOOPS 5000
@@ -1017,37 +1032,50 @@ static void tg3_frob_aux_power(struct tg3 *tp)
1017 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0) 1032 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1018 return; 1033 return;
1019 1034
1020 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { 1035 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1021 tp_peer = pci_get_drvdata(tp->pdev_peer); 1036 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1022 if (!tp_peer) 1037 struct net_device *dev_peer;
1038
1039 dev_peer = pci_get_drvdata(tp->pdev_peer);
1040 if (!dev_peer)
1023 BUG(); 1041 BUG();
1042 tp_peer = netdev_priv(dev_peer);
1024 } 1043 }
1025 1044
1026
1027 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 || 1045 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1028 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) { 1046 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1047 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1048 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1029 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || 1049 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { 1050 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1031 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | 1051 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1032 (GRC_LCLCTRL_GPIO_OE0 | 1052 (GRC_LCLCTRL_GPIO_OE0 |
1033 GRC_LCLCTRL_GPIO_OE1 | 1053 GRC_LCLCTRL_GPIO_OE1 |
1034 GRC_LCLCTRL_GPIO_OE2 | 1054 GRC_LCLCTRL_GPIO_OE2 |
1035 GRC_LCLCTRL_GPIO_OUTPUT0 | 1055 GRC_LCLCTRL_GPIO_OUTPUT0 |
1036 GRC_LCLCTRL_GPIO_OUTPUT1)); 1056 GRC_LCLCTRL_GPIO_OUTPUT1),
1037 udelay(100); 1057 100);
1038 } else { 1058 } else {
1039 u32 no_gpio2; 1059 u32 no_gpio2;
1040 u32 grc_local_ctrl; 1060 u32 grc_local_ctrl = 0;
1041 1061
1042 if (tp_peer != tp && 1062 if (tp_peer != tp &&
1043 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) 1063 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1044 return; 1064 return;
1045 1065
1066 /* Workaround to prevent overdrawing Amps. */
1067 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1068 ASIC_REV_5714) {
1069 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1070 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1071 grc_local_ctrl, 100);
1072 }
1073
1046 /* On 5753 and variants, GPIO2 cannot be used. */ 1074 /* On 5753 and variants, GPIO2 cannot be used. */
1047 no_gpio2 = tp->nic_sram_data_cfg & 1075 no_gpio2 = tp->nic_sram_data_cfg &
1048 NIC_SRAM_DATA_CFG_NO_GPIO2; 1076 NIC_SRAM_DATA_CFG_NO_GPIO2;
1049 1077
1050 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | 1078 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1051 GRC_LCLCTRL_GPIO_OE1 | 1079 GRC_LCLCTRL_GPIO_OE1 |
1052 GRC_LCLCTRL_GPIO_OE2 | 1080 GRC_LCLCTRL_GPIO_OE2 |
1053 GRC_LCLCTRL_GPIO_OUTPUT1 | 1081 GRC_LCLCTRL_GPIO_OUTPUT1 |
@@ -1056,21 +1084,18 @@ static void tg3_frob_aux_power(struct tg3 *tp)
1056 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | 1084 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1057 GRC_LCLCTRL_GPIO_OUTPUT2); 1085 GRC_LCLCTRL_GPIO_OUTPUT2);
1058 } 1086 }
1059 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | 1087 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1060 grc_local_ctrl); 1088 grc_local_ctrl, 100);
1061 udelay(100);
1062 1089
1063 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; 1090 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1064 1091
1065 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | 1092 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1066 grc_local_ctrl); 1093 grc_local_ctrl, 100);
1067 udelay(100);
1068 1094
1069 if (!no_gpio2) { 1095 if (!no_gpio2) {
1070 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; 1096 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1071 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | 1097 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1072 grc_local_ctrl); 1098 grc_local_ctrl, 100);
1073 udelay(100);
1074 } 1099 }
1075 } 1100 }
1076 } else { 1101 } else {
@@ -1080,19 +1105,16 @@ static void tg3_frob_aux_power(struct tg3 *tp)
1080 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) 1105 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1081 return; 1106 return;
1082 1107
1083 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | 1108 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1084 (GRC_LCLCTRL_GPIO_OE1 | 1109 (GRC_LCLCTRL_GPIO_OE1 |
1085 GRC_LCLCTRL_GPIO_OUTPUT1)); 1110 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1086 udelay(100);
1087 1111
1088 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | 1112 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1089 (GRC_LCLCTRL_GPIO_OE1)); 1113 GRC_LCLCTRL_GPIO_OE1, 100);
1090 udelay(100);
1091 1114
1092 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | 1115 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1093 (GRC_LCLCTRL_GPIO_OE1 | 1116 (GRC_LCLCTRL_GPIO_OE1 |
1094 GRC_LCLCTRL_GPIO_OUTPUT1)); 1117 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1095 udelay(100);
1096 } 1118 }
1097 } 1119 }
1098} 1120}
@@ -1105,6 +1127,8 @@ static int tg3_setup_phy(struct tg3 *, int);
1105 1127
1106static void tg3_write_sig_post_reset(struct tg3 *, int); 1128static void tg3_write_sig_post_reset(struct tg3 *, int);
1107static int tg3_halt_cpu(struct tg3 *, u32); 1129static int tg3_halt_cpu(struct tg3 *, u32);
1130static int tg3_nvram_lock(struct tg3 *);
1131static void tg3_nvram_unlock(struct tg3 *);
1108 1132
1109static int tg3_set_power_state(struct tg3 *tp, int state) 1133static int tg3_set_power_state(struct tg3 *tp, int state)
1110{ 1134{
@@ -1133,10 +1157,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1133 udelay(100); /* Delay after power state change */ 1157 udelay(100); /* Delay after power state change */
1134 1158
1135 /* Switch out of Vaux if it is not a LOM */ 1159 /* Switch out of Vaux if it is not a LOM */
1136 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) { 1160 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
1137 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); 1161 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1138 udelay(100);
1139 }
1140 1162
1141 return 0; 1163 return 0;
1142 1164
@@ -1179,6 +1201,21 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1179 tg3_setup_phy(tp, 0); 1201 tg3_setup_phy(tp, 0);
1180 } 1202 }
1181 1203
1204 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1205 int i;
1206 u32 val;
1207
1208 for (i = 0; i < 200; i++) {
1209 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1210 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1211 break;
1212 msleep(1);
1213 }
1214 }
1215 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1216 WOL_DRV_STATE_SHUTDOWN |
1217 WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1218
1182 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps); 1219 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1183 1220
1184 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) { 1221 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
@@ -1220,10 +1257,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1220 base_val |= (CLOCK_CTRL_RXCLK_DISABLE | 1257 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1221 CLOCK_CTRL_TXCLK_DISABLE); 1258 CLOCK_CTRL_TXCLK_DISABLE);
1222 1259
1223 tw32_f(TG3PCI_CLOCK_CTRL, base_val | 1260 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1224 CLOCK_CTRL_ALTCLK | 1261 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1225 CLOCK_CTRL_PWRDOWN_PLL133);
1226 udelay(40);
1227 } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { 1262 } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1228 /* do nothing */ 1263 /* do nothing */
1229 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && 1264 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
@@ -1244,11 +1279,11 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1244 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; 1279 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1245 } 1280 }
1246 1281
1247 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1); 1282 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1248 udelay(40); 1283 40);
1249 1284
1250 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2); 1285 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1251 udelay(40); 1286 40);
1252 1287
1253 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 1288 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1254 u32 newbits3; 1289 u32 newbits3;
@@ -1262,9 +1297,20 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1262 newbits3 = CLOCK_CTRL_44MHZ_CORE; 1297 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1263 } 1298 }
1264 1299
1265 tw32_f(TG3PCI_CLOCK_CTRL, 1300 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1266 tp->pci_clock_ctrl | newbits3); 1301 tp->pci_clock_ctrl | newbits3, 40);
1267 udelay(40); 1302 }
1303 }
1304
1305 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1306 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1307 /* Turn off the PHY */
1308 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1309 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1310 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1311 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1312 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
1313 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1268 } 1314 }
1269 } 1315 }
1270 1316
@@ -1277,8 +1323,12 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1277 1323
1278 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); 1324 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1279 tw32(0x7d00, val); 1325 tw32(0x7d00, val);
1280 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) 1326 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1327 tg3_nvram_lock(tp);
1281 tg3_halt_cpu(tp, RX_CPU_BASE); 1328 tg3_halt_cpu(tp, RX_CPU_BASE);
1329 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR0);
1330 tg3_nvram_unlock(tp);
1331 }
1282 } 1332 }
1283 1333
1284 /* Finally, set the new power state. */ 1334 /* Finally, set the new power state. */
@@ -1812,7 +1862,7 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1812 } 1862 }
1813 } 1863 }
1814relink: 1864relink:
1815 if (current_link_up == 0) { 1865 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1816 u32 tmp; 1866 u32 tmp;
1817 1867
1818 tg3_phy_copper_begin(tp); 1868 tg3_phy_copper_begin(tp);
@@ -3565,12 +3615,15 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3565 if (!spin_trylock(&tp->tx_lock)) 3615 if (!spin_trylock(&tp->tx_lock))
3566 return NETDEV_TX_LOCKED; 3616 return NETDEV_TX_LOCKED;
3567 3617
3568 /* This is a hard error, log it. */
3569 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) { 3618 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3570 netif_stop_queue(dev); 3619 if (!netif_queue_stopped(dev)) {
3620 netif_stop_queue(dev);
3621
3622 /* This is a hard error, log it. */
3623 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3624 "queue awake!\n", dev->name);
3625 }
3571 spin_unlock(&tp->tx_lock); 3626 spin_unlock(&tp->tx_lock);
3572 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
3573 dev->name);
3574 return NETDEV_TX_BUSY; 3627 return NETDEV_TX_BUSY;
3575 } 3628 }
3576 3629
@@ -7098,8 +7151,13 @@ do { p = (u32 *)(orig_p + (reg)); \
7098 GET_REG32_LOOP(BUFMGR_MODE, 0x58); 7151 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7099 GET_REG32_LOOP(RDMAC_MODE, 0x08); 7152 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7100 GET_REG32_LOOP(WDMAC_MODE, 0x08); 7153 GET_REG32_LOOP(WDMAC_MODE, 0x08);
7101 GET_REG32_LOOP(RX_CPU_BASE, 0x280); 7154 GET_REG32_1(RX_CPU_MODE);
7102 GET_REG32_LOOP(TX_CPU_BASE, 0x280); 7155 GET_REG32_1(RX_CPU_STATE);
7156 GET_REG32_1(RX_CPU_PGMCTR);
7157 GET_REG32_1(RX_CPU_HWBKPT);
7158 GET_REG32_1(TX_CPU_MODE);
7159 GET_REG32_1(TX_CPU_STATE);
7160 GET_REG32_1(TX_CPU_PGMCTR);
7103 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110); 7161 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7104 GET_REG32_LOOP(FTQ_RESET, 0x120); 7162 GET_REG32_LOOP(FTQ_RESET, 0x120);
7105 GET_REG32_LOOP(MSGINT_MODE, 0x0c); 7163 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
@@ -7922,13 +7980,12 @@ static int tg3_test_memory(struct tg3 *tp)
7922 u32 offset; 7980 u32 offset;
7923 u32 len; 7981 u32 len;
7924 } mem_tbl_570x[] = { 7982 } mem_tbl_570x[] = {
7925 { 0x00000000, 0x01000}, 7983 { 0x00000000, 0x00b50},
7926 { 0x00002000, 0x1c000}, 7984 { 0x00002000, 0x1c000},
7927 { 0xffffffff, 0x00000} 7985 { 0xffffffff, 0x00000}
7928 }, mem_tbl_5705[] = { 7986 }, mem_tbl_5705[] = {
7929 { 0x00000100, 0x0000c}, 7987 { 0x00000100, 0x0000c},
7930 { 0x00000200, 0x00008}, 7988 { 0x00000200, 0x00008},
7931 { 0x00000b50, 0x00400},
7932 { 0x00004000, 0x00800}, 7989 { 0x00004000, 0x00800},
7933 { 0x00006000, 0x01000}, 7990 { 0x00006000, 0x01000},
7934 { 0x00008000, 0x02000}, 7991 { 0x00008000, 0x02000},
@@ -8530,6 +8587,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
8530 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { 8587 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
8531 tp->tg3_flags |= TG3_FLAG_NVRAM; 8588 tp->tg3_flags |= TG3_FLAG_NVRAM;
8532 8589
8590 tg3_nvram_lock(tp);
8533 tg3_enable_nvram_access(tp); 8591 tg3_enable_nvram_access(tp);
8534 8592
8535 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) 8593 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
@@ -8540,6 +8598,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
8540 tg3_get_nvram_size(tp); 8598 tg3_get_nvram_size(tp);
8541 8599
8542 tg3_disable_nvram_access(tp); 8600 tg3_disable_nvram_access(tp);
8601 tg3_nvram_unlock(tp);
8543 8602
8544 } else { 8603 } else {
8545 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED); 8604 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
@@ -8637,10 +8696,10 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
8637 if (ret == 0) 8696 if (ret == 0)
8638 *val = swab32(tr32(NVRAM_RDDATA)); 8697 *val = swab32(tr32(NVRAM_RDDATA));
8639 8698
8640 tg3_nvram_unlock(tp);
8641
8642 tg3_disable_nvram_access(tp); 8699 tg3_disable_nvram_access(tp);
8643 8700
8701 tg3_nvram_unlock(tp);
8702
8644 return ret; 8703 return ret;
8645} 8704}
8646 8705
@@ -8725,6 +8784,10 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
8725 8784
8726 offset = offset + (pagesize - page_off); 8785 offset = offset + (pagesize - page_off);
8727 8786
8787 /* Nvram lock released by tg3_nvram_read() above,
8788 * so need to get it again.
8789 */
8790 tg3_nvram_lock(tp);
8728 tg3_enable_nvram_access(tp); 8791 tg3_enable_nvram_access(tp);
8729 8792
8730 /* 8793 /*
@@ -10423,7 +10486,7 @@ static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
10423 return str; 10486 return str;
10424} 10487}
10425 10488
10426static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp) 10489static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
10427{ 10490{
10428 struct pci_dev *peer; 10491 struct pci_dev *peer;
10429 unsigned int func, devnr = tp->pdev->devfn & ~7; 10492 unsigned int func, devnr = tp->pdev->devfn & ~7;
@@ -10434,8 +10497,13 @@ static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
10434 break; 10497 break;
10435 pci_dev_put(peer); 10498 pci_dev_put(peer);
10436 } 10499 }
10437 if (!peer || peer == tp->pdev) 10500 /* 5704 can be configured in single-port mode, set peer to
10438 BUG(); 10501 * tp->pdev in that case.
10502 */
10503 if (!peer) {
10504 peer = tp->pdev;
10505 return peer;
10506 }
10439 10507
10440 /* 10508 /*
10441 * We don't need to keep the refcount elevated; there's no way 10509 * We don't need to keep the refcount elevated; there's no way
@@ -10671,8 +10739,9 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
10671 tp->rx_pending = 63; 10739 tp->rx_pending = 63;
10672 } 10740 }
10673 10741
10674 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) 10742 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10675 tp->pdev_peer = tg3_find_5704_peer(tp); 10743 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
10744 tp->pdev_peer = tg3_find_peer(tp);
10676 10745
10677 err = tg3_get_device_address(tp); 10746 err = tg3_get_device_address(tp);
10678 if (err) { 10747 if (err) {
@@ -10817,12 +10886,14 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
10817 10886
10818 tg3_full_lock(tp, 0); 10887 tg3_full_lock(tp, 0);
10819 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 10888 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10889 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
10820 tg3_full_unlock(tp); 10890 tg3_full_unlock(tp);
10821 10891
10822 err = tg3_set_power_state(tp, pci_choose_state(pdev, state)); 10892 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
10823 if (err) { 10893 if (err) {
10824 tg3_full_lock(tp, 0); 10894 tg3_full_lock(tp, 0);
10825 10895
10896 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10826 tg3_init_hw(tp); 10897 tg3_init_hw(tp);
10827 10898
10828 tp->timer.expires = jiffies + tp->timer_offset; 10899 tp->timer.expires = jiffies + tp->timer_offset;
@@ -10856,6 +10927,7 @@ static int tg3_resume(struct pci_dev *pdev)
10856 10927
10857 tg3_full_lock(tp, 0); 10928 tg3_full_lock(tp, 0);
10858 10929
10930 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10859 tg3_init_hw(tp); 10931 tg3_init_hw(tp);
10860 10932
10861 tp->timer.expires = jiffies + tp->timer_offset; 10933 tp->timer.expires = jiffies + tp->timer_offset;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 11:32:25 -0500