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path: root/drivers/net/tg3.c
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-rw-r--r--drivers/net/tg3.c101
1 files changed, 78 insertions, 23 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index d2439b85a790..71d2c5cfdad9 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -66,8 +66,8 @@
66 66
67#define DRV_MODULE_NAME "tg3" 67#define DRV_MODULE_NAME "tg3"
68#define PFX DRV_MODULE_NAME ": " 68#define PFX DRV_MODULE_NAME ": "
69#define DRV_MODULE_VERSION "3.93" 69#define DRV_MODULE_VERSION "3.94"
70#define DRV_MODULE_RELDATE "May 22, 2008" 70#define DRV_MODULE_RELDATE "August 14, 2008"
71 71
72#define TG3_DEF_MAC_MODE 0 72#define TG3_DEF_MAC_MODE 0
73#define TG3_DEF_RX_MODE 0 73#define TG3_DEF_RX_MODE 0
@@ -536,6 +536,7 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
536 return 0; 536 return 0;
537 537
538 switch (locknum) { 538 switch (locknum) {
539 case TG3_APE_LOCK_GRC:
539 case TG3_APE_LOCK_MEM: 540 case TG3_APE_LOCK_MEM:
540 break; 541 break;
541 default: 542 default:
@@ -573,6 +574,7 @@ static void tg3_ape_unlock(struct tg3 *tp, int locknum)
573 return; 574 return;
574 575
575 switch (locknum) { 576 switch (locknum) {
577 case TG3_APE_LOCK_GRC:
576 case TG3_APE_LOCK_MEM: 578 case TG3_APE_LOCK_MEM:
577 break; 579 break;
578 default: 580 default:
@@ -1018,15 +1020,43 @@ static void tg3_mdio_fini(struct tg3 *tp)
1018} 1020}
1019 1021
1020/* tp->lock is held. */ 1022/* tp->lock is held. */
1023static inline void tg3_generate_fw_event(struct tg3 *tp)
1024{
1025 u32 val;
1026
1027 val = tr32(GRC_RX_CPU_EVENT);
1028 val |= GRC_RX_CPU_DRIVER_EVENT;
1029 tw32_f(GRC_RX_CPU_EVENT, val);
1030
1031 tp->last_event_jiffies = jiffies;
1032}
1033
1034#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1035
1036/* tp->lock is held. */
1021static void tg3_wait_for_event_ack(struct tg3 *tp) 1037static void tg3_wait_for_event_ack(struct tg3 *tp)
1022{ 1038{
1023 int i; 1039 int i;
1040 unsigned int delay_cnt;
1041 long time_remain;
1042
1043 /* If enough time has passed, no wait is necessary. */
1044 time_remain = (long)(tp->last_event_jiffies + 1 +
1045 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1046 (long)jiffies;
1047 if (time_remain < 0)
1048 return;
1024 1049
1025 /* Wait for up to 2.5 milliseconds */ 1050 /* Check if we can shorten the wait time. */
1026 for (i = 0; i < 250000; i++) { 1051 delay_cnt = jiffies_to_usecs(time_remain);
1052 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1053 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1054 delay_cnt = (delay_cnt >> 3) + 1;
1055
1056 for (i = 0; i < delay_cnt; i++) {
1027 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) 1057 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1028 break; 1058 break;
1029 udelay(10); 1059 udelay(8);
1030 } 1060 }
1031} 1061}
1032 1062
@@ -1075,9 +1105,7 @@ static void tg3_ump_link_report(struct tg3 *tp)
1075 val = 0; 1105 val = 0;
1076 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); 1106 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1077 1107
1078 val = tr32(GRC_RX_CPU_EVENT); 1108 tg3_generate_fw_event(tp);
1079 val |= GRC_RX_CPU_DRIVER_EVENT;
1080 tw32_f(GRC_RX_CPU_EVENT, val);
1081} 1109}
1082 1110
1083static void tg3_link_report(struct tg3 *tp) 1111static void tg3_link_report(struct tg3 *tp)
@@ -2124,6 +2152,13 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2124 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) 2152 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE))
2125 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; 2153 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2126 2154
2155 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2156 mac_mode |= tp->mac_mode &
2157 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2158 if (mac_mode & MAC_MODE_APE_TX_EN)
2159 mac_mode |= MAC_MODE_TDE_ENABLE;
2160 }
2161
2127 tw32_f(MAC_MODE, mac_mode); 2162 tw32_f(MAC_MODE, mac_mode);
2128 udelay(100); 2163 udelay(100);
2129 2164
@@ -5493,7 +5528,7 @@ static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5493 return; 5528 return;
5494 5529
5495 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); 5530 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5496 if (apedata != APE_FW_STATUS_READY) 5531 if (!(apedata & APE_FW_STATUS_READY))
5497 return; 5532 return;
5498 5533
5499 /* Wait for up to 1 millisecond for APE to service previous event. */ 5534 /* Wait for up to 1 millisecond for APE to service previous event. */
@@ -5760,6 +5795,8 @@ static int tg3_chip_reset(struct tg3 *tp)
5760 5795
5761 tg3_mdio_stop(tp); 5796 tg3_mdio_stop(tp);
5762 5797
5798 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
5799
5763 /* No matching tg3_nvram_unlock() after this because 5800 /* No matching tg3_nvram_unlock() after this because
5764 * chip reset below will undo the nvram lock. 5801 * chip reset below will undo the nvram lock.
5765 */ 5802 */
@@ -5908,12 +5945,19 @@ static int tg3_chip_reset(struct tg3 *tp)
5908 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { 5945 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5909 tp->mac_mode = MAC_MODE_PORT_MODE_GMII; 5946 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5910 tw32_f(MAC_MODE, tp->mac_mode); 5947 tw32_f(MAC_MODE, tp->mac_mode);
5948 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
5949 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
5950 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
5951 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
5952 tw32_f(MAC_MODE, tp->mac_mode);
5911 } else 5953 } else
5912 tw32_f(MAC_MODE, 0); 5954 tw32_f(MAC_MODE, 0);
5913 udelay(40); 5955 udelay(40);
5914 5956
5915 tg3_mdio_start(tp); 5957 tg3_mdio_start(tp);
5916 5958
5959 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
5960
5917 err = tg3_poll_fw(tp); 5961 err = tg3_poll_fw(tp);
5918 if (err) 5962 if (err)
5919 return err; 5963 return err;
@@ -5935,6 +5979,7 @@ static int tg3_chip_reset(struct tg3 *tp)
5935 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); 5979 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5936 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { 5980 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5937 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; 5981 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5982 tp->last_event_jiffies = jiffies;
5938 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) 5983 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5939 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; 5984 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5940 } 5985 }
@@ -5948,15 +5993,12 @@ static void tg3_stop_fw(struct tg3 *tp)
5948{ 5993{
5949 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && 5994 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
5950 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { 5995 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
5951 u32 val;
5952
5953 /* Wait for RX cpu to ACK the previous event. */ 5996 /* Wait for RX cpu to ACK the previous event. */
5954 tg3_wait_for_event_ack(tp); 5997 tg3_wait_for_event_ack(tp);
5955 5998
5956 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); 5999 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5957 val = tr32(GRC_RX_CPU_EVENT); 6000
5958 val |= GRC_RX_CPU_DRIVER_EVENT; 6001 tg3_generate_fw_event(tp);
5959 tw32(GRC_RX_CPU_EVENT, val);
5960 6002
5961 /* Wait for RX cpu to ACK this event. */ 6003 /* Wait for RX cpu to ACK this event. */
5962 tg3_wait_for_event_ack(tp); 6004 tg3_wait_for_event_ack(tp);
@@ -7406,7 +7448,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7406 udelay(10); 7448 udelay(10);
7407 } 7449 }
7408 7450
7409 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | 7451 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7452 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7453 else
7454 tp->mac_mode = 0;
7455 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7410 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; 7456 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7411 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && 7457 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7412 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && 7458 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
@@ -7840,9 +7886,8 @@ static void tg3_timer(unsigned long __opaque)
7840 * resets. 7886 * resets.
7841 */ 7887 */
7842 if (!--tp->asf_counter) { 7888 if (!--tp->asf_counter) {
7843 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { 7889 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7844 u32 val; 7890 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7845
7846 tg3_wait_for_event_ack(tp); 7891 tg3_wait_for_event_ack(tp);
7847 7892
7848 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, 7893 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
@@ -7850,9 +7895,8 @@ static void tg3_timer(unsigned long __opaque)
7850 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); 7895 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7851 /* 5 seconds timeout */ 7896 /* 5 seconds timeout */
7852 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5); 7897 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7853 val = tr32(GRC_RX_CPU_EVENT); 7898
7854 val |= GRC_RX_CPU_DRIVER_EVENT; 7899 tg3_generate_fw_event(tp);
7855 tw32_f(GRC_RX_CPU_EVENT, val);
7856 } 7900 }
7857 tp->asf_counter = tp->asf_multiplier; 7901 tp->asf_counter = tp->asf_multiplier;
7858 } 7902 }
@@ -8422,6 +8466,11 @@ static inline unsigned long get_stat64(tg3_stat64_t *val)
8422 return ret; 8466 return ret;
8423} 8467}
8424 8468
8469static inline u64 get_estat64(tg3_stat64_t *val)
8470{
8471 return ((u64)val->high << 32) | ((u64)val->low);
8472}
8473
8425static unsigned long calc_crc_errors(struct tg3 *tp) 8474static unsigned long calc_crc_errors(struct tg3 *tp)
8426{ 8475{
8427 struct tg3_hw_stats *hw_stats = tp->hw_stats; 8476 struct tg3_hw_stats *hw_stats = tp->hw_stats;
@@ -8450,7 +8499,7 @@ static unsigned long calc_crc_errors(struct tg3 *tp)
8450 8499
8451#define ESTAT_ADD(member) \ 8500#define ESTAT_ADD(member) \
8452 estats->member = old_estats->member + \ 8501 estats->member = old_estats->member + \
8453 get_stat64(&hw_stats->member) 8502 get_estat64(&hw_stats->member)
8454 8503
8455static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp) 8504static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8456{ 8505{
@@ -12416,6 +12465,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12416 tp->misc_host_ctrl); 12465 tp->misc_host_ctrl);
12417 } 12466 }
12418 12467
12468 /* Preserve the APE MAC_MODE bits */
12469 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12470 tp->mac_mode = tr32(MAC_MODE) |
12471 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12472 else
12473 tp->mac_mode = TG3_DEF_MAC_MODE;
12474
12419 /* these are limited to 10/100 only */ 12475 /* these are limited to 10/100 only */
12420 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && 12476 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12421 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || 12477 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
@@ -13275,7 +13331,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
13275 tp->pdev = pdev; 13331 tp->pdev = pdev;
13276 tp->dev = dev; 13332 tp->dev = dev;
13277 tp->pm_cap = pm_cap; 13333 tp->pm_cap = pm_cap;
13278 tp->mac_mode = TG3_DEF_MAC_MODE;
13279 tp->rx_mode = TG3_DEF_RX_MODE; 13334 tp->rx_mode = TG3_DEF_RX_MODE;
13280 tp->tx_mode = TG3_DEF_TX_MODE; 13335 tp->tx_mode = TG3_DEF_TX_MODE;
13281 13336