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path: root/drivers/net/tg3.c
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-rw-r--r--drivers/net/tg3.c1268
1 files changed, 900 insertions, 368 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index cc4bde852542..633c128a6228 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -32,6 +32,8 @@
32#include <linux/skbuff.h> 32#include <linux/skbuff.h>
33#include <linux/ethtool.h> 33#include <linux/ethtool.h>
34#include <linux/mii.h> 34#include <linux/mii.h>
35#include <linux/phy.h>
36#include <linux/brcmphy.h>
35#include <linux/if_vlan.h> 37#include <linux/if_vlan.h>
36#include <linux/ip.h> 38#include <linux/ip.h>
37#include <linux/tcp.h> 39#include <linux/tcp.h>
@@ -64,8 +66,8 @@
64 66
65#define DRV_MODULE_NAME "tg3" 67#define DRV_MODULE_NAME "tg3"
66#define PFX DRV_MODULE_NAME ": " 68#define PFX DRV_MODULE_NAME ": "
67#define DRV_MODULE_VERSION "3.92.1" 69#define DRV_MODULE_VERSION "3.93"
68#define DRV_MODULE_RELDATE "June 9, 2008" 70#define DRV_MODULE_RELDATE "May 22, 2008"
69 71
70#define TG3_DEF_MAC_MODE 0 72#define TG3_DEF_MAC_MODE 0
71#define TG3_DEF_RX_MODE 0 73#define TG3_DEF_RX_MODE 0
@@ -203,6 +205,7 @@ static struct pci_device_id tg3_pci_tbl[] = {
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, 205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, 206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, 207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
206 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, 209 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
207 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, 210 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
208 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, 211 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
@@ -804,6 +807,569 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
804 return ret; 807 return ret;
805} 808}
806 809
810static int tg3_bmcr_reset(struct tg3 *tp)
811{
812 u32 phy_control;
813 int limit, err;
814
815 /* OK, reset it, and poll the BMCR_RESET bit until it
816 * clears or we time out.
817 */
818 phy_control = BMCR_RESET;
819 err = tg3_writephy(tp, MII_BMCR, phy_control);
820 if (err != 0)
821 return -EBUSY;
822
823 limit = 5000;
824 while (limit--) {
825 err = tg3_readphy(tp, MII_BMCR, &phy_control);
826 if (err != 0)
827 return -EBUSY;
828
829 if ((phy_control & BMCR_RESET) == 0) {
830 udelay(40);
831 break;
832 }
833 udelay(10);
834 }
835 if (limit <= 0)
836 return -EBUSY;
837
838 return 0;
839}
840
841static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
842{
843 struct tg3 *tp = (struct tg3 *)bp->priv;
844 u32 val;
845
846 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
847 return -EAGAIN;
848
849 if (tg3_readphy(tp, reg, &val))
850 return -EIO;
851
852 return val;
853}
854
855static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
856{
857 struct tg3 *tp = (struct tg3 *)bp->priv;
858
859 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
860 return -EAGAIN;
861
862 if (tg3_writephy(tp, reg, val))
863 return -EIO;
864
865 return 0;
866}
867
868static int tg3_mdio_reset(struct mii_bus *bp)
869{
870 return 0;
871}
872
873static void tg3_mdio_config(struct tg3 *tp)
874{
875 u32 val;
876
877 if (tp->mdio_bus.phy_map[PHY_ADDR]->interface !=
878 PHY_INTERFACE_MODE_RGMII)
879 return;
880
881 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
882 MAC_PHYCFG1_RGMII_SND_STAT_EN);
883 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
884 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
885 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
886 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
887 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
888 }
889 tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
890
891 val = tr32(MAC_PHYCFG2) & ~(MAC_PHYCFG2_INBAND_ENABLE);
892 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
893 val |= MAC_PHYCFG2_INBAND_ENABLE;
894 tw32(MAC_PHYCFG2, val);
895
896 val = tr32(MAC_EXT_RGMII_MODE);
897 val &= ~(MAC_RGMII_MODE_RX_INT_B |
898 MAC_RGMII_MODE_RX_QUALITY |
899 MAC_RGMII_MODE_RX_ACTIVITY |
900 MAC_RGMII_MODE_RX_ENG_DET |
901 MAC_RGMII_MODE_TX_ENABLE |
902 MAC_RGMII_MODE_TX_LOWPWR |
903 MAC_RGMII_MODE_TX_RESET);
904 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
905 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
906 val |= MAC_RGMII_MODE_RX_INT_B |
907 MAC_RGMII_MODE_RX_QUALITY |
908 MAC_RGMII_MODE_RX_ACTIVITY |
909 MAC_RGMII_MODE_RX_ENG_DET;
910 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
911 val |= MAC_RGMII_MODE_TX_ENABLE |
912 MAC_RGMII_MODE_TX_LOWPWR |
913 MAC_RGMII_MODE_TX_RESET;
914 }
915 tw32(MAC_EXT_RGMII_MODE, val);
916}
917
918static void tg3_mdio_start(struct tg3 *tp)
919{
920 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
921 mutex_lock(&tp->mdio_bus.mdio_lock);
922 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
923 mutex_unlock(&tp->mdio_bus.mdio_lock);
924 }
925
926 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
927 tw32_f(MAC_MI_MODE, tp->mi_mode);
928 udelay(80);
929
930 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)
931 tg3_mdio_config(tp);
932}
933
934static void tg3_mdio_stop(struct tg3 *tp)
935{
936 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
937 mutex_lock(&tp->mdio_bus.mdio_lock);
938 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
939 mutex_unlock(&tp->mdio_bus.mdio_lock);
940 }
941}
942
943static int tg3_mdio_init(struct tg3 *tp)
944{
945 int i;
946 u32 reg;
947 struct phy_device *phydev;
948 struct mii_bus *mdio_bus = &tp->mdio_bus;
949
950 tg3_mdio_start(tp);
951
952 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
953 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
954 return 0;
955
956 memset(mdio_bus, 0, sizeof(*mdio_bus));
957
958 mdio_bus->name = "tg3 mdio bus";
959 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%x",
960 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
961 mdio_bus->priv = tp;
962 mdio_bus->dev = &tp->pdev->dev;
963 mdio_bus->read = &tg3_mdio_read;
964 mdio_bus->write = &tg3_mdio_write;
965 mdio_bus->reset = &tg3_mdio_reset;
966 mdio_bus->phy_mask = ~(1 << PHY_ADDR);
967 mdio_bus->irq = &tp->mdio_irq[0];
968
969 for (i = 0; i < PHY_MAX_ADDR; i++)
970 mdio_bus->irq[i] = PHY_POLL;
971
972 /* The bus registration will look for all the PHYs on the mdio bus.
973 * Unfortunately, it does not ensure the PHY is powered up before
974 * accessing the PHY ID registers. A chip reset is the
975 * quickest way to bring the device back to an operational state..
976 */
977 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
978 tg3_bmcr_reset(tp);
979
980 i = mdiobus_register(mdio_bus);
981 if (i) {
982 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
983 tp->dev->name, i);
984 return i;
985 }
986
987 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
988
989 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
990
991 switch (phydev->phy_id) {
992 case TG3_PHY_ID_BCM50610:
993 phydev->interface = PHY_INTERFACE_MODE_RGMII;
994 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
995 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
996 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
997 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
998 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
999 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1000 break;
1001 case TG3_PHY_ID_BCMAC131:
1002 phydev->interface = PHY_INTERFACE_MODE_MII;
1003 break;
1004 }
1005
1006 tg3_mdio_config(tp);
1007
1008 return 0;
1009}
1010
1011static void tg3_mdio_fini(struct tg3 *tp)
1012{
1013 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1014 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1015 mdiobus_unregister(&tp->mdio_bus);
1016 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1017 }
1018}
1019
1020/* tp->lock is held. */
1021static void tg3_wait_for_event_ack(struct tg3 *tp)
1022{
1023 int i;
1024
1025 /* Wait for up to 2.5 milliseconds */
1026 for (i = 0; i < 250000; i++) {
1027 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1028 break;
1029 udelay(10);
1030 }
1031}
1032
1033/* tp->lock is held. */
1034static void tg3_ump_link_report(struct tg3 *tp)
1035{
1036 u32 reg;
1037 u32 val;
1038
1039 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1040 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1041 return;
1042
1043 tg3_wait_for_event_ack(tp);
1044
1045 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1046
1047 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1048
1049 val = 0;
1050 if (!tg3_readphy(tp, MII_BMCR, &reg))
1051 val = reg << 16;
1052 if (!tg3_readphy(tp, MII_BMSR, &reg))
1053 val |= (reg & 0xffff);
1054 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1055
1056 val = 0;
1057 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1058 val = reg << 16;
1059 if (!tg3_readphy(tp, MII_LPA, &reg))
1060 val |= (reg & 0xffff);
1061 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1062
1063 val = 0;
1064 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1065 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1066 val = reg << 16;
1067 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1068 val |= (reg & 0xffff);
1069 }
1070 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1071
1072 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1073 val = reg << 16;
1074 else
1075 val = 0;
1076 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1077
1078 val = tr32(GRC_RX_CPU_EVENT);
1079 val |= GRC_RX_CPU_DRIVER_EVENT;
1080 tw32_f(GRC_RX_CPU_EVENT, val);
1081}
1082
1083static void tg3_link_report(struct tg3 *tp)
1084{
1085 if (!netif_carrier_ok(tp->dev)) {
1086 if (netif_msg_link(tp))
1087 printk(KERN_INFO PFX "%s: Link is down.\n",
1088 tp->dev->name);
1089 tg3_ump_link_report(tp);
1090 } else if (netif_msg_link(tp)) {
1091 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1092 tp->dev->name,
1093 (tp->link_config.active_speed == SPEED_1000 ?
1094 1000 :
1095 (tp->link_config.active_speed == SPEED_100 ?
1096 100 : 10)),
1097 (tp->link_config.active_duplex == DUPLEX_FULL ?
1098 "full" : "half"));
1099
1100 printk(KERN_INFO PFX
1101 "%s: Flow control is %s for TX and %s for RX.\n",
1102 tp->dev->name,
1103 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1104 "on" : "off",
1105 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1106 "on" : "off");
1107 tg3_ump_link_report(tp);
1108 }
1109}
1110
1111static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1112{
1113 u16 miireg;
1114
1115 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1116 miireg = ADVERTISE_PAUSE_CAP;
1117 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1118 miireg = ADVERTISE_PAUSE_ASYM;
1119 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1120 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1121 else
1122 miireg = 0;
1123
1124 return miireg;
1125}
1126
1127static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1128{
1129 u16 miireg;
1130
1131 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1132 miireg = ADVERTISE_1000XPAUSE;
1133 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1134 miireg = ADVERTISE_1000XPSE_ASYM;
1135 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1136 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1137 else
1138 miireg = 0;
1139
1140 return miireg;
1141}
1142
1143static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1144{
1145 u8 cap = 0;
1146
1147 if (lcladv & ADVERTISE_PAUSE_CAP) {
1148 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1149 if (rmtadv & LPA_PAUSE_CAP)
1150 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1151 else if (rmtadv & LPA_PAUSE_ASYM)
1152 cap = TG3_FLOW_CTRL_RX;
1153 } else {
1154 if (rmtadv & LPA_PAUSE_CAP)
1155 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1156 }
1157 } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1158 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1159 cap = TG3_FLOW_CTRL_TX;
1160 }
1161
1162 return cap;
1163}
1164
1165static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1166{
1167 u8 cap = 0;
1168
1169 if (lcladv & ADVERTISE_1000XPAUSE) {
1170 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1171 if (rmtadv & LPA_1000XPAUSE)
1172 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1173 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1174 cap = TG3_FLOW_CTRL_RX;
1175 } else {
1176 if (rmtadv & LPA_1000XPAUSE)
1177 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1178 }
1179 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1180 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1181 cap = TG3_FLOW_CTRL_TX;
1182 }
1183
1184 return cap;
1185}
1186
1187static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1188{
1189 u8 autoneg;
1190 u8 flowctrl = 0;
1191 u32 old_rx_mode = tp->rx_mode;
1192 u32 old_tx_mode = tp->tx_mode;
1193
1194 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1195 autoneg = tp->mdio_bus.phy_map[PHY_ADDR]->autoneg;
1196 else
1197 autoneg = tp->link_config.autoneg;
1198
1199 if (autoneg == AUTONEG_ENABLE &&
1200 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1201 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1202 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1203 else
1204 flowctrl = tg3_resolve_flowctrl_1000T(lcladv, rmtadv);
1205 } else
1206 flowctrl = tp->link_config.flowctrl;
1207
1208 tp->link_config.active_flowctrl = flowctrl;
1209
1210 if (flowctrl & TG3_FLOW_CTRL_RX)
1211 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1212 else
1213 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1214
1215 if (old_rx_mode != tp->rx_mode)
1216 tw32_f(MAC_RX_MODE, tp->rx_mode);
1217
1218 if (flowctrl & TG3_FLOW_CTRL_TX)
1219 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1220 else
1221 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1222
1223 if (old_tx_mode != tp->tx_mode)
1224 tw32_f(MAC_TX_MODE, tp->tx_mode);
1225}
1226
1227static void tg3_adjust_link(struct net_device *dev)
1228{
1229 u8 oldflowctrl, linkmesg = 0;
1230 u32 mac_mode, lcl_adv, rmt_adv;
1231 struct tg3 *tp = netdev_priv(dev);
1232 struct phy_device *phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1233
1234 spin_lock(&tp->lock);
1235
1236 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1237 MAC_MODE_HALF_DUPLEX);
1238
1239 oldflowctrl = tp->link_config.active_flowctrl;
1240
1241 if (phydev->link) {
1242 lcl_adv = 0;
1243 rmt_adv = 0;
1244
1245 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1246 mac_mode |= MAC_MODE_PORT_MODE_MII;
1247 else
1248 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1249
1250 if (phydev->duplex == DUPLEX_HALF)
1251 mac_mode |= MAC_MODE_HALF_DUPLEX;
1252 else {
1253 lcl_adv = tg3_advert_flowctrl_1000T(
1254 tp->link_config.flowctrl);
1255
1256 if (phydev->pause)
1257 rmt_adv = LPA_PAUSE_CAP;
1258 if (phydev->asym_pause)
1259 rmt_adv |= LPA_PAUSE_ASYM;
1260 }
1261
1262 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1263 } else
1264 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1265
1266 if (mac_mode != tp->mac_mode) {
1267 tp->mac_mode = mac_mode;
1268 tw32_f(MAC_MODE, tp->mac_mode);
1269 udelay(40);
1270 }
1271
1272 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1273 tw32(MAC_TX_LENGTHS,
1274 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1275 (6 << TX_LENGTHS_IPG_SHIFT) |
1276 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1277 else
1278 tw32(MAC_TX_LENGTHS,
1279 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1280 (6 << TX_LENGTHS_IPG_SHIFT) |
1281 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1282
1283 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1284 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1285 phydev->speed != tp->link_config.active_speed ||
1286 phydev->duplex != tp->link_config.active_duplex ||
1287 oldflowctrl != tp->link_config.active_flowctrl)
1288 linkmesg = 1;
1289
1290 tp->link_config.active_speed = phydev->speed;
1291 tp->link_config.active_duplex = phydev->duplex;
1292
1293 spin_unlock(&tp->lock);
1294
1295 if (linkmesg)
1296 tg3_link_report(tp);
1297}
1298
1299static int tg3_phy_init(struct tg3 *tp)
1300{
1301 struct phy_device *phydev;
1302
1303 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1304 return 0;
1305
1306 /* Bring the PHY back to a known state. */
1307 tg3_bmcr_reset(tp);
1308
1309 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1310
1311 /* Attach the MAC to the PHY. */
1312 phydev = phy_connect(tp->dev, phydev->dev.bus_id, tg3_adjust_link,
1313 phydev->dev_flags, phydev->interface);
1314 if (IS_ERR(phydev)) {
1315 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1316 return PTR_ERR(phydev);
1317 }
1318
1319 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1320
1321 /* Mask with MAC supported features. */
1322 phydev->supported &= (PHY_GBIT_FEATURES |
1323 SUPPORTED_Pause |
1324 SUPPORTED_Asym_Pause);
1325
1326 phydev->advertising = phydev->supported;
1327
1328 printk(KERN_INFO
1329 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
1330 tp->dev->name, phydev->drv->name, phydev->dev.bus_id);
1331
1332 return 0;
1333}
1334
1335static void tg3_phy_start(struct tg3 *tp)
1336{
1337 struct phy_device *phydev;
1338
1339 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1340 return;
1341
1342 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1343
1344 if (tp->link_config.phy_is_low_power) {
1345 tp->link_config.phy_is_low_power = 0;
1346 phydev->speed = tp->link_config.orig_speed;
1347 phydev->duplex = tp->link_config.orig_duplex;
1348 phydev->autoneg = tp->link_config.orig_autoneg;
1349 phydev->advertising = tp->link_config.orig_advertising;
1350 }
1351
1352 phy_start(phydev);
1353
1354 phy_start_aneg(phydev);
1355}
1356
1357static void tg3_phy_stop(struct tg3 *tp)
1358{
1359 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1360 return;
1361
1362 phy_stop(tp->mdio_bus.phy_map[PHY_ADDR]);
1363}
1364
1365static void tg3_phy_fini(struct tg3 *tp)
1366{
1367 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1368 phy_disconnect(tp->mdio_bus.phy_map[PHY_ADDR]);
1369 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1370 }
1371}
1372
807static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) 1373static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
808{ 1374{
809 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); 1375 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
@@ -861,37 +1427,6 @@ static void tg3_phy_set_wirespeed(struct tg3 *tp)
861 (val | (1 << 15) | (1 << 4))); 1427 (val | (1 << 15) | (1 << 4)));
862} 1428}
863 1429
864static int tg3_bmcr_reset(struct tg3 *tp)
865{
866 u32 phy_control;
867 int limit, err;
868
869 /* OK, reset it, and poll the BMCR_RESET bit until it
870 * clears or we time out.
871 */
872 phy_control = BMCR_RESET;
873 err = tg3_writephy(tp, MII_BMCR, phy_control);
874 if (err != 0)
875 return -EBUSY;
876
877 limit = 5000;
878 while (limit--) {
879 err = tg3_readphy(tp, MII_BMCR, &phy_control);
880 if (err != 0)
881 return -EBUSY;
882
883 if ((phy_control & BMCR_RESET) == 0) {
884 udelay(40);
885 break;
886 }
887 udelay(10);
888 }
889 if (limit <= 0)
890 return -EBUSY;
891
892 return 0;
893}
894
895static void tg3_phy_apply_otp(struct tg3 *tp) 1430static void tg3_phy_apply_otp(struct tg3 *tp)
896{ 1431{
897 u32 otp, phy; 1432 u32 otp, phy;
@@ -1115,8 +1650,6 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1115 return err; 1650 return err;
1116} 1651}
1117 1652
1118static void tg3_link_report(struct tg3 *);
1119
1120/* This will reset the tigon3 PHY if there is no valid 1653/* This will reset the tigon3 PHY if there is no valid
1121 * link unless the FORCE argument is non-zero. 1654 * link unless the FORCE argument is non-zero.
1122 */ 1655 */
@@ -1421,7 +1954,7 @@ static void tg3_power_down_phy(struct tg3 *tp)
1421 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); 1954 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1422 udelay(40); 1955 udelay(40);
1423 return; 1956 return;
1424 } else { 1957 } else if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
1425 tg3_writephy(tp, MII_TG3_EXT_CTRL, 1958 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1426 MII_TG3_EXT_CTRL_FORCE_LED_OFF); 1959 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1427 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2); 1960 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
@@ -1495,7 +2028,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1495 "requested.\n", 2028 "requested.\n",
1496 tp->dev->name, state); 2029 tp->dev->name, state);
1497 return -EINVAL; 2030 return -EINVAL;
1498 }; 2031 }
1499 2032
1500 power_control |= PCI_PM_CTRL_PME_ENABLE; 2033 power_control |= PCI_PM_CTRL_PME_ENABLE;
1501 2034
@@ -1503,18 +2036,55 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1503 tw32(TG3PCI_MISC_HOST_CTRL, 2036 tw32(TG3PCI_MISC_HOST_CTRL,
1504 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); 2037 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1505 2038
1506 if (tp->link_config.phy_is_low_power == 0) { 2039 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
1507 tp->link_config.phy_is_low_power = 1; 2040 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
1508 tp->link_config.orig_speed = tp->link_config.speed; 2041 !tp->link_config.phy_is_low_power) {
1509 tp->link_config.orig_duplex = tp->link_config.duplex; 2042 struct phy_device *phydev;
1510 tp->link_config.orig_autoneg = tp->link_config.autoneg; 2043 u32 advertising;
1511 } 2044
2045 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
2046
2047 tp->link_config.phy_is_low_power = 1;
2048
2049 tp->link_config.orig_speed = phydev->speed;
2050 tp->link_config.orig_duplex = phydev->duplex;
2051 tp->link_config.orig_autoneg = phydev->autoneg;
2052 tp->link_config.orig_advertising = phydev->advertising;
2053
2054 advertising = ADVERTISED_TP |
2055 ADVERTISED_Pause |
2056 ADVERTISED_Autoneg |
2057 ADVERTISED_10baseT_Half;
2058
2059 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2060 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
2061 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2062 advertising |=
2063 ADVERTISED_100baseT_Half |
2064 ADVERTISED_100baseT_Full |
2065 ADVERTISED_10baseT_Full;
2066 else
2067 advertising |= ADVERTISED_10baseT_Full;
2068 }
1512 2069
1513 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) { 2070 phydev->advertising = advertising;
1514 tp->link_config.speed = SPEED_10; 2071
1515 tp->link_config.duplex = DUPLEX_HALF; 2072 phy_start_aneg(phydev);
1516 tp->link_config.autoneg = AUTONEG_ENABLE; 2073 }
1517 tg3_setup_phy(tp, 0); 2074 } else {
2075 if (tp->link_config.phy_is_low_power == 0) {
2076 tp->link_config.phy_is_low_power = 1;
2077 tp->link_config.orig_speed = tp->link_config.speed;
2078 tp->link_config.orig_duplex = tp->link_config.duplex;
2079 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2080 }
2081
2082 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2083 tp->link_config.speed = SPEED_10;
2084 tp->link_config.duplex = DUPLEX_HALF;
2085 tp->link_config.autoneg = AUTONEG_ENABLE;
2086 tg3_setup_phy(tp, 0);
2087 }
1518 } 2088 }
1519 2089
1520 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 2090 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
@@ -1545,8 +2115,10 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1545 u32 mac_mode; 2115 u32 mac_mode;
1546 2116
1547 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { 2117 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1548 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a); 2118 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
1549 udelay(40); 2119 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2120 udelay(40);
2121 }
1550 2122
1551 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) 2123 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1552 mac_mode = MAC_MODE_PORT_MODE_GMII; 2124 mac_mode = MAC_MODE_PORT_MODE_GMII;
@@ -1671,212 +2243,6 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1671 return 0; 2243 return 0;
1672} 2244}
1673 2245
1674/* tp->lock is held. */
1675static void tg3_wait_for_event_ack(struct tg3 *tp)
1676{
1677 int i;
1678
1679 /* Wait for up to 2.5 milliseconds */
1680 for (i = 0; i < 250000; i++) {
1681 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1682 break;
1683 udelay(10);
1684 }
1685}
1686
1687/* tp->lock is held. */
1688static void tg3_ump_link_report(struct tg3 *tp)
1689{
1690 u32 reg;
1691 u32 val;
1692
1693 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1694 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1695 return;
1696
1697 tg3_wait_for_event_ack(tp);
1698
1699 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1700
1701 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1702
1703 val = 0;
1704 if (!tg3_readphy(tp, MII_BMCR, &reg))
1705 val = reg << 16;
1706 if (!tg3_readphy(tp, MII_BMSR, &reg))
1707 val |= (reg & 0xffff);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1709
1710 val = 0;
1711 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1712 val = reg << 16;
1713 if (!tg3_readphy(tp, MII_LPA, &reg))
1714 val |= (reg & 0xffff);
1715 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1716
1717 val = 0;
1718 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1719 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1720 val = reg << 16;
1721 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1722 val |= (reg & 0xffff);
1723 }
1724 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1725
1726 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1727 val = reg << 16;
1728 else
1729 val = 0;
1730 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1731
1732 val = tr32(GRC_RX_CPU_EVENT);
1733 val |= GRC_RX_CPU_DRIVER_EVENT;
1734 tw32_f(GRC_RX_CPU_EVENT, val);
1735}
1736
1737static void tg3_link_report(struct tg3 *tp)
1738{
1739 if (!netif_carrier_ok(tp->dev)) {
1740 if (netif_msg_link(tp))
1741 printk(KERN_INFO PFX "%s: Link is down.\n",
1742 tp->dev->name);
1743 tg3_ump_link_report(tp);
1744 } else if (netif_msg_link(tp)) {
1745 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1746 tp->dev->name,
1747 (tp->link_config.active_speed == SPEED_1000 ?
1748 1000 :
1749 (tp->link_config.active_speed == SPEED_100 ?
1750 100 : 10)),
1751 (tp->link_config.active_duplex == DUPLEX_FULL ?
1752 "full" : "half"));
1753
1754 printk(KERN_INFO PFX
1755 "%s: Flow control is %s for TX and %s for RX.\n",
1756 tp->dev->name,
1757 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1758 "on" : "off",
1759 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1760 "on" : "off");
1761 tg3_ump_link_report(tp);
1762 }
1763}
1764
1765static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1766{
1767 u16 miireg;
1768
1769 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1770 miireg = ADVERTISE_PAUSE_CAP;
1771 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1772 miireg = ADVERTISE_PAUSE_ASYM;
1773 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1774 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1775 else
1776 miireg = 0;
1777
1778 return miireg;
1779}
1780
1781static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1782{
1783 u16 miireg;
1784
1785 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1786 miireg = ADVERTISE_1000XPAUSE;
1787 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1788 miireg = ADVERTISE_1000XPSE_ASYM;
1789 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1790 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1791 else
1792 miireg = 0;
1793
1794 return miireg;
1795}
1796
1797static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1798{
1799 u8 cap = 0;
1800
1801 if (lcladv & ADVERTISE_PAUSE_CAP) {
1802 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1803 if (rmtadv & LPA_PAUSE_CAP)
1804 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1805 else if (rmtadv & LPA_PAUSE_ASYM)
1806 cap = TG3_FLOW_CTRL_RX;
1807 } else {
1808 if (rmtadv & LPA_PAUSE_CAP)
1809 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1810 }
1811 } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1812 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1813 cap = TG3_FLOW_CTRL_TX;
1814 }
1815
1816 return cap;
1817}
1818
1819static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1820{
1821 u8 cap = 0;
1822
1823 if (lcladv & ADVERTISE_1000XPAUSE) {
1824 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1825 if (rmtadv & LPA_1000XPAUSE)
1826 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1827 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1828 cap = TG3_FLOW_CTRL_RX;
1829 } else {
1830 if (rmtadv & LPA_1000XPAUSE)
1831 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1832 }
1833 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1834 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1835 cap = TG3_FLOW_CTRL_TX;
1836 }
1837
1838 return cap;
1839}
1840
1841static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1842{
1843 u8 new_tg3_flags = 0;
1844 u32 old_rx_mode = tp->rx_mode;
1845 u32 old_tx_mode = tp->tx_mode;
1846
1847 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1848 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1849 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1850 new_tg3_flags = tg3_resolve_flowctrl_1000X(local_adv,
1851 remote_adv);
1852 else
1853 new_tg3_flags = tg3_resolve_flowctrl_1000T(local_adv,
1854 remote_adv);
1855 } else {
1856 new_tg3_flags = tp->link_config.flowctrl;
1857 }
1858
1859 tp->link_config.active_flowctrl = new_tg3_flags;
1860
1861 if (new_tg3_flags & TG3_FLOW_CTRL_RX)
1862 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1863 else
1864 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1865
1866 if (old_rx_mode != tp->rx_mode) {
1867 tw32_f(MAC_RX_MODE, tp->rx_mode);
1868 }
1869
1870 if (new_tg3_flags & TG3_FLOW_CTRL_TX)
1871 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1872 else
1873 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1874
1875 if (old_tx_mode != tp->tx_mode) {
1876 tw32_f(MAC_TX_MODE, tp->tx_mode);
1877 }
1878}
1879
1880static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) 2246static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1881{ 2247{
1882 switch (val & MII_TG3_AUX_STAT_SPDMASK) { 2248 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
@@ -1921,7 +2287,7 @@ static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8
1921 *speed = SPEED_INVALID; 2287 *speed = SPEED_INVALID;
1922 *duplex = DUPLEX_INVALID; 2288 *duplex = DUPLEX_INVALID;
1923 break; 2289 break;
1924 }; 2290 }
1925} 2291}
1926 2292
1927static void tg3_phy_copper_begin(struct tg3 *tp) 2293static void tg3_phy_copper_begin(struct tg3 *tp)
@@ -2033,7 +2399,7 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
2033 case SPEED_1000: 2399 case SPEED_1000:
2034 bmcr |= TG3_BMCR_SPEED1000; 2400 bmcr |= TG3_BMCR_SPEED1000;
2035 break; 2401 break;
2036 }; 2402 }
2037 2403
2038 if (tp->link_config.duplex == DUPLEX_FULL) 2404 if (tp->link_config.duplex == DUPLEX_FULL)
2039 bmcr |= BMCR_FULLDPLX; 2405 bmcr |= BMCR_FULLDPLX;
@@ -2731,7 +3097,7 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2731 default: 3097 default:
2732 ret = ANEG_FAILED; 3098 ret = ANEG_FAILED;
2733 break; 3099 break;
2734 }; 3100 }
2735 3101
2736 return ret; 3102 return ret;
2737} 3103}
@@ -3572,7 +3938,7 @@ static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3572 3938
3573 default: 3939 default:
3574 return -EINVAL; 3940 return -EINVAL;
3575 }; 3941 }
3576 3942
3577 /* Do not overwrite any of the map or rp information 3943 /* Do not overwrite any of the map or rp information
3578 * until we are sure we can commit to a new buffer. 3944 * until we are sure we can commit to a new buffer.
@@ -3632,7 +3998,7 @@ static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3632 3998
3633 default: 3999 default:
3634 return; 4000 return;
3635 }; 4001 }
3636 4002
3637 dest_map->skb = src_map->skb; 4003 dest_map->skb = src_map->skb;
3638 pci_unmap_addr_set(dest_map, mapping, 4004 pci_unmap_addr_set(dest_map, mapping,
@@ -3842,7 +4208,15 @@ static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
3842 sblk->status = SD_STATUS_UPDATED | 4208 sblk->status = SD_STATUS_UPDATED |
3843 (sblk->status & ~SD_STATUS_LINK_CHG); 4209 (sblk->status & ~SD_STATUS_LINK_CHG);
3844 spin_lock(&tp->lock); 4210 spin_lock(&tp->lock);
3845 tg3_setup_phy(tp, 0); 4211 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4212 tw32_f(MAC_STATUS,
4213 (MAC_STATUS_SYNC_CHANGED |
4214 MAC_STATUS_CFG_CHANGED |
4215 MAC_STATUS_MI_COMPLETION |
4216 MAC_STATUS_LNKSTATE_CHANGED));
4217 udelay(40);
4218 } else
4219 tg3_setup_phy(tp, 0);
3846 spin_unlock(&tp->lock); 4220 spin_unlock(&tp->lock);
3847 } 4221 }
3848 } 4222 }
@@ -4130,6 +4504,7 @@ static void tg3_poll_controller(struct net_device *dev)
4130static void tg3_reset_task(struct work_struct *work) 4504static void tg3_reset_task(struct work_struct *work)
4131{ 4505{
4132 struct tg3 *tp = container_of(work, struct tg3, reset_task); 4506 struct tg3 *tp = container_of(work, struct tg3, reset_task);
4507 int err;
4133 unsigned int restart_timer; 4508 unsigned int restart_timer;
4134 4509
4135 tg3_full_lock(tp, 0); 4510 tg3_full_lock(tp, 0);
@@ -4141,6 +4516,8 @@ static void tg3_reset_task(struct work_struct *work)
4141 4516
4142 tg3_full_unlock(tp); 4517 tg3_full_unlock(tp);
4143 4518
4519 tg3_phy_stop(tp);
4520
4144 tg3_netif_stop(tp); 4521 tg3_netif_stop(tp);
4145 4522
4146 tg3_full_lock(tp, 1); 4523 tg3_full_lock(tp, 1);
@@ -4156,7 +4533,8 @@ static void tg3_reset_task(struct work_struct *work)
4156 } 4533 }
4157 4534
4158 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); 4535 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4159 if (tg3_init_hw(tp, 1)) 4536 err = tg3_init_hw(tp, 1);
4537 if (err)
4160 goto out; 4538 goto out;
4161 4539
4162 tg3_netif_start(tp); 4540 tg3_netif_start(tp);
@@ -4166,6 +4544,9 @@ static void tg3_reset_task(struct work_struct *work)
4166 4544
4167out: 4545out:
4168 tg3_full_unlock(tp); 4546 tg3_full_unlock(tp);
4547
4548 if (!err)
4549 tg3_phy_start(tp);
4169} 4550}
4170 4551
4171static void tg3_dump_short_state(struct tg3 *tp) 4552static void tg3_dump_short_state(struct tg3 *tp)
@@ -4669,6 +5050,8 @@ static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4669 return 0; 5050 return 0;
4670 } 5051 }
4671 5052
5053 tg3_phy_stop(tp);
5054
4672 tg3_netif_stop(tp); 5055 tg3_netif_stop(tp);
4673 5056
4674 tg3_full_lock(tp, 1); 5057 tg3_full_lock(tp, 1);
@@ -4684,6 +5067,9 @@ static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4684 5067
4685 tg3_full_unlock(tp); 5068 tg3_full_unlock(tp);
4686 5069
5070 if (!err)
5071 tg3_phy_start(tp);
5072
4687 return err; 5073 return err;
4688} 5074}
4689 5075
@@ -4975,7 +5361,7 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int
4975 5361
4976 default: 5362 default:
4977 break; 5363 break;
4978 }; 5364 }
4979 } 5365 }
4980 5366
4981 val = tr32(ofs); 5367 val = tr32(ofs);
@@ -5217,7 +5603,7 @@ static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5217 5603
5218 default: 5604 default:
5219 break; 5605 break;
5220 }; 5606 }
5221 } 5607 }
5222 5608
5223 if (kind == RESET_KIND_INIT || 5609 if (kind == RESET_KIND_INIT ||
@@ -5242,7 +5628,7 @@ static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5242 5628
5243 default: 5629 default:
5244 break; 5630 break;
5245 }; 5631 }
5246 } 5632 }
5247 5633
5248 if (kind == RESET_KIND_SHUTDOWN) 5634 if (kind == RESET_KIND_SHUTDOWN)
@@ -5271,7 +5657,7 @@ static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5271 5657
5272 default: 5658 default:
5273 break; 5659 break;
5274 }; 5660 }
5275 } 5661 }
5276} 5662}
5277 5663
@@ -5393,6 +5779,8 @@ static int tg3_chip_reset(struct tg3 *tp)
5393 5779
5394 tg3_nvram_lock(tp); 5780 tg3_nvram_lock(tp);
5395 5781
5782 tg3_mdio_stop(tp);
5783
5396 /* No matching tg3_nvram_unlock() after this because 5784 /* No matching tg3_nvram_unlock() after this because
5397 * chip reset below will undo the nvram lock. 5785 * chip reset below will undo the nvram lock.
5398 */ 5786 */
@@ -5408,7 +5796,8 @@ static int tg3_chip_reset(struct tg3 *tp)
5408 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 5796 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
5409 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 5797 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
5410 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 5798 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5411 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 5799 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
5800 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
5412 tw32(GRC_FASTBOOT_PC, 0); 5801 tw32(GRC_FASTBOOT_PC, 0);
5413 5802
5414 /* 5803 /*
@@ -5544,6 +5933,8 @@ static int tg3_chip_reset(struct tg3 *tp)
5544 tw32_f(MAC_MODE, 0); 5933 tw32_f(MAC_MODE, 0);
5545 udelay(40); 5934 udelay(40);
5546 5935
5936 tg3_mdio_start(tp);
5937
5547 err = tg3_poll_fw(tp); 5938 err = tg3_poll_fw(tp);
5548 if (err) 5939 if (err)
5549 return err; 5940 return err;
@@ -6623,7 +7014,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6623 tg3_abort_hw(tp, 1); 7014 tg3_abort_hw(tp, 1);
6624 } 7015 }
6625 7016
6626 if (reset_phy) 7017 if (reset_phy &&
7018 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6627 tg3_phy_reset(tp); 7019 tg3_phy_reset(tp);
6628 7020
6629 err = tg3_chip_reset(tp); 7021 err = tg3_chip_reset(tp);
@@ -6699,7 +7091,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6699 return err; 7091 return err;
6700 7092
6701 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && 7093 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6702 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { 7094 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7095 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6703 /* This value is determined during the probe time DMA 7096 /* This value is determined during the probe time DMA
6704 * engine test, tg3_test_dma. 7097 * engine test, tg3_test_dma.
6705 */ 7098 */
@@ -6938,7 +7331,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6938 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | 7331 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6939 RDMAC_MODE_LNGREAD_ENAB); 7332 RDMAC_MODE_LNGREAD_ENAB);
6940 7333
6941 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) 7334 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7335 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
6942 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | 7336 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
6943 RDMAC_MODE_MBUF_RBD_CRPT_ENAB | 7337 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
6944 RDMAC_MODE_MBUF_SBD_CRPT_ENAB; 7338 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
@@ -7106,8 +7500,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7106 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) || 7500 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
7107 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) || 7501 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
7108 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) || 7502 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
7109 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)) 7503 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) ||
7110 val |= (1 << 29); 7504 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785))
7505 val |= WDMAC_MODE_STATUS_TAG_FIX;
7111 7506
7112 tw32_f(WDMAC_MODE, val); 7507 tw32_f(WDMAC_MODE, val);
7113 udelay(40); 7508 udelay(40);
@@ -7168,23 +7563,14 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7168 7563
7169 tp->rx_mode = RX_MODE_ENABLE; 7564 tp->rx_mode = RX_MODE_ENABLE;
7170 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 7565 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7171 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 7566 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7567 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
7568 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7172 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; 7569 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7173 7570
7174 tw32_f(MAC_RX_MODE, tp->rx_mode); 7571 tw32_f(MAC_RX_MODE, tp->rx_mode);
7175 udelay(10); 7572 udelay(10);
7176 7573
7177 if (tp->link_config.phy_is_low_power) {
7178 tp->link_config.phy_is_low_power = 0;
7179 tp->link_config.speed = tp->link_config.orig_speed;
7180 tp->link_config.duplex = tp->link_config.orig_duplex;
7181 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7182 }
7183
7184 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
7185 tw32_f(MAC_MI_MODE, tp->mi_mode);
7186 udelay(80);
7187
7188 tw32(MAC_LED_CTRL, tp->led_ctrl); 7574 tw32(MAC_LED_CTRL, tp->led_ctrl);
7189 7575
7190 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); 7576 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
@@ -7231,19 +7617,28 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7231 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); 7617 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7232 } 7618 }
7233 7619
7234 err = tg3_setup_phy(tp, 0); 7620 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7235 if (err) 7621 if (tp->link_config.phy_is_low_power) {
7236 return err; 7622 tp->link_config.phy_is_low_power = 0;
7623 tp->link_config.speed = tp->link_config.orig_speed;
7624 tp->link_config.duplex = tp->link_config.orig_duplex;
7625 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7626 }
7237 7627
7238 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && 7628 err = tg3_setup_phy(tp, 0);
7239 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) { 7629 if (err)
7240 u32 tmp; 7630 return err;
7241 7631
7242 /* Clear CRC stats. */ 7632 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7243 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { 7633 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7244 tg3_writephy(tp, MII_TG3_TEST1, 7634 u32 tmp;
7245 tmp | MII_TG3_TEST1_CRC_EN); 7635
7246 tg3_readphy(tp, 0x14, &tmp); 7636 /* Clear CRC stats. */
7637 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7638 tg3_writephy(tp, MII_TG3_TEST1,
7639 tmp | MII_TG3_TEST1_CRC_EN);
7640 tg3_readphy(tp, 0x14, &tmp);
7641 }
7247 } 7642 }
7248 } 7643 }
7249 7644
@@ -7296,7 +7691,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7296 7691
7297 default: 7692 default:
7298 break; 7693 break;
7299 }; 7694 }
7300 7695
7301 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) 7696 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7302 /* Write our heartbeat update interval to APE. */ 7697 /* Write our heartbeat update interval to APE. */
@@ -7758,6 +8153,8 @@ static int tg3_open(struct net_device *dev)
7758 } 8153 }
7759 } 8154 }
7760 8155
8156 tg3_phy_start(tp);
8157
7761 tg3_full_lock(tp, 0); 8158 tg3_full_lock(tp, 0);
7762 8159
7763 add_timer(&tp->timer); 8160 add_timer(&tp->timer);
@@ -8559,7 +8956,13 @@ static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
8559 8956
8560static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 8957static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8561{ 8958{
8562 struct tg3 *tp = netdev_priv(dev); 8959 struct tg3 *tp = netdev_priv(dev);
8960
8961 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8962 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8963 return -EAGAIN;
8964 return phy_ethtool_gset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
8965 }
8563 8966
8564 cmd->supported = (SUPPORTED_Autoneg); 8967 cmd->supported = (SUPPORTED_Autoneg);
8565 8968
@@ -8596,6 +8999,12 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8596{ 8999{
8597 struct tg3 *tp = netdev_priv(dev); 9000 struct tg3 *tp = netdev_priv(dev);
8598 9001
9002 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9003 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9004 return -EAGAIN;
9005 return phy_ethtool_sset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
9006 }
9007
8599 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) { 9008 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8600 /* These are the only valid advertisement bits allowed. */ 9009 /* These are the only valid advertisement bits allowed. */
8601 if (cmd->autoneg == AUTONEG_ENABLE && 9010 if (cmd->autoneg == AUTONEG_ENABLE &&
@@ -8628,7 +9037,7 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8628 tp->link_config.advertising = 0; 9037 tp->link_config.advertising = 0;
8629 tp->link_config.speed = cmd->speed; 9038 tp->link_config.speed = cmd->speed;
8630 tp->link_config.duplex = cmd->duplex; 9039 tp->link_config.duplex = cmd->duplex;
8631 } 9040 }
8632 9041
8633 tp->link_config.orig_speed = tp->link_config.speed; 9042 tp->link_config.orig_speed = tp->link_config.speed;
8634 tp->link_config.orig_duplex = tp->link_config.duplex; 9043 tp->link_config.orig_duplex = tp->link_config.duplex;
@@ -8711,7 +9120,10 @@ static int tg3_set_tso(struct net_device *dev, u32 value)
8711 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) { 9120 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8712 if (value) { 9121 if (value) {
8713 dev->features |= NETIF_F_TSO6; 9122 dev->features |= NETIF_F_TSO6;
8714 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 9123 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9124 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9125 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9126 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8715 dev->features |= NETIF_F_TSO_ECN; 9127 dev->features |= NETIF_F_TSO_ECN;
8716 } else 9128 } else
8717 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN); 9129 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
@@ -8722,7 +9134,6 @@ static int tg3_set_tso(struct net_device *dev, u32 value)
8722static int tg3_nway_reset(struct net_device *dev) 9134static int tg3_nway_reset(struct net_device *dev)
8723{ 9135{
8724 struct tg3 *tp = netdev_priv(dev); 9136 struct tg3 *tp = netdev_priv(dev);
8725 u32 bmcr;
8726 int r; 9137 int r;
8727 9138
8728 if (!netif_running(dev)) 9139 if (!netif_running(dev))
@@ -8731,17 +9142,25 @@ static int tg3_nway_reset(struct net_device *dev)
8731 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) 9142 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8732 return -EINVAL; 9143 return -EINVAL;
8733 9144
8734 spin_lock_bh(&tp->lock); 9145 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8735 r = -EINVAL; 9146 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8736 tg3_readphy(tp, MII_BMCR, &bmcr); 9147 return -EAGAIN;
8737 if (!tg3_readphy(tp, MII_BMCR, &bmcr) && 9148 r = phy_start_aneg(tp->mdio_bus.phy_map[PHY_ADDR]);
8738 ((bmcr & BMCR_ANENABLE) || 9149 } else {
8739 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) { 9150 u32 bmcr;
8740 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | 9151
8741 BMCR_ANENABLE); 9152 spin_lock_bh(&tp->lock);
8742 r = 0; 9153 r = -EINVAL;
9154 tg3_readphy(tp, MII_BMCR, &bmcr);
9155 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9156 ((bmcr & BMCR_ANENABLE) ||
9157 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9158 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9159 BMCR_ANENABLE);
9160 r = 0;
9161 }
9162 spin_unlock_bh(&tp->lock);
8743 } 9163 }
8744 spin_unlock_bh(&tp->lock);
8745 9164
8746 return r; 9165 return r;
8747} 9166}
@@ -8783,6 +9202,7 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e
8783 return -EINVAL; 9202 return -EINVAL;
8784 9203
8785 if (netif_running(dev)) { 9204 if (netif_running(dev)) {
9205 tg3_phy_stop(tp);
8786 tg3_netif_stop(tp); 9206 tg3_netif_stop(tp);
8787 irq_sync = 1; 9207 irq_sync = 1;
8788 } 9208 }
@@ -8806,6 +9226,9 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e
8806 9226
8807 tg3_full_unlock(tp); 9227 tg3_full_unlock(tp);
8808 9228
9229 if (irq_sync && !err)
9230 tg3_phy_start(tp);
9231
8809 return err; 9232 return err;
8810} 9233}
8811 9234
@@ -8829,36 +9252,92 @@ static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam
8829static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) 9252static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8830{ 9253{
8831 struct tg3 *tp = netdev_priv(dev); 9254 struct tg3 *tp = netdev_priv(dev);
8832 int irq_sync = 0, err = 0; 9255 int err = 0;
8833 9256
8834 if (netif_running(dev)) { 9257 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8835 tg3_netif_stop(tp); 9258 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8836 irq_sync = 1; 9259 return -EAGAIN;
8837 }
8838 9260
8839 tg3_full_lock(tp, irq_sync); 9261 if (epause->autoneg) {
9262 u32 newadv;
9263 struct phy_device *phydev;
8840 9264
8841 if (epause->autoneg) 9265 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
8842 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8843 else
8844 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8845 if (epause->rx_pause)
8846 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
8847 else
8848 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
8849 if (epause->tx_pause)
8850 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
8851 else
8852 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
8853 9266
8854 if (netif_running(dev)) { 9267 if (epause->rx_pause) {
8855 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 9268 if (epause->tx_pause)
8856 err = tg3_restart_hw(tp, 1); 9269 newadv = ADVERTISED_Pause;
8857 if (!err) 9270 else
8858 tg3_netif_start(tp); 9271 newadv = ADVERTISED_Pause |
8859 } 9272 ADVERTISED_Asym_Pause;
9273 } else if (epause->tx_pause) {
9274 newadv = ADVERTISED_Asym_Pause;
9275 } else
9276 newadv = 0;
9277
9278 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9279 u32 oldadv = phydev->advertising &
9280 (ADVERTISED_Pause |
9281 ADVERTISED_Asym_Pause);
9282 if (oldadv != newadv) {
9283 phydev->advertising &=
9284 ~(ADVERTISED_Pause |
9285 ADVERTISED_Asym_Pause);
9286 phydev->advertising |= newadv;
9287 err = phy_start_aneg(phydev);
9288 }
9289 } else {
9290 tp->link_config.advertising &=
9291 ~(ADVERTISED_Pause |
9292 ADVERTISED_Asym_Pause);
9293 tp->link_config.advertising |= newadv;
9294 }
9295 } else {
9296 if (epause->rx_pause)
9297 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9298 else
9299 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
8860 9300
8861 tg3_full_unlock(tp); 9301 if (epause->tx_pause)
9302 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9303 else
9304 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9305
9306 if (netif_running(dev))
9307 tg3_setup_flow_control(tp, 0, 0);
9308 }
9309 } else {
9310 int irq_sync = 0;
9311
9312 if (netif_running(dev)) {
9313 tg3_netif_stop(tp);
9314 irq_sync = 1;
9315 }
9316
9317 tg3_full_lock(tp, irq_sync);
9318
9319 if (epause->autoneg)
9320 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9321 else
9322 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9323 if (epause->rx_pause)
9324 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9325 else
9326 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
9327 if (epause->tx_pause)
9328 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9329 else
9330 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9331
9332 if (netif_running(dev)) {
9333 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9334 err = tg3_restart_hw(tp, 1);
9335 if (!err)
9336 tg3_netif_start(tp);
9337 }
9338
9339 tg3_full_unlock(tp);
9340 }
8862 9341
8863 return err; 9342 return err;
8864} 9343}
@@ -8902,7 +9381,8 @@ static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8902 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 9381 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8903 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 9382 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
8904 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 9383 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8905 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 9384 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9385 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8906 ethtool_op_set_tx_ipv6_csum(dev, data); 9386 ethtool_op_set_tx_ipv6_csum(dev, data);
8907 else 9387 else
8908 ethtool_op_set_tx_csum(dev, data); 9388 ethtool_op_set_tx_csum(dev, data);
@@ -9423,7 +9903,8 @@ static int tg3_test_memory(struct tg3 *tp)
9423 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 9903 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9424 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 9904 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 9905 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9426 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 9906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9907 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9427 mem_tbl = mem_tbl_5755; 9908 mem_tbl = mem_tbl_5755;
9428 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 9909 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9429 mem_tbl = mem_tbl_5906; 9910 mem_tbl = mem_tbl_5906;
@@ -9630,7 +10111,8 @@ static int tg3_test_loopback(struct tg3 *tp)
9630 return TG3_LOOPBACK_FAILED; 10111 return TG3_LOOPBACK_FAILED;
9631 10112
9632 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 10113 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9633 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { 10114 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10115 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
9634 int i; 10116 int i;
9635 u32 status; 10117 u32 status;
9636 10118
@@ -9658,14 +10140,16 @@ static int tg3_test_loopback(struct tg3 *tp)
9658 err |= TG3_MAC_LOOPBACK_FAILED; 10140 err |= TG3_MAC_LOOPBACK_FAILED;
9659 10141
9660 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 10142 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9661 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { 10143 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10144 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
9662 tw32(TG3_CPMU_CTRL, cpmuctrl); 10145 tw32(TG3_CPMU_CTRL, cpmuctrl);
9663 10146
9664 /* Release the mutex */ 10147 /* Release the mutex */
9665 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER); 10148 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9666 } 10149 }
9667 10150
9668 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { 10151 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10152 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9669 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK)) 10153 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9670 err |= TG3_PHY_LOOPBACK_FAILED; 10154 err |= TG3_PHY_LOOPBACK_FAILED;
9671 } 10155 }
@@ -9692,9 +10176,10 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9692 data[1] = 1; 10176 data[1] = 1;
9693 } 10177 }
9694 if (etest->flags & ETH_TEST_FL_OFFLINE) { 10178 if (etest->flags & ETH_TEST_FL_OFFLINE) {
9695 int err, irq_sync = 0; 10179 int err, err2 = 0, irq_sync = 0;
9696 10180
9697 if (netif_running(dev)) { 10181 if (netif_running(dev)) {
10182 tg3_phy_stop(tp);
9698 tg3_netif_stop(tp); 10183 tg3_netif_stop(tp);
9699 irq_sync = 1; 10184 irq_sync = 1;
9700 } 10185 }
@@ -9735,11 +10220,15 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9735 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 10220 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9736 if (netif_running(dev)) { 10221 if (netif_running(dev)) {
9737 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 10222 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9738 if (!tg3_restart_hw(tp, 1)) 10223 err2 = tg3_restart_hw(tp, 1);
10224 if (!err2)
9739 tg3_netif_start(tp); 10225 tg3_netif_start(tp);
9740 } 10226 }
9741 10227
9742 tg3_full_unlock(tp); 10228 tg3_full_unlock(tp);
10229
10230 if (irq_sync && !err2)
10231 tg3_phy_start(tp);
9743 } 10232 }
9744 if (tp->link_config.phy_is_low_power) 10233 if (tp->link_config.phy_is_low_power)
9745 tg3_set_power_state(tp, PCI_D3hot); 10234 tg3_set_power_state(tp, PCI_D3hot);
@@ -9752,6 +10241,12 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9752 struct tg3 *tp = netdev_priv(dev); 10241 struct tg3 *tp = netdev_priv(dev);
9753 int err; 10242 int err;
9754 10243
10244 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10245 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10246 return -EAGAIN;
10247 return phy_mii_ioctl(tp->mdio_bus.phy_map[PHY_ADDR], data, cmd);
10248 }
10249
9755 switch(cmd) { 10250 switch(cmd) {
9756 case SIOCGMIIPHY: 10251 case SIOCGMIIPHY:
9757 data->phy_id = PHY_ADDR; 10252 data->phy_id = PHY_ADDR;
@@ -10294,7 +10789,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
10294 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) 10789 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10295 tg3_get_5755_nvram_info(tp); 10790 tg3_get_5755_nvram_info(tp);
10296 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 10791 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10297 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) 10792 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10793 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10298 tg3_get_5787_nvram_info(tp); 10794 tg3_get_5787_nvram_info(tp);
10299 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 10795 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10300 tg3_get_5761_nvram_info(tp); 10796 tg3_get_5761_nvram_info(tp);
@@ -10625,6 +11121,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10625 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) && 11121 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
10626 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) && 11122 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
10627 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) && 11123 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
11124 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) &&
10628 (tp->nvram_jedecnum == JEDEC_ST) && 11125 (tp->nvram_jedecnum == JEDEC_ST) &&
10629 (nvram_cmd & NVRAM_CMD_FIRST)) { 11126 (nvram_cmd & NVRAM_CMD_FIRST)) {
10630 11127
@@ -10807,7 +11304,7 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10807 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); 11304 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10808 if (val == NIC_SRAM_DATA_SIG_MAGIC) { 11305 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10809 u32 nic_cfg, led_cfg; 11306 u32 nic_cfg, led_cfg;
10810 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id; 11307 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
10811 int eeprom_phy_serdes = 0; 11308 int eeprom_phy_serdes = 0;
10812 11309
10813 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); 11310 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
@@ -10821,6 +11318,9 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10821 (ver > 0) && (ver < 0x100)) 11318 (ver > 0) && (ver < 0x100))
10822 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); 11319 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10823 11320
11321 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11322 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11323
10824 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == 11324 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10825 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) 11325 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10826 eeprom_phy_serdes = 1; 11326 eeprom_phy_serdes = 1;
@@ -10893,7 +11393,7 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10893 LED_CTRL_MODE_PHY_2); 11393 LED_CTRL_MODE_PHY_2);
10894 break; 11394 break;
10895 11395
10896 }; 11396 }
10897 11397
10898 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || 11398 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10899 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && 11399 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
@@ -10945,6 +11445,13 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10945 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) 11445 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
10946 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; 11446 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10947 } 11447 }
11448
11449 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11450 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11451 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11452 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11453 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11454 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
10948 } 11455 }
10949} 11456}
10950 11457
@@ -11003,6 +11510,9 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
11003 u32 hw_phy_id, hw_phy_id_masked; 11510 u32 hw_phy_id, hw_phy_id_masked;
11004 int err; 11511 int err;
11005 11512
11513 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11514 return tg3_phy_init(tp);
11515
11006 /* Reading the PHY ID register can conflict with ASF 11516 /* Reading the PHY ID register can conflict with ASF
11007 * firwmare access to the PHY hardware. 11517 * firwmare access to the PHY hardware.
11008 */ 11518 */
@@ -11525,6 +12035,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11525 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 12035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11526 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 12036 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11527 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || 12037 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
11528 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || 12039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11529 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) 12040 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11530 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS; 12041 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
@@ -11546,6 +12057,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11546 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 12057 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11547 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 12058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11548 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || 12059 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12060 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
11549 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 12061 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11550 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2; 12062 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
11551 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI; 12063 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
@@ -11558,14 +12070,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11558 } 12070 }
11559 } 12071 }
11560 12072
11561 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && 12073 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11562 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 && 12074 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11563 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11564 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
11565 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
11566 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
11567 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
11568 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
11569 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE; 12075 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11570 12076
11571 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); 12077 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
@@ -11754,7 +12260,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11754 } 12260 }
11755 12261
11756 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 12262 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11757 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { 12263 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12264 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
11758 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT; 12265 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
11759 12266
11760 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 || 12267 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
@@ -11847,7 +12354,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11847 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG; 12354 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
11848 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) 12355 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
11849 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM; 12356 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
11850 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) 12357 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12358 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
11851 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG; 12359 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
11852 } 12360 }
11853 12361
@@ -11858,8 +12366,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11858 tp->phy_otp = TG3_OTP_DEFAULT; 12366 tp->phy_otp = TG3_OTP_DEFAULT;
11859 } 12367 }
11860 12368
11861 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 12369 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
11862 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11863 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; 12370 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
11864 else 12371 else
11865 tp->mi_mode = MAC_MI_MODE_BASE; 12372 tp->mi_mode = MAC_MI_MODE_BASE;
@@ -11869,9 +12376,12 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11869 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) 12376 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
11870 tp->coalesce_mode |= HOSTCC_MODE_32BYTE; 12377 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
11871 12378
11872 /* Initialize MAC MI mode, polling disabled. */ 12379 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11873 tw32_f(MAC_MI_MODE, tp->mi_mode); 12380 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
11874 udelay(80); 12381
12382 err = tg3_mdio_init(tp);
12383 if (err)
12384 return err;
11875 12385
11876 /* Initialize data/descriptor byte/word swapping. */ 12386 /* Initialize data/descriptor byte/word swapping. */
11877 val = tr32(GRC_MODE); 12387 val = tr32(GRC_MODE);
@@ -11952,6 +12462,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11952 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n", 12462 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
11953 pci_name(tp->pdev), err); 12463 pci_name(tp->pdev), err);
11954 /* ... but do not return immediately ... */ 12464 /* ... but do not return immediately ... */
12465 tg3_mdio_fini(tp);
11955 } 12466 }
11956 12467
11957 tg3_read_partno(tp); 12468 tg3_read_partno(tp);
@@ -11999,6 +12510,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11999 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 12510 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12000 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 12511 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12001 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || 12512 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12513 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12002 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 12514 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12003 tp->dev->hard_start_xmit = tg3_start_xmit; 12515 tp->dev->hard_start_xmit = tg3_start_xmit;
12004 else 12516 else
@@ -12201,7 +12713,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12201 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | 12713 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12202 DMA_RWCTRL_WRITE_BNDRY_384_PCIX); 12714 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12203 break; 12715 break;
12204 }; 12716 }
12205 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { 12717 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12206 switch (cacheline_size) { 12718 switch (cacheline_size) {
12207 case 16: 12719 case 16:
@@ -12218,7 +12730,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12218 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; 12730 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12219 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; 12731 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12220 break; 12732 break;
12221 }; 12733 }
12222 } else { 12734 } else {
12223 switch (cacheline_size) { 12735 switch (cacheline_size) {
12224 case 16: 12736 case 16:
@@ -12262,7 +12774,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12262 val |= (DMA_RWCTRL_READ_BNDRY_1024 | 12774 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12263 DMA_RWCTRL_WRITE_BNDRY_1024); 12775 DMA_RWCTRL_WRITE_BNDRY_1024);
12264 break; 12776 break;
12265 }; 12777 }
12266 } 12778 }
12267 12779
12268out: 12780out:
@@ -12622,7 +13134,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp)
12622 case PHY_ID_BCM8002: return "8002/serdes"; 13134 case PHY_ID_BCM8002: return "8002/serdes";
12623 case 0: return "serdes"; 13135 case 0: return "serdes";
12624 default: return "unknown"; 13136 default: return "unknown";
12625 }; 13137 }
12626} 13138}
12627 13139
12628static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) 13140static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
@@ -12923,7 +13435,10 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
12923 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) && 13435 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
12924 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) 13436 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
12925 dev->features |= NETIF_F_TSO6; 13437 dev->features |= NETIF_F_TSO6;
12926 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 13438 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13439 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13440 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13441 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12927 dev->features |= NETIF_F_TSO_ECN; 13442 dev->features |= NETIF_F_TSO_ECN;
12928 } 13443 }
12929 13444
@@ -12989,7 +13504,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
12989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 13504 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12990 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 13505 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12991 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 13506 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 13507 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13508 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12993 dev->features |= NETIF_F_IPV6_CSUM; 13509 dev->features |= NETIF_F_IPV6_CSUM;
12994 13510
12995 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; 13511 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
@@ -13071,6 +13587,12 @@ static void __devexit tg3_remove_one(struct pci_dev *pdev)
13071 struct tg3 *tp = netdev_priv(dev); 13587 struct tg3 *tp = netdev_priv(dev);
13072 13588
13073 flush_scheduled_work(); 13589 flush_scheduled_work();
13590
13591 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13592 tg3_phy_fini(tp);
13593 tg3_mdio_fini(tp);
13594 }
13595
13074 unregister_netdev(dev); 13596 unregister_netdev(dev);
13075 if (tp->aperegs) { 13597 if (tp->aperegs) {
13076 iounmap(tp->aperegs); 13598 iounmap(tp->aperegs);
@@ -13103,6 +13625,7 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13103 return 0; 13625 return 0;
13104 13626
13105 flush_scheduled_work(); 13627 flush_scheduled_work();
13628 tg3_phy_stop(tp);
13106 tg3_netif_stop(tp); 13629 tg3_netif_stop(tp);
13107 13630
13108 del_timer_sync(&tp->timer); 13631 del_timer_sync(&tp->timer);
@@ -13120,10 +13643,13 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13120 13643
13121 err = tg3_set_power_state(tp, pci_choose_state(pdev, state)); 13644 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
13122 if (err) { 13645 if (err) {
13646 int err2;
13647
13123 tg3_full_lock(tp, 0); 13648 tg3_full_lock(tp, 0);
13124 13649
13125 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 13650 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13126 if (tg3_restart_hw(tp, 1)) 13651 err2 = tg3_restart_hw(tp, 1);
13652 if (err2)
13127 goto out; 13653 goto out;
13128 13654
13129 tp->timer.expires = jiffies + tp->timer_offset; 13655 tp->timer.expires = jiffies + tp->timer_offset;
@@ -13134,6 +13660,9 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13134 13660
13135out: 13661out:
13136 tg3_full_unlock(tp); 13662 tg3_full_unlock(tp);
13663
13664 if (!err2)
13665 tg3_phy_start(tp);
13137 } 13666 }
13138 13667
13139 return err; 13668 return err;
@@ -13171,6 +13700,9 @@ static int tg3_resume(struct pci_dev *pdev)
13171out: 13700out:
13172 tg3_full_unlock(tp); 13701 tg3_full_unlock(tp);
13173 13702
13703 if (!err)
13704 tg3_phy_start(tp);
13705
13174 return err; 13706 return err;
13175} 13707}
13176 13708
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-08 05:00:51 -0500