1 files changed, 19 insertions, 19 deletions
diff --git a/drivers/net/tc35815.c b/drivers/net/tc35815.c
index b6eec8cea209..7ca51cebcddd 100644
--- a/drivers/net/tc35815.c
+++ b/drivers/net/tc35815.c
@@ -119,13 +119,13 @@ struct tc35815_regs {
 /*
 * Bit assignments
 */
-/* DMA_Ctl bit asign ------------------------------------------------------- */
+/* DMA_Ctl bit assign ------------------------------------------------------- */
 #define DMA_RxAlign            0x00c00000 /* 1:Reception Alignment           */
 #define DMA_RxAlign_1          0x00400000
 #define DMA_RxAlign_2          0x00800000
 #define DMA_RxAlign_3          0x00c00000
 #define DMA_M66EnStat          0x00080000 /* 1:66MHz Enable State            */
-#define DMA_IntMask            0x00040000 /* 1:Interupt mask                 */
+#define DMA_IntMask            0x00040000 /* 1:Interrupt mask                */
 #define DMA_SWIntReq           0x00020000 /* 1:Software Interrupt request    */
 #define DMA_TxWakeUp           0x00010000 /* 1:Transmit Wake Up              */
 #define DMA_RxBigE             0x00008000 /* 1:Receive Big Endian            */
@@ -134,11 +134,11 @@ struct tc35815_regs {
 #define DMA_PowrMgmnt          0x00001000 /* 1:Power Management              */
 #define DMA_DmBurst_Mask       0x000001fc /* DMA Burst size                  */
-/* RxFragSize bit asign ---------------------------------------------------- */
+/* RxFragSize bit assign ---------------------------------------------------- */
 #define RxFrag_EnPack          0x00008000 /* 1:Enable Packing                */
 #define RxFrag_MinFragMask     0x00000ffc /* Minimum Fragment                */
-/* MAC_Ctl bit asign ------------------------------------------------------- */
+/* MAC_Ctl bit assign ------------------------------------------------------- */
 #define MAC_Link10             0x00008000 /* 1:Link Status 10Mbits           */
 #define MAC_EnMissRoll         0x00002000 /* 1:Enable Missed Roll            */
 #define MAC_MissRoll           0x00000400 /* 1:Missed Roll                   */
@@ -152,7 +152,7 @@ struct tc35815_regs {
 #define MAC_HaltImm            0x00000002 /* 1:Halt Immediate                */
 #define MAC_HaltReq            0x00000001 /* 1:Halt request                  */
-/* PROM_Ctl bit asign ------------------------------------------------------ */
+/* PROM_Ctl bit assign ------------------------------------------------------ */
 #define PROM_Busy              0x00008000 /* 1:Busy (Start Operation)        */
 #define PROM_Read              0x00004000 /*10:Read operation                */
 #define PROM_Write             0x00002000 /*01:Write operation               */
@@ -162,7 +162,7 @@ struct tc35815_regs {
 #define PROM_Addr_Ena          0x00000030 /*11xxxx:PROM Write enable         */
                                          /*00xxxx:           disable        */
-/* CAM_Ctl bit asign ------------------------------------------------------- */
+/* CAM_Ctl bit assign ------------------------------------------------------- */
 #define CAM_CompEn             0x00000010 /* 1:CAM Compare Enable            */
 #define CAM_NegCAM             0x00000008 /* 1:Reject packets CAM recognizes,*/
                                          /*                    accept other */
@@ -170,7 +170,7 @@ struct tc35815_regs {
 #define CAM_GroupAcc           0x00000002 /* 1:Multicast assept              */
 #define CAM_StationAcc         0x00000001 /* 1:unicast accept                */
-/* CAM_Ena bit asign ------------------------------------------------------- */
+/* CAM_Ena bit assign ------------------------------------------------------- */
 #define CAM_ENTRY_MAX                  21   /* CAM Data entry max count      */
 #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits)  */
 #define CAM_Ena_Bit(index)      (1 << (index))
@@ -178,7 +178,7 @@ struct tc35815_regs {
 #define CAM_ENTRY_SOURCE        1
 #define CAM_ENTRY_MACCTL        20
-/* Tx_Ctl bit asign -------------------------------------------------------- */
+/* Tx_Ctl bit assign -------------------------------------------------------- */
 #define Tx_En                  0x00000001 /* 1:Transmit enable               */
 #define Tx_TxHalt              0x00000002 /* 1:Transmit Halt Request         */
 #define Tx_NoPad               0x00000004 /* 1:Suppress Padding              */
@@ -192,7 +192,7 @@ struct tc35815_regs {
 #define Tx_EnTxPar             0x00002000 /* 1:Enable Transmit Parity        */
 #define Tx_EnComp              0x00004000 /* 1:Enable Completion             */
-/* Tx_Stat bit asign ------------------------------------------------------- */
+/* Tx_Stat bit assign ------------------------------------------------------- */
 #define Tx_TxColl_MASK         0x0000000F /* Tx Collision Count              */
 #define Tx_ExColl              0x00000010 /* Excessive Collision             */
 #define Tx_TXDefer             0x00000020 /* Transmit Defered                */
@@ -208,7 +208,7 @@ struct tc35815_regs {
 #define Tx_Halted              0x00008000 /* Tx Halted                       */
 #define Tx_SQErr               0x00010000 /* Signal Quality Error(SQE)       */
-/* Rx_Ctl bit asign -------------------------------------------------------- */
+/* Rx_Ctl bit assign -------------------------------------------------------- */
 #define Rx_EnGood              0x00004000 /* 1:Enable Good                   */
 #define Rx_EnRxPar             0x00002000 /* 1:Enable Receive Parity         */
 #define Rx_EnLongErr           0x00000800 /* 1:Enable Long Error             */
@@ -222,7 +222,7 @@ struct tc35815_regs {
 #define Rx_RxHalt              0x00000002 /* 1:Receive Halt Request          */
 #define Rx_RxEn                0x00000001 /* 1:Receive Intrrupt Enable       */
-/* Rx_Stat bit asign ------------------------------------------------------- */
+/* Rx_Stat bit assign ------------------------------------------------------- */
 #define Rx_Halted              0x00008000 /* Rx Halted                       */
 #define Rx_Good                0x00004000 /* Rx Good                         */
 #define Rx_RxPar               0x00002000 /* Rx Parity Error                 */
@@ -238,7 +238,7 @@ struct tc35815_regs {
 #define Rx_Stat_Mask           0x0000FFF0 /* Rx All Status Mask              */
-/* Int_En bit asign -------------------------------------------------------- */
+/* Int_En bit assign -------------------------------------------------------- */
 #define Int_NRAbtEn            0x00000800 /* 1:Non-recoverable Abort Enable  */
 #define Int_TxCtlCmpEn         0x00000400 /* 1:Transmit Ctl Complete Enable  */
 #define Int_DmParErrEn         0x00000200 /* 1:DMA Parity Error Enable       */
@@ -253,7 +253,7 @@ struct tc35815_regs {
 #define Int_FDAExEn            0x00000001 /* 1:Free Descriptor Area          */
                                          /*               Exhausted Enable  */
-/* Int_Src bit asign ------------------------------------------------------- */
+/* Int_Src bit assign ------------------------------------------------------- */
 #define Int_NRabt              0x00004000 /* 1:Non Recoverable error         */
 #define Int_DmParErrStat       0x00002000 /* 1:DMA Parity Error & Clear      */
 #define Int_BLEx               0x00001000 /* 1:Buffer List Empty & Clear     */
@@ -270,8 +270,8 @@ struct tc35815_regs {
 #define Int_IntMacRx           0x00000002 /* 1:Rx controller & Clear         */
 #define Int_IntMacTx           0x00000001 /* 1:Tx controller & Clear         */
-/* MD_CA bit asign --------------------------------------------------------- */
+/* MD_CA bit assign --------------------------------------------------------- */
-#define MD_CA_PreSup           0x00001000 /* 1:Preamble Supress              */
+#define MD_CA_PreSup           0x00001000 /* 1:Preamble Suppress                     */
 #define MD_CA_Busy             0x00000800 /* 1:Busy (Start Operation)        */
 #define MD_CA_Wr               0x00000400 /* 1:Write 0:Read                  */
@@ -296,7 +296,7 @@ struct BDesc {
 #define FD_ALIGN        16
-/* Frame Descripter bit asign ---------------------------------------------- */
+/* Frame Descripter bit assign ---------------------------------------------- */
 #define FD_FDLength_MASK       0x0000FFFF /* Length MASK                     */
 #define FD_BDCnt_MASK          0x001F0000 /* BD count MASK in FD             */
 #define FD_FrmOpt_MASK         0x7C000000 /* Frame option MASK               */
@@ -309,8 +309,8 @@ struct BDesc {
 #define FD_Next_EOL            0x00000001 /* FD EOL indicator                */
 #define FD_BDCnt_SHIFT         16
-/* Buffer Descripter bit asign --------------------------------------------- */
+/* Buffer Descripter bit assign --------------------------------------------- */
-#define BD_BuffLength_MASK     0x0000FFFF /* Recieve Data Size               */
+#define BD_BuffLength_MASK     0x0000FFFF /* Receive Data Size               */
 #define BD_RxBDID_MASK         0x00FF0000 /* BD ID Number MASK               */
 #define BD_RxBDSeqN_MASK       0x7F000000 /* Rx BD Sequence Number           */
 #define BD_CownsBD             0x80000000 /* BD Controller owner bit         */
@@ -339,7 +339,7 @@ struct BDesc {
 #define TX_THRESHOLD    1024
 /* used threshold with packet max byte for low pci transfer ability.*/
 #define TX_THRESHOLD_MAX 1536
-/* setting threshold max value when overrun error occured this count. */
+/* setting threshold max value when overrun error occurred this count. */
 #define TX_THRESHOLD_KEEP_LIMIT 10
 /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */

diff --git a/drivers/net/tc35815.c b/drivers/net/tc35815.c index b6eec8cea209..7ca51cebcddd 100644 --- a/drivers/net/tc35815.c +++ b/drivers/net/tc35815.c
@@ -119,13 +119,13 @@ struct tc35815_regs {
119	/*	119	/*
120	* Bit assignments	120	* Bit assignments
121	*/	121	*/
122	/* DMA_Ctl bit asign ------------------------------------------------------- */	122	/* DMA_Ctl bit assign ------------------------------------------------------- */
123	#define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */	123	#define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */
124	#define DMA_RxAlign_1 0x00400000	124	#define DMA_RxAlign_1 0x00400000
125	#define DMA_RxAlign_2 0x00800000	125	#define DMA_RxAlign_2 0x00800000
126	#define DMA_RxAlign_3 0x00c00000	126	#define DMA_RxAlign_3 0x00c00000
127	#define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */	127	#define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */
128	#define DMA_IntMask 0x00040000 /* 1:Interupt mask */	128	#define DMA_IntMask 0x00040000 /* 1:Interrupt mask */
129	#define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */	129	#define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
130	#define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */	130	#define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
131	#define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */	131	#define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
@@ -134,11 +134,11 @@ struct tc35815_regs {
134	#define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */	134	#define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
135	#define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */	135	#define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
136		136
137	/* RxFragSize bit asign ---------------------------------------------------- */	137	/* RxFragSize bit assign ---------------------------------------------------- */
138	#define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */	138	#define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
139	#define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */	139	#define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
140		140
141	/* MAC_Ctl bit asign ------------------------------------------------------- */	141	/* MAC_Ctl bit assign ------------------------------------------------------- */
142	#define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */	142	#define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
143	#define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */	143	#define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
144	#define MAC_MissRoll 0x00000400 /* 1:Missed Roll */	144	#define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
@@ -152,7 +152,7 @@ struct tc35815_regs {
152	#define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */	152	#define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
153	#define MAC_HaltReq 0x00000001 /* 1:Halt request */	153	#define MAC_HaltReq 0x00000001 /* 1:Halt request */
154		154
155	/* PROM_Ctl bit asign ------------------------------------------------------ */	155	/* PROM_Ctl bit assign ------------------------------------------------------ */
156	#define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */	156	#define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
157	#define PROM_Read 0x00004000 /10:Read operation /	157	#define PROM_Read 0x00004000 /10:Read operation /
158	#define PROM_Write 0x00002000 /01:Write operation /	158	#define PROM_Write 0x00002000 /01:Write operation /
@@ -162,7 +162,7 @@ struct tc35815_regs {
162	#define PROM_Addr_Ena 0x00000030 /11xxxx:PROM Write enable /	162	#define PROM_Addr_Ena 0x00000030 /11xxxx:PROM Write enable /
163	/00xxxx: disable /	163	/00xxxx: disable /
164		164
165	/* CAM_Ctl bit asign ------------------------------------------------------- */	165	/* CAM_Ctl bit assign ------------------------------------------------------- */
166	#define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */	166	#define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
167	#define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/	167	#define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
168	/* accept other */	168	/* accept other */
@@ -170,7 +170,7 @@ struct tc35815_regs {
170	#define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */	170	#define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
171	#define CAM_StationAcc 0x00000001 /* 1:unicast accept */	171	#define CAM_StationAcc 0x00000001 /* 1:unicast accept */
172		172
173	/* CAM_Ena bit asign ------------------------------------------------------- */	173	/* CAM_Ena bit assign ------------------------------------------------------- */
174	#define CAM_ENTRY_MAX 21 /* CAM Data entry max count */	174	#define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
175	#define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */	175	#define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
176	#define CAM_Ena_Bit(index) (1 << (index))	176	#define CAM_Ena_Bit(index) (1 << (index))
@@ -178,7 +178,7 @@ struct tc35815_regs {
178	#define CAM_ENTRY_SOURCE 1	178	#define CAM_ENTRY_SOURCE 1
179	#define CAM_ENTRY_MACCTL 20	179	#define CAM_ENTRY_MACCTL 20
180		180
181	/* Tx_Ctl bit asign -------------------------------------------------------- */	181	/* Tx_Ctl bit assign -------------------------------------------------------- */
182	#define Tx_En 0x00000001 /* 1:Transmit enable */	182	#define Tx_En 0x00000001 /* 1:Transmit enable */
183	#define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */	183	#define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
184	#define Tx_NoPad 0x00000004 /* 1:Suppress Padding */	184	#define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
@@ -192,7 +192,7 @@ struct tc35815_regs {
192	#define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */	192	#define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
193	#define Tx_EnComp 0x00004000 /* 1:Enable Completion */	193	#define Tx_EnComp 0x00004000 /* 1:Enable Completion */
194		194
195	/* Tx_Stat bit asign ------------------------------------------------------- */	195	/* Tx_Stat bit assign ------------------------------------------------------- */
196	#define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */	196	#define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
197	#define Tx_ExColl 0x00000010 /* Excessive Collision */	197	#define Tx_ExColl 0x00000010 /* Excessive Collision */
198	#define Tx_TXDefer 0x00000020 /* Transmit Defered */	198	#define Tx_TXDefer 0x00000020 /* Transmit Defered */
@@ -208,7 +208,7 @@ struct tc35815_regs {
208	#define Tx_Halted 0x00008000 /* Tx Halted */	208	#define Tx_Halted 0x00008000 /* Tx Halted */
209	#define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */	209	#define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
210		210
211	/* Rx_Ctl bit asign -------------------------------------------------------- */	211	/* Rx_Ctl bit assign -------------------------------------------------------- */
212	#define Rx_EnGood 0x00004000 /* 1:Enable Good */	212	#define Rx_EnGood 0x00004000 /* 1:Enable Good */
213	#define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */	213	#define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
214	#define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */	214	#define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
@@ -222,7 +222,7 @@ struct tc35815_regs {
222	#define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */	222	#define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
223	#define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */	223	#define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
224		224
225	/* Rx_Stat bit asign ------------------------------------------------------- */	225	/* Rx_Stat bit assign ------------------------------------------------------- */
226	#define Rx_Halted 0x00008000 /* Rx Halted */	226	#define Rx_Halted 0x00008000 /* Rx Halted */
227	#define Rx_Good 0x00004000 /* Rx Good */	227	#define Rx_Good 0x00004000 /* Rx Good */
228	#define Rx_RxPar 0x00002000 /* Rx Parity Error */	228	#define Rx_RxPar 0x00002000 /* Rx Parity Error */
@@ -238,7 +238,7 @@ struct tc35815_regs {
238		238
239	#define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */	239	#define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */
240		240
241	/* Int_En bit asign -------------------------------------------------------- */	241	/* Int_En bit assign -------------------------------------------------------- */
242	#define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */	242	#define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
243	#define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */	243	#define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */
244	#define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */	244	#define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
@@ -253,7 +253,7 @@ struct tc35815_regs {
253	#define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */	253	#define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
254	/* Exhausted Enable */	254	/* Exhausted Enable */
255		255
256	/* Int_Src bit asign ------------------------------------------------------- */	256	/* Int_Src bit assign ------------------------------------------------------- */
257	#define Int_NRabt 0x00004000 /* 1:Non Recoverable error */	257	#define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
258	#define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */	258	#define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
259	#define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */	259	#define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
@@ -270,8 +270,8 @@ struct tc35815_regs {
270	#define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */	270	#define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
271	#define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */	271	#define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
272		272
273	/* MD_CA bit asign --------------------------------------------------------- */	273	/* MD_CA bit assign --------------------------------------------------------- */
274	#define MD_CA_PreSup 0x00001000 /* 1:Preamble Supress */	274	#define MD_CA_PreSup 0x00001000 /* 1:Preamble Suppress */
275	#define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */	275	#define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
276	#define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */	276	#define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
277		277
@@ -296,7 +296,7 @@ struct BDesc {
296		296
297	#define FD_ALIGN 16	297	#define FD_ALIGN 16
298		298
299	/* Frame Descripter bit asign ---------------------------------------------- */	299	/* Frame Descripter bit assign ---------------------------------------------- */
300	#define FD_FDLength_MASK 0x0000FFFF /* Length MASK */	300	#define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
301	#define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */	301	#define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
302	#define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */	302	#define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
@@ -309,8 +309,8 @@ struct BDesc {
309	#define FD_Next_EOL 0x00000001 /* FD EOL indicator */	309	#define FD_Next_EOL 0x00000001 /* FD EOL indicator */
310	#define FD_BDCnt_SHIFT 16	310	#define FD_BDCnt_SHIFT 16
311		311
312	/* Buffer Descripter bit asign --------------------------------------------- */	312	/* Buffer Descripter bit assign --------------------------------------------- */
313	#define BD_BuffLength_MASK 0x0000FFFF /* Recieve Data Size */	313	#define BD_BuffLength_MASK 0x0000FFFF /* Receive Data Size */
314	#define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */	314	#define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
315	#define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */	315	#define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
316	#define BD_CownsBD 0x80000000 /* BD Controller owner bit */	316	#define BD_CownsBD 0x80000000 /* BD Controller owner bit */
@@ -339,7 +339,7 @@ struct BDesc {
339	#define TX_THRESHOLD 1024	339	#define TX_THRESHOLD 1024
340	/* used threshold with packet max byte for low pci transfer ability.*/	340	/* used threshold with packet max byte for low pci transfer ability.*/
341	#define TX_THRESHOLD_MAX 1536	341	#define TX_THRESHOLD_MAX 1536
342	/* setting threshold max value when overrun error occured this count. */	342	/* setting threshold max value when overrun error occurred this count. */
343	#define TX_THRESHOLD_KEEP_LIMIT 10	343	#define TX_THRESHOLD_KEEP_LIMIT 10
344		344
345	/* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZEFD_PAGE_NUM /	345	/* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZEFD_PAGE_NUM /