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path: root/drivers/net/stmmac/common.h
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Diffstat (limited to 'drivers/net/stmmac/common.h')
-rw-r--r--drivers/net/stmmac/common.h279
1 files changed, 91 insertions, 188 deletions
diff --git a/drivers/net/stmmac/common.h b/drivers/net/stmmac/common.h
index e49e5188e887..2a58172e986a 100644
--- a/drivers/net/stmmac/common.h
+++ b/drivers/net/stmmac/common.h
@@ -23,132 +23,7 @@
23*******************************************************************************/ 23*******************************************************************************/
24 24
25#include "descs.h" 25#include "descs.h"
26#include <linux/io.h> 26#include <linux/netdevice.h>
27
28/* *********************************************
29 DMA CRS Control and Status Register Mapping
30 * *********************************************/
31#define DMA_BUS_MODE 0x00001000 /* Bus Mode */
32#define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */
33#define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */
34#define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */
35#define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
36#define DMA_STATUS 0x00001014 /* Status Register */
37#define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */
38#define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */
39#define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */
40#define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */
41#define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */
42
43/* ********************************
44 DMA Control register defines
45 * ********************************/
46#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
47#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
48
49/* **************************************
50 DMA Interrupt Enable register defines
51 * **************************************/
52/**** NORMAL INTERRUPT ****/
53#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
54#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
55#define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */
56#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
57#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
58
59#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
60 DMA_INTR_ENA_TIE)
61
62/**** ABNORMAL INTERRUPT ****/
63#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
64#define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
65#define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
66#define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
67#define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
68#define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
69#define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
70#define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
71#define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
72#define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
73
74#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
75 DMA_INTR_ENA_UNE)
76
77/* DMA default interrupt mask */
78#define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
79
80/* ****************************
81 * DMA Status register defines
82 * ****************************/
83#define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */
84#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
85#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int. */
86#define DMA_STATUS_GMI 0x08000000
87#define DMA_STATUS_GLI 0x04000000
88#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
89#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
90#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
91#define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
92#define DMA_STATUS_TS_SHIFT 20
93#define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
94#define DMA_STATUS_RS_SHIFT 17
95#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
96#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
97#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
98#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
99#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
100#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
101#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
102#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
103#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
104#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
105#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
106#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
107#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
108#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
109#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
110
111/* Other defines */
112#define HASH_TABLE_SIZE 64
113#define PAUSE_TIME 0x200
114
115/* Flow Control defines */
116#define FLOW_OFF 0
117#define FLOW_RX 1
118#define FLOW_TX 2
119#define FLOW_AUTO (FLOW_TX | FLOW_RX)
120
121/* DMA STORE-AND-FORWARD Operation Mode */
122#define SF_DMA_MODE 1
123
124#define HW_CSUM 1
125#define NO_HW_CSUM 0
126
127/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
128#define BUF_SIZE_16KiB 16384
129#define BUF_SIZE_8KiB 8192
130#define BUF_SIZE_4KiB 4096
131#define BUF_SIZE_2KiB 2048
132
133/* Power Down and WOL */
134#define PMT_NOT_SUPPORTED 0
135#define PMT_SUPPORTED 1
136
137/* Common MAC defines */
138#define MAC_CTRL_REG 0x00000000 /* MAC Control */
139#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
140#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
141
142/* MAC Management Counters register */
143#define MMC_CONTROL 0x00000100 /* MMC Control */
144#define MMC_HIGH_INTR 0x00000104 /* MMC High Interrupt */
145#define MMC_LOW_INTR 0x00000108 /* MMC Low Interrupt */
146#define MMC_HIGH_INTR_MASK 0x0000010c /* MMC High Interrupt Mask */
147#define MMC_LOW_INTR_MASK 0x00000110 /* MMC Low Interrupt Mask */
148
149#define MMC_CONTROL_MAX_FRM_MASK 0x0003ff8 /* Maximum Frame Size */
150#define MMC_CONTROL_MAX_FRM_SHIFT 3
151#define MMC_CONTROL_MAX_FRAME 0x7FF
152 27
153struct stmmac_extra_stats { 28struct stmmac_extra_stats {
154 /* Transmit errors */ 29 /* Transmit errors */
@@ -169,7 +44,7 @@ struct stmmac_extra_stats {
169 unsigned long rx_toolong; 44 unsigned long rx_toolong;
170 unsigned long rx_collision; 45 unsigned long rx_collision;
171 unsigned long rx_crc; 46 unsigned long rx_crc;
172 unsigned long rx_lenght; 47 unsigned long rx_length;
173 unsigned long rx_mii; 48 unsigned long rx_mii;
174 unsigned long rx_multicast; 49 unsigned long rx_multicast;
175 unsigned long rx_gmac_overflow; 50 unsigned long rx_gmac_overflow;
@@ -198,66 +73,62 @@ struct stmmac_extra_stats {
198 unsigned long normal_irq_n; 73 unsigned long normal_irq_n;
199}; 74};
200 75
201/* GMAC core can compute the checksums in HW. */ 76#define HASH_TABLE_SIZE 64
202enum rx_frame_status { 77#define PAUSE_TIME 0x200
78
79/* Flow Control defines */
80#define FLOW_OFF 0
81#define FLOW_RX 1
82#define FLOW_TX 2
83#define FLOW_AUTO (FLOW_TX | FLOW_RX)
84
85#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
86
87#define HW_CSUM 1
88#define NO_HW_CSUM 0
89enum rx_frame_status { /* IPC status */
203 good_frame = 0, 90 good_frame = 0,
204 discard_frame = 1, 91 discard_frame = 1,
205 csum_none = 2, 92 csum_none = 2,
206}; 93};
207 94
208static inline void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6], 95enum tx_dma_irq_status {
209 unsigned int high, unsigned int low) 96 tx_hard_error = 1,
210{ 97 tx_hard_error_bump_tc = 2,
211 unsigned long data; 98 handle_tx_rx = 3,
212 99};
213 data = (addr[5] << 8) | addr[4];
214 writel(data, ioaddr + high);
215 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
216 writel(data, ioaddr + low);
217 100
218 return; 101/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
219} 102#define BUF_SIZE_16KiB 16384
103#define BUF_SIZE_8KiB 8192
104#define BUF_SIZE_4KiB 4096
105#define BUF_SIZE_2KiB 2048
220 106
221static inline void stmmac_get_mac_addr(unsigned long ioaddr, 107/* Power Down and WOL */
222 unsigned char *addr, unsigned int high, 108#define PMT_NOT_SUPPORTED 0
223 unsigned int low) 109#define PMT_SUPPORTED 1
224{
225 unsigned int hi_addr, lo_addr;
226 110
227 /* Read the MAC address from the hardware */ 111/* Common MAC defines */
228 hi_addr = readl(ioaddr + high); 112#define MAC_CTRL_REG 0x00000000 /* MAC Control */
229 lo_addr = readl(ioaddr + low); 113#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
114#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
230 115
231 /* Extract the MAC address from the high and low words */ 116/* MAC Management Counters register */
232 addr[0] = lo_addr & 0xff; 117#define MMC_CONTROL 0x00000100 /* MMC Control */
233 addr[1] = (lo_addr >> 8) & 0xff; 118#define MMC_HIGH_INTR 0x00000104 /* MMC High Interrupt */
234 addr[2] = (lo_addr >> 16) & 0xff; 119#define MMC_LOW_INTR 0x00000108 /* MMC Low Interrupt */
235 addr[3] = (lo_addr >> 24) & 0xff; 120#define MMC_HIGH_INTR_MASK 0x0000010c /* MMC High Interrupt Mask */
236 addr[4] = hi_addr & 0xff; 121#define MMC_LOW_INTR_MASK 0x00000110 /* MMC Low Interrupt Mask */
237 addr[5] = (hi_addr >> 8) & 0xff;
238 122
239 return; 123#define MMC_CONTROL_MAX_FRM_MASK 0x0003ff8 /* Maximum Frame Size */
240} 124#define MMC_CONTROL_MAX_FRM_SHIFT 3
125#define MMC_CONTROL_MAX_FRAME 0x7FF
241 126
242struct stmmac_ops { 127struct stmmac_desc_ops {
243 /* MAC core initialization */ 128 /* DMA RX descriptor ring initialization */
244 void (*core_init) (unsigned long ioaddr) ____cacheline_aligned;
245 /* DMA core initialization */
246 int (*dma_init) (unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
247 /* Dump MAC registers */
248 void (*dump_mac_regs) (unsigned long ioaddr);
249 /* Dump DMA registers */
250 void (*dump_dma_regs) (unsigned long ioaddr);
251 /* Set tx/rx threshold in the csr6 register
252 * An invalid value enables the store-and-forward mode */
253 void (*dma_mode) (unsigned long ioaddr, int txmode, int rxmode);
254 /* To track extra statistic (if supported) */
255 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
256 unsigned long ioaddr);
257 /* RX descriptor ring initialization */
258 void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size, 129 void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
259 int disable_rx_ic); 130 int disable_rx_ic);
260 /* TX descriptor ring initialization */ 131 /* DMA TX descriptor ring initialization */
261 void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size); 132 void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size);
262 133
263 /* Invoked by the xmit function to prepare the tx descriptor */ 134 /* Invoked by the xmit function to prepare the tx descriptor */
@@ -281,7 +152,6 @@ struct stmmac_ops {
281 /* Get the buffer size from the descriptor */ 152 /* Get the buffer size from the descriptor */
282 int (*get_tx_len) (struct dma_desc *p); 153 int (*get_tx_len) (struct dma_desc *p);
283 /* Handle extra events on specific interrupts hw dependent */ 154 /* Handle extra events on specific interrupts hw dependent */
284 void (*host_irq_status) (unsigned long ioaddr);
285 int (*get_rx_owner) (struct dma_desc *p); 155 int (*get_rx_owner) (struct dma_desc *p);
286 void (*set_rx_owner) (struct dma_desc *p); 156 void (*set_rx_owner) (struct dma_desc *p);
287 /* Get the receive frame size */ 157 /* Get the receive frame size */
@@ -289,6 +159,37 @@ struct stmmac_ops {
289 /* Return the reception status looking at the RDES1 */ 159 /* Return the reception status looking at the RDES1 */
290 int (*rx_status) (void *data, struct stmmac_extra_stats *x, 160 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
291 struct dma_desc *p); 161 struct dma_desc *p);
162};
163
164struct stmmac_dma_ops {
165 /* DMA core initialization */
166 int (*init) (unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
167 /* Dump DMA registers */
168 void (*dump_regs) (unsigned long ioaddr);
169 /* Set tx/rx threshold in the csr6 register
170 * An invalid value enables the store-and-forward mode */
171 void (*dma_mode) (unsigned long ioaddr, int txmode, int rxmode);
172 /* To track extra statistic (if supported) */
173 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
174 unsigned long ioaddr);
175 void (*enable_dma_transmission) (unsigned long ioaddr);
176 void (*enable_dma_irq) (unsigned long ioaddr);
177 void (*disable_dma_irq) (unsigned long ioaddr);
178 void (*start_tx) (unsigned long ioaddr);
179 void (*stop_tx) (unsigned long ioaddr);
180 void (*start_rx) (unsigned long ioaddr);
181 void (*stop_rx) (unsigned long ioaddr);
182 int (*dma_interrupt) (unsigned long ioaddr,
183 struct stmmac_extra_stats *x);
184};
185
186struct stmmac_ops {
187 /* MAC core initialization */
188 void (*core_init) (unsigned long ioaddr) ____cacheline_aligned;
189 /* Dump MAC registers */
190 void (*dump_regs) (unsigned long ioaddr);
191 /* Handle extra events on specific interrupts hw dependent */
192 void (*host_irq_status) (unsigned long ioaddr);
292 /* Multicast filter setting */ 193 /* Multicast filter setting */
293 void (*set_filter) (struct net_device *dev); 194 void (*set_filter) (struct net_device *dev);
294 /* Flow control setting */ 195 /* Flow control setting */
@@ -298,9 +199,9 @@ struct stmmac_ops {
298 void (*pmt) (unsigned long ioaddr, unsigned long mode); 199 void (*pmt) (unsigned long ioaddr, unsigned long mode);
299 /* Set/Get Unicast MAC addresses */ 200 /* Set/Get Unicast MAC addresses */
300 void (*set_umac_addr) (unsigned long ioaddr, unsigned char *addr, 201 void (*set_umac_addr) (unsigned long ioaddr, unsigned char *addr,
301 unsigned int reg_n); 202 unsigned int reg_n);
302 void (*get_umac_addr) (unsigned long ioaddr, unsigned char *addr, 203 void (*get_umac_addr) (unsigned long ioaddr, unsigned char *addr,
303 unsigned int reg_n); 204 unsigned int reg_n);
304}; 205};
305 206
306struct mac_link { 207struct mac_link {
@@ -314,17 +215,19 @@ struct mii_regs {
314 unsigned int data; /* MII Data */ 215 unsigned int data; /* MII Data */
315}; 216};
316 217
317struct hw_cap { 218struct mac_device_info {
318 unsigned int version; /* Core Version register (GMAC) */ 219 struct stmmac_ops *mac;
319 unsigned int pmt; /* Power-Down mode (GMAC) */ 220 struct stmmac_desc_ops *desc;
221 struct stmmac_dma_ops *dma;
222 unsigned int pmt; /* support Power-Down */
223 struct mii_regs mii; /* MII register Addresses */
320 struct mac_link link; 224 struct mac_link link;
321 struct mii_regs mii;
322}; 225};
323 226
324struct mac_device_info { 227struct mac_device_info *dwmac1000_setup(unsigned long addr);
325 struct hw_cap hw; 228struct mac_device_info *dwmac100_setup(unsigned long addr);
326 struct stmmac_ops *ops;
327};
328 229
329struct mac_device_info *gmac_setup(unsigned long addr); 230extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
330struct mac_device_info *mac100_setup(unsigned long addr); 231 unsigned int high, unsigned int low);
232extern void stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr,
233 unsigned int high, unsigned int low);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-10 16:20:16 -0400