diff options
Diffstat (limited to 'drivers/net/smsc9420.c')
-rw-r--r-- | drivers/net/smsc9420.c | 1744 |
1 files changed, 1744 insertions, 0 deletions
diff --git a/drivers/net/smsc9420.c b/drivers/net/smsc9420.c new file mode 100644 index 000000000000..27e017d96966 --- /dev/null +++ b/drivers/net/smsc9420.c | |||
@@ -0,0 +1,1744 @@ | |||
1 | /*************************************************************************** | ||
2 | * | ||
3 | * Copyright (C) 2007,2008 SMSC | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * as published by the Free Software Foundation; either version 2 | ||
8 | * of the License, or (at your option) any later version. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
18 | * | ||
19 | *************************************************************************** | ||
20 | */ | ||
21 | |||
22 | #include <linux/kernel.h> | ||
23 | #include <linux/netdevice.h> | ||
24 | #include <linux/phy.h> | ||
25 | #include <linux/pci.h> | ||
26 | #include <linux/if_vlan.h> | ||
27 | #include <linux/dma-mapping.h> | ||
28 | #include <linux/crc32.h> | ||
29 | #include <asm/unaligned.h> | ||
30 | #include "smsc9420.h" | ||
31 | |||
32 | #define DRV_NAME "smsc9420" | ||
33 | #define PFX DRV_NAME ": " | ||
34 | #define DRV_MDIONAME "smsc9420-mdio" | ||
35 | #define DRV_DESCRIPTION "SMSC LAN9420 driver" | ||
36 | #define DRV_VERSION "1.01" | ||
37 | |||
38 | MODULE_LICENSE("GPL"); | ||
39 | MODULE_VERSION(DRV_VERSION); | ||
40 | |||
41 | struct smsc9420_dma_desc { | ||
42 | u32 status; | ||
43 | u32 length; | ||
44 | u32 buffer1; | ||
45 | u32 buffer2; | ||
46 | }; | ||
47 | |||
48 | struct smsc9420_ring_info { | ||
49 | struct sk_buff *skb; | ||
50 | dma_addr_t mapping; | ||
51 | }; | ||
52 | |||
53 | struct smsc9420_pdata { | ||
54 | void __iomem *base_addr; | ||
55 | struct pci_dev *pdev; | ||
56 | struct net_device *dev; | ||
57 | |||
58 | struct smsc9420_dma_desc *rx_ring; | ||
59 | struct smsc9420_dma_desc *tx_ring; | ||
60 | struct smsc9420_ring_info *tx_buffers; | ||
61 | struct smsc9420_ring_info *rx_buffers; | ||
62 | dma_addr_t rx_dma_addr; | ||
63 | dma_addr_t tx_dma_addr; | ||
64 | int tx_ring_head, tx_ring_tail; | ||
65 | int rx_ring_head, rx_ring_tail; | ||
66 | |||
67 | spinlock_t int_lock; | ||
68 | spinlock_t phy_lock; | ||
69 | |||
70 | struct napi_struct napi; | ||
71 | |||
72 | bool software_irq_signal; | ||
73 | bool rx_csum; | ||
74 | u32 msg_enable; | ||
75 | |||
76 | struct phy_device *phy_dev; | ||
77 | struct mii_bus *mii_bus; | ||
78 | int phy_irq[PHY_MAX_ADDR]; | ||
79 | int last_duplex; | ||
80 | int last_carrier; | ||
81 | }; | ||
82 | |||
83 | static const struct pci_device_id smsc9420_id_table[] = { | ||
84 | { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, }, | ||
85 | { 0, } | ||
86 | }; | ||
87 | |||
88 | MODULE_DEVICE_TABLE(pci, smsc9420_id_table); | ||
89 | |||
90 | #define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) | ||
91 | |||
92 | static uint smsc_debug; | ||
93 | static uint debug = -1; | ||
94 | module_param(debug, uint, 0); | ||
95 | MODULE_PARM_DESC(debug, "debug level"); | ||
96 | |||
97 | #define smsc_dbg(TYPE, f, a...) \ | ||
98 | do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \ | ||
99 | printk(KERN_DEBUG PFX f "\n", ## a); \ | ||
100 | } while (0) | ||
101 | |||
102 | #define smsc_info(TYPE, f, a...) \ | ||
103 | do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \ | ||
104 | printk(KERN_INFO PFX f "\n", ## a); \ | ||
105 | } while (0) | ||
106 | |||
107 | #define smsc_warn(TYPE, f, a...) \ | ||
108 | do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \ | ||
109 | printk(KERN_WARNING PFX f "\n", ## a); \ | ||
110 | } while (0) | ||
111 | |||
112 | static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset) | ||
113 | { | ||
114 | return ioread32(pd->base_addr + offset); | ||
115 | } | ||
116 | |||
117 | static inline void | ||
118 | smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value) | ||
119 | { | ||
120 | iowrite32(value, pd->base_addr + offset); | ||
121 | } | ||
122 | |||
123 | static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd) | ||
124 | { | ||
125 | /* to ensure PCI write completion, we must perform a PCI read */ | ||
126 | smsc9420_reg_read(pd, ID_REV); | ||
127 | } | ||
128 | |||
129 | static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx) | ||
130 | { | ||
131 | struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv; | ||
132 | unsigned long flags; | ||
133 | u32 addr; | ||
134 | int i, reg = -EIO; | ||
135 | |||
136 | spin_lock_irqsave(&pd->phy_lock, flags); | ||
137 | |||
138 | /* confirm MII not busy */ | ||
139 | if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) { | ||
140 | smsc_warn(DRV, "MII is busy???"); | ||
141 | goto out; | ||
142 | } | ||
143 | |||
144 | /* set the address, index & direction (read from PHY) */ | ||
145 | addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | | ||
146 | MII_ACCESS_MII_READ_; | ||
147 | smsc9420_reg_write(pd, MII_ACCESS, addr); | ||
148 | |||
149 | /* wait for read to complete with 50us timeout */ | ||
150 | for (i = 0; i < 5; i++) { | ||
151 | if (!(smsc9420_reg_read(pd, MII_ACCESS) & | ||
152 | MII_ACCESS_MII_BUSY_)) { | ||
153 | reg = (u16)smsc9420_reg_read(pd, MII_DATA); | ||
154 | goto out; | ||
155 | } | ||
156 | udelay(10); | ||
157 | } | ||
158 | |||
159 | smsc_warn(DRV, "MII busy timeout!"); | ||
160 | |||
161 | out: | ||
162 | spin_unlock_irqrestore(&pd->phy_lock, flags); | ||
163 | return reg; | ||
164 | } | ||
165 | |||
166 | static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx, | ||
167 | u16 val) | ||
168 | { | ||
169 | struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv; | ||
170 | unsigned long flags; | ||
171 | u32 addr; | ||
172 | int i, reg = -EIO; | ||
173 | |||
174 | spin_lock_irqsave(&pd->phy_lock, flags); | ||
175 | |||
176 | /* confirm MII not busy */ | ||
177 | if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) { | ||
178 | smsc_warn(DRV, "MII is busy???"); | ||
179 | goto out; | ||
180 | } | ||
181 | |||
182 | /* put the data to write in the MAC */ | ||
183 | smsc9420_reg_write(pd, MII_DATA, (u32)val); | ||
184 | |||
185 | /* set the address, index & direction (write to PHY) */ | ||
186 | addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | | ||
187 | MII_ACCESS_MII_WRITE_; | ||
188 | smsc9420_reg_write(pd, MII_ACCESS, addr); | ||
189 | |||
190 | /* wait for write to complete with 50us timeout */ | ||
191 | for (i = 0; i < 5; i++) { | ||
192 | if (!(smsc9420_reg_read(pd, MII_ACCESS) & | ||
193 | MII_ACCESS_MII_BUSY_)) { | ||
194 | reg = 0; | ||
195 | goto out; | ||
196 | } | ||
197 | udelay(10); | ||
198 | } | ||
199 | |||
200 | smsc_warn(DRV, "MII busy timeout!"); | ||
201 | |||
202 | out: | ||
203 | spin_unlock_irqrestore(&pd->phy_lock, flags); | ||
204 | return reg; | ||
205 | } | ||
206 | |||
207 | /* Returns hash bit number for given MAC address | ||
208 | * Example: | ||
209 | * 01 00 5E 00 00 01 -> returns bit number 31 */ | ||
210 | static u32 smsc9420_hash(u8 addr[ETH_ALEN]) | ||
211 | { | ||
212 | return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f; | ||
213 | } | ||
214 | |||
215 | static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd) | ||
216 | { | ||
217 | int timeout = 100000; | ||
218 | |||
219 | BUG_ON(!pd); | ||
220 | |||
221 | if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) { | ||
222 | smsc_dbg(DRV, "smsc9420_eeprom_reload: Eeprom busy"); | ||
223 | return -EIO; | ||
224 | } | ||
225 | |||
226 | smsc9420_reg_write(pd, E2P_CMD, | ||
227 | (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_)); | ||
228 | |||
229 | do { | ||
230 | udelay(10); | ||
231 | if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_)) | ||
232 | return 0; | ||
233 | } while (timeout--); | ||
234 | |||
235 | smsc_warn(DRV, "smsc9420_eeprom_reload: Eeprom timed out"); | ||
236 | return -EIO; | ||
237 | } | ||
238 | |||
239 | /* Standard ioctls for mii-tool */ | ||
240 | static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | ||
241 | { | ||
242 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
243 | |||
244 | if (!netif_running(dev) || !pd->phy_dev) | ||
245 | return -EINVAL; | ||
246 | |||
247 | return phy_mii_ioctl(pd->phy_dev, if_mii(ifr), cmd); | ||
248 | } | ||
249 | |||
250 | static int smsc9420_ethtool_get_settings(struct net_device *dev, | ||
251 | struct ethtool_cmd *cmd) | ||
252 | { | ||
253 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
254 | |||
255 | cmd->maxtxpkt = 1; | ||
256 | cmd->maxrxpkt = 1; | ||
257 | return phy_ethtool_gset(pd->phy_dev, cmd); | ||
258 | } | ||
259 | |||
260 | static int smsc9420_ethtool_set_settings(struct net_device *dev, | ||
261 | struct ethtool_cmd *cmd) | ||
262 | { | ||
263 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
264 | |||
265 | return phy_ethtool_sset(pd->phy_dev, cmd); | ||
266 | } | ||
267 | |||
268 | static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev, | ||
269 | struct ethtool_drvinfo *drvinfo) | ||
270 | { | ||
271 | struct smsc9420_pdata *pd = netdev_priv(netdev); | ||
272 | |||
273 | strcpy(drvinfo->driver, DRV_NAME); | ||
274 | strcpy(drvinfo->bus_info, pci_name(pd->pdev)); | ||
275 | strcpy(drvinfo->version, DRV_VERSION); | ||
276 | } | ||
277 | |||
278 | static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev) | ||
279 | { | ||
280 | struct smsc9420_pdata *pd = netdev_priv(netdev); | ||
281 | return pd->msg_enable; | ||
282 | } | ||
283 | |||
284 | static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data) | ||
285 | { | ||
286 | struct smsc9420_pdata *pd = netdev_priv(netdev); | ||
287 | pd->msg_enable = data; | ||
288 | } | ||
289 | |||
290 | static int smsc9420_ethtool_nway_reset(struct net_device *netdev) | ||
291 | { | ||
292 | struct smsc9420_pdata *pd = netdev_priv(netdev); | ||
293 | return phy_start_aneg(pd->phy_dev); | ||
294 | } | ||
295 | |||
296 | static int smsc9420_ethtool_getregslen(struct net_device *dev) | ||
297 | { | ||
298 | /* all smsc9420 registers plus all phy registers */ | ||
299 | return 0x100 + (32 * sizeof(u32)); | ||
300 | } | ||
301 | |||
302 | static void | ||
303 | smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs, | ||
304 | void *buf) | ||
305 | { | ||
306 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
307 | struct phy_device *phy_dev = pd->phy_dev; | ||
308 | unsigned int i, j = 0; | ||
309 | u32 *data = buf; | ||
310 | |||
311 | regs->version = smsc9420_reg_read(pd, ID_REV); | ||
312 | for (i = 0; i < 0x100; i += (sizeof(u32))) | ||
313 | data[j++] = smsc9420_reg_read(pd, i); | ||
314 | |||
315 | for (i = 0; i <= 31; i++) | ||
316 | data[j++] = smsc9420_mii_read(phy_dev->bus, phy_dev->addr, i); | ||
317 | } | ||
318 | |||
319 | static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd) | ||
320 | { | ||
321 | unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG); | ||
322 | temp &= ~GPIO_CFG_EEPR_EN_; | ||
323 | smsc9420_reg_write(pd, GPIO_CFG, temp); | ||
324 | msleep(1); | ||
325 | } | ||
326 | |||
327 | static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op) | ||
328 | { | ||
329 | int timeout = 100; | ||
330 | u32 e2cmd; | ||
331 | |||
332 | smsc_dbg(HW, "op 0x%08x", op); | ||
333 | if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) { | ||
334 | smsc_warn(HW, "Busy at start"); | ||
335 | return -EBUSY; | ||
336 | } | ||
337 | |||
338 | e2cmd = op | E2P_CMD_EPC_BUSY_; | ||
339 | smsc9420_reg_write(pd, E2P_CMD, e2cmd); | ||
340 | |||
341 | do { | ||
342 | msleep(1); | ||
343 | e2cmd = smsc9420_reg_read(pd, E2P_CMD); | ||
344 | } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (timeout--)); | ||
345 | |||
346 | if (!timeout) { | ||
347 | smsc_info(HW, "TIMED OUT"); | ||
348 | return -EAGAIN; | ||
349 | } | ||
350 | |||
351 | if (e2cmd & E2P_CMD_EPC_TIMEOUT_) { | ||
352 | smsc_info(HW, "Error occured during eeprom operation"); | ||
353 | return -EINVAL; | ||
354 | } | ||
355 | |||
356 | return 0; | ||
357 | } | ||
358 | |||
359 | static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd, | ||
360 | u8 address, u8 *data) | ||
361 | { | ||
362 | u32 op = E2P_CMD_EPC_CMD_READ_ | address; | ||
363 | int ret; | ||
364 | |||
365 | smsc_dbg(HW, "address 0x%x", address); | ||
366 | ret = smsc9420_eeprom_send_cmd(pd, op); | ||
367 | |||
368 | if (!ret) | ||
369 | data[address] = smsc9420_reg_read(pd, E2P_DATA); | ||
370 | |||
371 | return ret; | ||
372 | } | ||
373 | |||
374 | static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd, | ||
375 | u8 address, u8 data) | ||
376 | { | ||
377 | u32 op = E2P_CMD_EPC_CMD_ERASE_ | address; | ||
378 | int ret; | ||
379 | |||
380 | smsc_dbg(HW, "address 0x%x, data 0x%x", address, data); | ||
381 | ret = smsc9420_eeprom_send_cmd(pd, op); | ||
382 | |||
383 | if (!ret) { | ||
384 | op = E2P_CMD_EPC_CMD_WRITE_ | address; | ||
385 | smsc9420_reg_write(pd, E2P_DATA, (u32)data); | ||
386 | ret = smsc9420_eeprom_send_cmd(pd, op); | ||
387 | } | ||
388 | |||
389 | return ret; | ||
390 | } | ||
391 | |||
392 | static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev) | ||
393 | { | ||
394 | return SMSC9420_EEPROM_SIZE; | ||
395 | } | ||
396 | |||
397 | static int smsc9420_ethtool_get_eeprom(struct net_device *dev, | ||
398 | struct ethtool_eeprom *eeprom, u8 *data) | ||
399 | { | ||
400 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
401 | u8 eeprom_data[SMSC9420_EEPROM_SIZE]; | ||
402 | int len, i; | ||
403 | |||
404 | smsc9420_eeprom_enable_access(pd); | ||
405 | |||
406 | len = min(eeprom->len, SMSC9420_EEPROM_SIZE); | ||
407 | for (i = 0; i < len; i++) { | ||
408 | int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data); | ||
409 | if (ret < 0) { | ||
410 | eeprom->len = 0; | ||
411 | return ret; | ||
412 | } | ||
413 | } | ||
414 | |||
415 | memcpy(data, &eeprom_data[eeprom->offset], len); | ||
416 | eeprom->len = len; | ||
417 | return 0; | ||
418 | } | ||
419 | |||
420 | static int smsc9420_ethtool_set_eeprom(struct net_device *dev, | ||
421 | struct ethtool_eeprom *eeprom, u8 *data) | ||
422 | { | ||
423 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
424 | int ret; | ||
425 | |||
426 | smsc9420_eeprom_enable_access(pd); | ||
427 | smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_); | ||
428 | ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data); | ||
429 | smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_); | ||
430 | |||
431 | /* Single byte write, according to man page */ | ||
432 | eeprom->len = 1; | ||
433 | |||
434 | return ret; | ||
435 | } | ||
436 | |||
437 | static const struct ethtool_ops smsc9420_ethtool_ops = { | ||
438 | .get_settings = smsc9420_ethtool_get_settings, | ||
439 | .set_settings = smsc9420_ethtool_set_settings, | ||
440 | .get_drvinfo = smsc9420_ethtool_get_drvinfo, | ||
441 | .get_msglevel = smsc9420_ethtool_get_msglevel, | ||
442 | .set_msglevel = smsc9420_ethtool_set_msglevel, | ||
443 | .nway_reset = smsc9420_ethtool_nway_reset, | ||
444 | .get_link = ethtool_op_get_link, | ||
445 | .get_eeprom_len = smsc9420_ethtool_get_eeprom_len, | ||
446 | .get_eeprom = smsc9420_ethtool_get_eeprom, | ||
447 | .set_eeprom = smsc9420_ethtool_set_eeprom, | ||
448 | .get_regs_len = smsc9420_ethtool_getregslen, | ||
449 | .get_regs = smsc9420_ethtool_getregs, | ||
450 | }; | ||
451 | |||
452 | /* Sets the device MAC address to dev_addr */ | ||
453 | static void smsc9420_set_mac_address(struct net_device *dev) | ||
454 | { | ||
455 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
456 | u8 *dev_addr = dev->dev_addr; | ||
457 | u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4]; | ||
458 | u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | | ||
459 | (dev_addr[1] << 8) | dev_addr[0]; | ||
460 | |||
461 | smsc9420_reg_write(pd, ADDRH, mac_high16); | ||
462 | smsc9420_reg_write(pd, ADDRL, mac_low32); | ||
463 | } | ||
464 | |||
465 | static void smsc9420_check_mac_address(struct net_device *dev) | ||
466 | { | ||
467 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
468 | |||
469 | /* Check if mac address has been specified when bringing interface up */ | ||
470 | if (is_valid_ether_addr(dev->dev_addr)) { | ||
471 | smsc9420_set_mac_address(dev); | ||
472 | smsc_dbg(PROBE, "MAC Address is specified by configuration"); | ||
473 | } else { | ||
474 | /* Try reading mac address from device. if EEPROM is present | ||
475 | * it will already have been set */ | ||
476 | u32 mac_high16 = smsc9420_reg_read(pd, ADDRH); | ||
477 | u32 mac_low32 = smsc9420_reg_read(pd, ADDRL); | ||
478 | dev->dev_addr[0] = (u8)(mac_low32); | ||
479 | dev->dev_addr[1] = (u8)(mac_low32 >> 8); | ||
480 | dev->dev_addr[2] = (u8)(mac_low32 >> 16); | ||
481 | dev->dev_addr[3] = (u8)(mac_low32 >> 24); | ||
482 | dev->dev_addr[4] = (u8)(mac_high16); | ||
483 | dev->dev_addr[5] = (u8)(mac_high16 >> 8); | ||
484 | |||
485 | if (is_valid_ether_addr(dev->dev_addr)) { | ||
486 | /* eeprom values are valid so use them */ | ||
487 | smsc_dbg(PROBE, "Mac Address is read from EEPROM"); | ||
488 | } else { | ||
489 | /* eeprom values are invalid, generate random MAC */ | ||
490 | random_ether_addr(dev->dev_addr); | ||
491 | smsc9420_set_mac_address(dev); | ||
492 | smsc_dbg(PROBE, | ||
493 | "MAC Address is set to random_ether_addr"); | ||
494 | } | ||
495 | } | ||
496 | } | ||
497 | |||
498 | static void smsc9420_stop_tx(struct smsc9420_pdata *pd) | ||
499 | { | ||
500 | u32 dmac_control, mac_cr, dma_intr_ena; | ||
501 | int timeOut = 1000; | ||
502 | |||
503 | /* disable TX DMAC */ | ||
504 | dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); | ||
505 | dmac_control &= (~DMAC_CONTROL_ST_); | ||
506 | smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); | ||
507 | |||
508 | /* Wait max 10ms for transmit process to stop */ | ||
509 | while (timeOut--) { | ||
510 | if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_) | ||
511 | break; | ||
512 | udelay(10); | ||
513 | } | ||
514 | |||
515 | if (!timeOut) | ||
516 | smsc_warn(IFDOWN, "TX DMAC failed to stop"); | ||
517 | |||
518 | /* ACK Tx DMAC stop bit */ | ||
519 | smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_); | ||
520 | |||
521 | /* mask TX DMAC interrupts */ | ||
522 | dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); | ||
523 | dma_intr_ena &= ~(DMAC_INTR_ENA_TX_); | ||
524 | smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); | ||
525 | smsc9420_pci_flush_write(pd); | ||
526 | |||
527 | /* stop MAC TX */ | ||
528 | mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_); | ||
529 | smsc9420_reg_write(pd, MAC_CR, mac_cr); | ||
530 | smsc9420_pci_flush_write(pd); | ||
531 | } | ||
532 | |||
533 | static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd) | ||
534 | { | ||
535 | int i; | ||
536 | |||
537 | BUG_ON(!pd->tx_ring); | ||
538 | |||
539 | if (!pd->tx_buffers) | ||
540 | return; | ||
541 | |||
542 | for (i = 0; i < TX_RING_SIZE; i++) { | ||
543 | struct sk_buff *skb = pd->tx_buffers[i].skb; | ||
544 | |||
545 | if (skb) { | ||
546 | BUG_ON(!pd->tx_buffers[i].mapping); | ||
547 | pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping, | ||
548 | skb->len, PCI_DMA_TODEVICE); | ||
549 | dev_kfree_skb_any(skb); | ||
550 | } | ||
551 | |||
552 | pd->tx_ring[i].status = 0; | ||
553 | pd->tx_ring[i].length = 0; | ||
554 | pd->tx_ring[i].buffer1 = 0; | ||
555 | pd->tx_ring[i].buffer2 = 0; | ||
556 | } | ||
557 | wmb(); | ||
558 | |||
559 | kfree(pd->tx_buffers); | ||
560 | pd->tx_buffers = NULL; | ||
561 | |||
562 | pd->tx_ring_head = 0; | ||
563 | pd->tx_ring_tail = 0; | ||
564 | } | ||
565 | |||
566 | static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd) | ||
567 | { | ||
568 | int i; | ||
569 | |||
570 | BUG_ON(!pd->rx_ring); | ||
571 | |||
572 | if (!pd->rx_buffers) | ||
573 | return; | ||
574 | |||
575 | for (i = 0; i < RX_RING_SIZE; i++) { | ||
576 | if (pd->rx_buffers[i].skb) | ||
577 | dev_kfree_skb_any(pd->rx_buffers[i].skb); | ||
578 | |||
579 | if (pd->rx_buffers[i].mapping) | ||
580 | pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping, | ||
581 | PKT_BUF_SZ, PCI_DMA_FROMDEVICE); | ||
582 | |||
583 | pd->rx_ring[i].status = 0; | ||
584 | pd->rx_ring[i].length = 0; | ||
585 | pd->rx_ring[i].buffer1 = 0; | ||
586 | pd->rx_ring[i].buffer2 = 0; | ||
587 | } | ||
588 | wmb(); | ||
589 | |||
590 | kfree(pd->rx_buffers); | ||
591 | pd->rx_buffers = NULL; | ||
592 | |||
593 | pd->rx_ring_head = 0; | ||
594 | pd->rx_ring_tail = 0; | ||
595 | } | ||
596 | |||
597 | static void smsc9420_stop_rx(struct smsc9420_pdata *pd) | ||
598 | { | ||
599 | int timeOut = 1000; | ||
600 | u32 mac_cr, dmac_control, dma_intr_ena; | ||
601 | |||
602 | /* mask RX DMAC interrupts */ | ||
603 | dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); | ||
604 | dma_intr_ena &= (~DMAC_INTR_ENA_RX_); | ||
605 | smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); | ||
606 | smsc9420_pci_flush_write(pd); | ||
607 | |||
608 | /* stop RX MAC prior to stoping DMA */ | ||
609 | mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_); | ||
610 | smsc9420_reg_write(pd, MAC_CR, mac_cr); | ||
611 | smsc9420_pci_flush_write(pd); | ||
612 | |||
613 | /* stop RX DMAC */ | ||
614 | dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); | ||
615 | dmac_control &= (~DMAC_CONTROL_SR_); | ||
616 | smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); | ||
617 | smsc9420_pci_flush_write(pd); | ||
618 | |||
619 | /* wait up to 10ms for receive to stop */ | ||
620 | while (timeOut--) { | ||
621 | if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_) | ||
622 | break; | ||
623 | udelay(10); | ||
624 | } | ||
625 | |||
626 | if (!timeOut) | ||
627 | smsc_warn(IFDOWN, "RX DMAC did not stop! timeout."); | ||
628 | |||
629 | /* ACK the Rx DMAC stop bit */ | ||
630 | smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_); | ||
631 | } | ||
632 | |||
633 | static irqreturn_t smsc9420_isr(int irq, void *dev_id) | ||
634 | { | ||
635 | struct smsc9420_pdata *pd = dev_id; | ||
636 | u32 int_cfg, int_sts, int_ctl; | ||
637 | irqreturn_t ret = IRQ_NONE; | ||
638 | ulong flags; | ||
639 | |||
640 | BUG_ON(!pd); | ||
641 | BUG_ON(!pd->base_addr); | ||
642 | |||
643 | int_cfg = smsc9420_reg_read(pd, INT_CFG); | ||
644 | |||
645 | /* check if it's our interrupt */ | ||
646 | if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) != | ||
647 | (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) | ||
648 | return IRQ_NONE; | ||
649 | |||
650 | int_sts = smsc9420_reg_read(pd, INT_STAT); | ||
651 | |||
652 | if (likely(INT_STAT_DMAC_INT_ & int_sts)) { | ||
653 | u32 status = smsc9420_reg_read(pd, DMAC_STATUS); | ||
654 | u32 ints_to_clear = 0; | ||
655 | |||
656 | if (status & DMAC_STS_TX_) { | ||
657 | ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_); | ||
658 | netif_wake_queue(pd->dev); | ||
659 | } | ||
660 | |||
661 | if (status & DMAC_STS_RX_) { | ||
662 | /* mask RX DMAC interrupts */ | ||
663 | u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); | ||
664 | dma_intr_ena &= (~DMAC_INTR_ENA_RX_); | ||
665 | smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); | ||
666 | smsc9420_pci_flush_write(pd); | ||
667 | |||
668 | ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_); | ||
669 | netif_rx_schedule(&pd->napi); | ||
670 | } | ||
671 | |||
672 | if (ints_to_clear) | ||
673 | smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear); | ||
674 | |||
675 | ret = IRQ_HANDLED; | ||
676 | } | ||
677 | |||
678 | if (unlikely(INT_STAT_SW_INT_ & int_sts)) { | ||
679 | /* mask software interrupt */ | ||
680 | spin_lock_irqsave(&pd->int_lock, flags); | ||
681 | int_ctl = smsc9420_reg_read(pd, INT_CTL); | ||
682 | int_ctl &= (~INT_CTL_SW_INT_EN_); | ||
683 | smsc9420_reg_write(pd, INT_CTL, int_ctl); | ||
684 | spin_unlock_irqrestore(&pd->int_lock, flags); | ||
685 | |||
686 | smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_); | ||
687 | pd->software_irq_signal = true; | ||
688 | smp_wmb(); | ||
689 | |||
690 | ret = IRQ_HANDLED; | ||
691 | } | ||
692 | |||
693 | /* to ensure PCI write completion, we must perform a PCI read */ | ||
694 | smsc9420_pci_flush_write(pd); | ||
695 | |||
696 | return ret; | ||
697 | } | ||
698 | |||
699 | #ifdef CONFIG_NET_POLL_CONTROLLER | ||
700 | static void smsc9420_poll_controller(struct net_device *dev) | ||
701 | { | ||
702 | disable_irq(dev->irq); | ||
703 | smsc9420_isr(0, dev); | ||
704 | enable_irq(dev->irq); | ||
705 | } | ||
706 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | ||
707 | |||
708 | static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd) | ||
709 | { | ||
710 | smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_); | ||
711 | smsc9420_reg_read(pd, BUS_MODE); | ||
712 | udelay(2); | ||
713 | if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_) | ||
714 | smsc_warn(DRV, "Software reset not cleared"); | ||
715 | } | ||
716 | |||
717 | static int smsc9420_stop(struct net_device *dev) | ||
718 | { | ||
719 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
720 | u32 int_cfg; | ||
721 | ulong flags; | ||
722 | |||
723 | BUG_ON(!pd); | ||
724 | BUG_ON(!pd->phy_dev); | ||
725 | |||
726 | /* disable master interrupt */ | ||
727 | spin_lock_irqsave(&pd->int_lock, flags); | ||
728 | int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); | ||
729 | smsc9420_reg_write(pd, INT_CFG, int_cfg); | ||
730 | spin_unlock_irqrestore(&pd->int_lock, flags); | ||
731 | |||
732 | netif_tx_disable(dev); | ||
733 | napi_disable(&pd->napi); | ||
734 | |||
735 | smsc9420_stop_tx(pd); | ||
736 | smsc9420_free_tx_ring(pd); | ||
737 | |||
738 | smsc9420_stop_rx(pd); | ||
739 | smsc9420_free_rx_ring(pd); | ||
740 | |||
741 | free_irq(dev->irq, pd); | ||
742 | |||
743 | smsc9420_dmac_soft_reset(pd); | ||
744 | |||
745 | phy_stop(pd->phy_dev); | ||
746 | |||
747 | phy_disconnect(pd->phy_dev); | ||
748 | pd->phy_dev = NULL; | ||
749 | mdiobus_unregister(pd->mii_bus); | ||
750 | mdiobus_free(pd->mii_bus); | ||
751 | |||
752 | return 0; | ||
753 | } | ||
754 | |||
755 | static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status) | ||
756 | { | ||
757 | if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) { | ||
758 | dev->stats.rx_errors++; | ||
759 | if (desc_status & RDES0_DESCRIPTOR_ERROR_) | ||
760 | dev->stats.rx_over_errors++; | ||
761 | else if (desc_status & (RDES0_FRAME_TOO_LONG_ | | ||
762 | RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_)) | ||
763 | dev->stats.rx_frame_errors++; | ||
764 | else if (desc_status & RDES0_CRC_ERROR_) | ||
765 | dev->stats.rx_crc_errors++; | ||
766 | } | ||
767 | |||
768 | if (unlikely(desc_status & RDES0_LENGTH_ERROR_)) | ||
769 | dev->stats.rx_length_errors++; | ||
770 | |||
771 | if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) && | ||
772 | (desc_status & RDES0_FIRST_DESCRIPTOR_)))) | ||
773 | dev->stats.rx_length_errors++; | ||
774 | |||
775 | if (desc_status & RDES0_MULTICAST_FRAME_) | ||
776 | dev->stats.multicast++; | ||
777 | } | ||
778 | |||
779 | static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index, | ||
780 | const u32 status) | ||
781 | { | ||
782 | struct net_device *dev = pd->dev; | ||
783 | struct sk_buff *skb; | ||
784 | u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_) | ||
785 | >> RDES0_FRAME_LENGTH_SHFT_; | ||
786 | |||
787 | /* remove crc from packet lendth */ | ||
788 | packet_length -= 4; | ||
789 | |||
790 | if (pd->rx_csum) | ||
791 | packet_length -= 2; | ||
792 | |||
793 | dev->stats.rx_packets++; | ||
794 | dev->stats.rx_bytes += packet_length; | ||
795 | |||
796 | pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping, | ||
797 | PKT_BUF_SZ, PCI_DMA_FROMDEVICE); | ||
798 | pd->rx_buffers[index].mapping = 0; | ||
799 | |||
800 | skb = pd->rx_buffers[index].skb; | ||
801 | pd->rx_buffers[index].skb = NULL; | ||
802 | |||
803 | if (pd->rx_csum) { | ||
804 | u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) + | ||
805 | NET_IP_ALIGN + packet_length + 4); | ||
806 | put_unaligned_le16(cpu_to_le16(hw_csum), &skb->csum); | ||
807 | skb->ip_summed = CHECKSUM_COMPLETE; | ||
808 | } | ||
809 | |||
810 | skb_reserve(skb, NET_IP_ALIGN); | ||
811 | skb_put(skb, packet_length); | ||
812 | |||
813 | skb->protocol = eth_type_trans(skb, dev); | ||
814 | |||
815 | netif_receive_skb(skb); | ||
816 | dev->last_rx = jiffies; | ||
817 | } | ||
818 | |||
819 | static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index) | ||
820 | { | ||
821 | struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ); | ||
822 | dma_addr_t mapping; | ||
823 | |||
824 | BUG_ON(pd->rx_buffers[index].skb); | ||
825 | BUG_ON(pd->rx_buffers[index].mapping); | ||
826 | |||
827 | if (unlikely(!skb)) { | ||
828 | smsc_warn(RX_ERR, "Failed to allocate new skb!"); | ||
829 | return -ENOMEM; | ||
830 | } | ||
831 | |||
832 | skb->dev = pd->dev; | ||
833 | |||
834 | mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb), | ||
835 | PKT_BUF_SZ, PCI_DMA_FROMDEVICE); | ||
836 | if (pci_dma_mapping_error(pd->pdev, mapping)) { | ||
837 | dev_kfree_skb_any(skb); | ||
838 | smsc_warn(RX_ERR, "pci_map_single failed!"); | ||
839 | return -ENOMEM; | ||
840 | } | ||
841 | |||
842 | pd->rx_buffers[index].skb = skb; | ||
843 | pd->rx_buffers[index].mapping = mapping; | ||
844 | pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN; | ||
845 | pd->rx_ring[index].status = RDES0_OWN_; | ||
846 | wmb(); | ||
847 | |||
848 | return 0; | ||
849 | } | ||
850 | |||
851 | static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd) | ||
852 | { | ||
853 | while (pd->rx_ring_tail != pd->rx_ring_head) { | ||
854 | if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail)) | ||
855 | break; | ||
856 | |||
857 | pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE; | ||
858 | } | ||
859 | } | ||
860 | |||
861 | static int smsc9420_rx_poll(struct napi_struct *napi, int budget) | ||
862 | { | ||
863 | struct smsc9420_pdata *pd = | ||
864 | container_of(napi, struct smsc9420_pdata, napi); | ||
865 | struct net_device *dev = pd->dev; | ||
866 | u32 drop_frame_cnt, dma_intr_ena, status; | ||
867 | int work_done; | ||
868 | |||
869 | for (work_done = 0; work_done < budget; work_done++) { | ||
870 | rmb(); | ||
871 | status = pd->rx_ring[pd->rx_ring_head].status; | ||
872 | |||
873 | /* stop if DMAC owns this dma descriptor */ | ||
874 | if (status & RDES0_OWN_) | ||
875 | break; | ||
876 | |||
877 | smsc9420_rx_count_stats(dev, status); | ||
878 | smsc9420_rx_handoff(pd, pd->rx_ring_head, status); | ||
879 | pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE; | ||
880 | smsc9420_alloc_new_rx_buffers(pd); | ||
881 | } | ||
882 | |||
883 | drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR); | ||
884 | dev->stats.rx_dropped += | ||
885 | (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF); | ||
886 | |||
887 | /* Kick RXDMA */ | ||
888 | smsc9420_reg_write(pd, RX_POLL_DEMAND, 1); | ||
889 | smsc9420_pci_flush_write(pd); | ||
890 | |||
891 | if (work_done < budget) { | ||
892 | netif_rx_complete(&pd->napi); | ||
893 | |||
894 | /* re-enable RX DMA interrupts */ | ||
895 | dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); | ||
896 | dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_); | ||
897 | smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); | ||
898 | smsc9420_pci_flush_write(pd); | ||
899 | } | ||
900 | return work_done; | ||
901 | } | ||
902 | |||
903 | static void | ||
904 | smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length) | ||
905 | { | ||
906 | if (unlikely(status & TDES0_ERROR_SUMMARY_)) { | ||
907 | dev->stats.tx_errors++; | ||
908 | if (status & (TDES0_EXCESSIVE_DEFERRAL_ | | ||
909 | TDES0_EXCESSIVE_COLLISIONS_)) | ||
910 | dev->stats.tx_aborted_errors++; | ||
911 | |||
912 | if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_)) | ||
913 | dev->stats.tx_carrier_errors++; | ||
914 | } else { | ||
915 | dev->stats.tx_packets++; | ||
916 | dev->stats.tx_bytes += (length & 0x7FF); | ||
917 | } | ||
918 | |||
919 | if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) { | ||
920 | dev->stats.collisions += 16; | ||
921 | } else { | ||
922 | dev->stats.collisions += | ||
923 | (status & TDES0_COLLISION_COUNT_MASK_) >> | ||
924 | TDES0_COLLISION_COUNT_SHFT_; | ||
925 | } | ||
926 | |||
927 | if (unlikely(status & TDES0_HEARTBEAT_FAIL_)) | ||
928 | dev->stats.tx_heartbeat_errors++; | ||
929 | } | ||
930 | |||
931 | /* Check for completed dma transfers, update stats and free skbs */ | ||
932 | static void smsc9420_complete_tx(struct net_device *dev) | ||
933 | { | ||
934 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
935 | |||
936 | while (pd->tx_ring_tail != pd->tx_ring_head) { | ||
937 | int index = pd->tx_ring_tail; | ||
938 | u32 status, length; | ||
939 | |||
940 | rmb(); | ||
941 | status = pd->tx_ring[index].status; | ||
942 | length = pd->tx_ring[index].length; | ||
943 | |||
944 | /* Check if DMA still owns this descriptor */ | ||
945 | if (unlikely(TDES0_OWN_ & status)) | ||
946 | break; | ||
947 | |||
948 | smsc9420_tx_update_stats(dev, status, length); | ||
949 | |||
950 | BUG_ON(!pd->tx_buffers[index].skb); | ||
951 | BUG_ON(!pd->tx_buffers[index].mapping); | ||
952 | |||
953 | pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping, | ||
954 | pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE); | ||
955 | pd->tx_buffers[index].mapping = 0; | ||
956 | |||
957 | dev_kfree_skb_any(pd->tx_buffers[index].skb); | ||
958 | pd->tx_buffers[index].skb = NULL; | ||
959 | |||
960 | pd->tx_ring[index].buffer1 = 0; | ||
961 | wmb(); | ||
962 | |||
963 | pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE; | ||
964 | } | ||
965 | } | ||
966 | |||
967 | static int smsc9420_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) | ||
968 | { | ||
969 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
970 | dma_addr_t mapping; | ||
971 | int index = pd->tx_ring_head; | ||
972 | u32 tmp_desc1; | ||
973 | bool about_to_take_last_desc = | ||
974 | (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail); | ||
975 | |||
976 | smsc9420_complete_tx(dev); | ||
977 | |||
978 | rmb(); | ||
979 | BUG_ON(pd->tx_ring[index].status & TDES0_OWN_); | ||
980 | BUG_ON(pd->tx_buffers[index].skb); | ||
981 | BUG_ON(pd->tx_buffers[index].mapping); | ||
982 | |||
983 | mapping = pci_map_single(pd->pdev, skb->data, | ||
984 | skb->len, PCI_DMA_TODEVICE); | ||
985 | if (pci_dma_mapping_error(pd->pdev, mapping)) { | ||
986 | smsc_warn(TX_ERR, "pci_map_single failed, dropping packet"); | ||
987 | return NETDEV_TX_BUSY; | ||
988 | } | ||
989 | |||
990 | pd->tx_buffers[index].skb = skb; | ||
991 | pd->tx_buffers[index].mapping = mapping; | ||
992 | |||
993 | tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF)); | ||
994 | if (unlikely(about_to_take_last_desc)) { | ||
995 | tmp_desc1 |= TDES1_IC_; | ||
996 | netif_stop_queue(pd->dev); | ||
997 | } | ||
998 | |||
999 | /* check if we are at the last descriptor and need to set EOR */ | ||
1000 | if (unlikely(index == (TX_RING_SIZE - 1))) | ||
1001 | tmp_desc1 |= TDES1_TER_; | ||
1002 | |||
1003 | pd->tx_ring[index].buffer1 = mapping; | ||
1004 | pd->tx_ring[index].length = tmp_desc1; | ||
1005 | wmb(); | ||
1006 | |||
1007 | /* increment head */ | ||
1008 | pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE; | ||
1009 | |||
1010 | /* assign ownership to DMAC */ | ||
1011 | pd->tx_ring[index].status = TDES0_OWN_; | ||
1012 | wmb(); | ||
1013 | |||
1014 | /* kick the DMA */ | ||
1015 | smsc9420_reg_write(pd, TX_POLL_DEMAND, 1); | ||
1016 | smsc9420_pci_flush_write(pd); | ||
1017 | |||
1018 | dev->trans_start = jiffies; | ||
1019 | |||
1020 | return NETDEV_TX_OK; | ||
1021 | } | ||
1022 | |||
1023 | static struct net_device_stats *smsc9420_get_stats(struct net_device *dev) | ||
1024 | { | ||
1025 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
1026 | u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR); | ||
1027 | dev->stats.rx_dropped += | ||
1028 | (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF); | ||
1029 | return &dev->stats; | ||
1030 | } | ||
1031 | |||
1032 | static void smsc9420_set_multicast_list(struct net_device *dev) | ||
1033 | { | ||
1034 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
1035 | u32 mac_cr = smsc9420_reg_read(pd, MAC_CR); | ||
1036 | |||
1037 | if (dev->flags & IFF_PROMISC) { | ||
1038 | smsc_dbg(HW, "Promiscuous Mode Enabled"); | ||
1039 | mac_cr |= MAC_CR_PRMS_; | ||
1040 | mac_cr &= (~MAC_CR_MCPAS_); | ||
1041 | mac_cr &= (~MAC_CR_HPFILT_); | ||
1042 | } else if (dev->flags & IFF_ALLMULTI) { | ||
1043 | smsc_dbg(HW, "Receive all Multicast Enabled"); | ||
1044 | mac_cr &= (~MAC_CR_PRMS_); | ||
1045 | mac_cr |= MAC_CR_MCPAS_; | ||
1046 | mac_cr &= (~MAC_CR_HPFILT_); | ||
1047 | } else if (dev->mc_count > 0) { | ||
1048 | struct dev_mc_list *mc_list = dev->mc_list; | ||
1049 | u32 hash_lo = 0, hash_hi = 0; | ||
1050 | |||
1051 | smsc_dbg(HW, "Multicast filter enabled"); | ||
1052 | while (mc_list) { | ||
1053 | u32 bit_num = smsc9420_hash(mc_list->dmi_addr); | ||
1054 | u32 mask = 1 << (bit_num & 0x1F); | ||
1055 | |||
1056 | if (bit_num & 0x20) | ||
1057 | hash_hi |= mask; | ||
1058 | else | ||
1059 | hash_lo |= mask; | ||
1060 | |||
1061 | mc_list = mc_list->next; | ||
1062 | } | ||
1063 | smsc9420_reg_write(pd, HASHH, hash_hi); | ||
1064 | smsc9420_reg_write(pd, HASHL, hash_lo); | ||
1065 | |||
1066 | mac_cr &= (~MAC_CR_PRMS_); | ||
1067 | mac_cr &= (~MAC_CR_MCPAS_); | ||
1068 | mac_cr |= MAC_CR_HPFILT_; | ||
1069 | } else { | ||
1070 | smsc_dbg(HW, "Receive own packets only."); | ||
1071 | smsc9420_reg_write(pd, HASHH, 0); | ||
1072 | smsc9420_reg_write(pd, HASHL, 0); | ||
1073 | |||
1074 | mac_cr &= (~MAC_CR_PRMS_); | ||
1075 | mac_cr &= (~MAC_CR_MCPAS_); | ||
1076 | mac_cr &= (~MAC_CR_HPFILT_); | ||
1077 | } | ||
1078 | |||
1079 | smsc9420_reg_write(pd, MAC_CR, mac_cr); | ||
1080 | smsc9420_pci_flush_write(pd); | ||
1081 | } | ||
1082 | |||
1083 | static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd) | ||
1084 | { | ||
1085 | struct phy_device *phy_dev = pd->phy_dev; | ||
1086 | u32 flow; | ||
1087 | |||
1088 | if (phy_dev->duplex == DUPLEX_FULL) { | ||
1089 | u16 lcladv = phy_read(phy_dev, MII_ADVERTISE); | ||
1090 | u16 rmtadv = phy_read(phy_dev, MII_LPA); | ||
1091 | u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); | ||
1092 | |||
1093 | if (cap & FLOW_CTRL_RX) | ||
1094 | flow = 0xFFFF0002; | ||
1095 | else | ||
1096 | flow = 0; | ||
1097 | |||
1098 | smsc_info(LINK, "rx pause %s, tx pause %s", | ||
1099 | (cap & FLOW_CTRL_RX ? "enabled" : "disabled"), | ||
1100 | (cap & FLOW_CTRL_TX ? "enabled" : "disabled")); | ||
1101 | } else { | ||
1102 | smsc_info(LINK, "half duplex"); | ||
1103 | flow = 0; | ||
1104 | } | ||
1105 | |||
1106 | smsc9420_reg_write(pd, FLOW, flow); | ||
1107 | } | ||
1108 | |||
1109 | /* Update link mode if anything has changed. Called periodically when the | ||
1110 | * PHY is in polling mode, even if nothing has changed. */ | ||
1111 | static void smsc9420_phy_adjust_link(struct net_device *dev) | ||
1112 | { | ||
1113 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
1114 | struct phy_device *phy_dev = pd->phy_dev; | ||
1115 | int carrier; | ||
1116 | |||
1117 | if (phy_dev->duplex != pd->last_duplex) { | ||
1118 | u32 mac_cr = smsc9420_reg_read(pd, MAC_CR); | ||
1119 | if (phy_dev->duplex) { | ||
1120 | smsc_dbg(LINK, "full duplex mode"); | ||
1121 | mac_cr |= MAC_CR_FDPX_; | ||
1122 | } else { | ||
1123 | smsc_dbg(LINK, "half duplex mode"); | ||
1124 | mac_cr &= ~MAC_CR_FDPX_; | ||
1125 | } | ||
1126 | smsc9420_reg_write(pd, MAC_CR, mac_cr); | ||
1127 | |||
1128 | smsc9420_phy_update_flowcontrol(pd); | ||
1129 | pd->last_duplex = phy_dev->duplex; | ||
1130 | } | ||
1131 | |||
1132 | carrier = netif_carrier_ok(dev); | ||
1133 | if (carrier != pd->last_carrier) { | ||
1134 | if (carrier) | ||
1135 | smsc_dbg(LINK, "carrier OK"); | ||
1136 | else | ||
1137 | smsc_dbg(LINK, "no carrier"); | ||
1138 | pd->last_carrier = carrier; | ||
1139 | } | ||
1140 | } | ||
1141 | |||
1142 | static int smsc9420_mii_probe(struct net_device *dev) | ||
1143 | { | ||
1144 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
1145 | struct phy_device *phydev = NULL; | ||
1146 | |||
1147 | BUG_ON(pd->phy_dev); | ||
1148 | |||
1149 | /* Device only supports internal PHY at address 1 */ | ||
1150 | if (!pd->mii_bus->phy_map[1]) { | ||
1151 | pr_err("%s: no PHY found at address 1\n", dev->name); | ||
1152 | return -ENODEV; | ||
1153 | } | ||
1154 | |||
1155 | phydev = pd->mii_bus->phy_map[1]; | ||
1156 | smsc_info(PROBE, "PHY addr %d, phy_id 0x%08X", phydev->addr, | ||
1157 | phydev->phy_id); | ||
1158 | |||
1159 | phydev = phy_connect(dev, phydev->dev.bus_id, | ||
1160 | &smsc9420_phy_adjust_link, 0, PHY_INTERFACE_MODE_MII); | ||
1161 | |||
1162 | if (IS_ERR(phydev)) { | ||
1163 | pr_err("%s: Could not attach to PHY\n", dev->name); | ||
1164 | return PTR_ERR(phydev); | ||
1165 | } | ||
1166 | |||
1167 | pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", | ||
1168 | dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq); | ||
1169 | |||
1170 | /* mask with MAC supported features */ | ||
1171 | phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause | | ||
1172 | SUPPORTED_Asym_Pause); | ||
1173 | phydev->advertising = phydev->supported; | ||
1174 | |||
1175 | pd->phy_dev = phydev; | ||
1176 | pd->last_duplex = -1; | ||
1177 | pd->last_carrier = -1; | ||
1178 | |||
1179 | return 0; | ||
1180 | } | ||
1181 | |||
1182 | static int smsc9420_mii_init(struct net_device *dev) | ||
1183 | { | ||
1184 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
1185 | int err = -ENXIO, i; | ||
1186 | |||
1187 | pd->mii_bus = mdiobus_alloc(); | ||
1188 | if (!pd->mii_bus) { | ||
1189 | err = -ENOMEM; | ||
1190 | goto err_out_1; | ||
1191 | } | ||
1192 | pd->mii_bus->name = DRV_MDIONAME; | ||
1193 | snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x", | ||
1194 | (pd->pdev->bus->number << 8) | pd->pdev->devfn); | ||
1195 | pd->mii_bus->priv = pd; | ||
1196 | pd->mii_bus->read = smsc9420_mii_read; | ||
1197 | pd->mii_bus->write = smsc9420_mii_write; | ||
1198 | pd->mii_bus->irq = pd->phy_irq; | ||
1199 | for (i = 0; i < PHY_MAX_ADDR; ++i) | ||
1200 | pd->mii_bus->irq[i] = PHY_POLL; | ||
1201 | |||
1202 | /* Mask all PHYs except ID 1 (internal) */ | ||
1203 | pd->mii_bus->phy_mask = ~(1 << 1); | ||
1204 | |||
1205 | if (mdiobus_register(pd->mii_bus)) { | ||
1206 | smsc_warn(PROBE, "Error registering mii bus"); | ||
1207 | goto err_out_free_bus_2; | ||
1208 | } | ||
1209 | |||
1210 | if (smsc9420_mii_probe(dev) < 0) { | ||
1211 | smsc_warn(PROBE, "Error probing mii bus"); | ||
1212 | goto err_out_unregister_bus_3; | ||
1213 | } | ||
1214 | |||
1215 | return 0; | ||
1216 | |||
1217 | err_out_unregister_bus_3: | ||
1218 | mdiobus_unregister(pd->mii_bus); | ||
1219 | err_out_free_bus_2: | ||
1220 | mdiobus_free(pd->mii_bus); | ||
1221 | err_out_1: | ||
1222 | return err; | ||
1223 | } | ||
1224 | |||
1225 | static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd) | ||
1226 | { | ||
1227 | int i; | ||
1228 | |||
1229 | BUG_ON(!pd->tx_ring); | ||
1230 | |||
1231 | pd->tx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) * | ||
1232 | TX_RING_SIZE), GFP_KERNEL); | ||
1233 | if (!pd->tx_buffers) { | ||
1234 | smsc_warn(IFUP, "Failed to allocated tx_buffers"); | ||
1235 | return -ENOMEM; | ||
1236 | } | ||
1237 | |||
1238 | /* Initialize the TX Ring */ | ||
1239 | for (i = 0; i < TX_RING_SIZE; i++) { | ||
1240 | pd->tx_buffers[i].skb = NULL; | ||
1241 | pd->tx_buffers[i].mapping = 0; | ||
1242 | pd->tx_ring[i].status = 0; | ||
1243 | pd->tx_ring[i].length = 0; | ||
1244 | pd->tx_ring[i].buffer1 = 0; | ||
1245 | pd->tx_ring[i].buffer2 = 0; | ||
1246 | } | ||
1247 | pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_; | ||
1248 | wmb(); | ||
1249 | |||
1250 | pd->tx_ring_head = 0; | ||
1251 | pd->tx_ring_tail = 0; | ||
1252 | |||
1253 | smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr); | ||
1254 | smsc9420_pci_flush_write(pd); | ||
1255 | |||
1256 | return 0; | ||
1257 | } | ||
1258 | |||
1259 | static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd) | ||
1260 | { | ||
1261 | int i; | ||
1262 | |||
1263 | BUG_ON(!pd->rx_ring); | ||
1264 | |||
1265 | pd->rx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) * | ||
1266 | RX_RING_SIZE), GFP_KERNEL); | ||
1267 | if (pd->rx_buffers == NULL) { | ||
1268 | smsc_warn(IFUP, "Failed to allocated rx_buffers"); | ||
1269 | goto out; | ||
1270 | } | ||
1271 | |||
1272 | /* initialize the rx ring */ | ||
1273 | for (i = 0; i < RX_RING_SIZE; i++) { | ||
1274 | pd->rx_ring[i].status = 0; | ||
1275 | pd->rx_ring[i].length = PKT_BUF_SZ; | ||
1276 | pd->rx_ring[i].buffer2 = 0; | ||
1277 | pd->rx_buffers[i].skb = NULL; | ||
1278 | pd->rx_buffers[i].mapping = 0; | ||
1279 | } | ||
1280 | pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_); | ||
1281 | |||
1282 | /* now allocate the entire ring of skbs */ | ||
1283 | for (i = 0; i < RX_RING_SIZE; i++) { | ||
1284 | if (smsc9420_alloc_rx_buffer(pd, i)) { | ||
1285 | smsc_warn(IFUP, "failed to allocate rx skb %d", i); | ||
1286 | goto out_free_rx_skbs; | ||
1287 | } | ||
1288 | } | ||
1289 | |||
1290 | pd->rx_ring_head = 0; | ||
1291 | pd->rx_ring_tail = 0; | ||
1292 | |||
1293 | smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q); | ||
1294 | smsc_dbg(IFUP, "VLAN1 = 0x%08x", smsc9420_reg_read(pd, VLAN1)); | ||
1295 | |||
1296 | if (pd->rx_csum) { | ||
1297 | /* Enable RX COE */ | ||
1298 | u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN; | ||
1299 | smsc9420_reg_write(pd, COE_CR, coe); | ||
1300 | smsc_dbg(IFUP, "COE_CR = 0x%08x", coe); | ||
1301 | } | ||
1302 | |||
1303 | smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr); | ||
1304 | smsc9420_pci_flush_write(pd); | ||
1305 | |||
1306 | return 0; | ||
1307 | |||
1308 | out_free_rx_skbs: | ||
1309 | smsc9420_free_rx_ring(pd); | ||
1310 | out: | ||
1311 | return -ENOMEM; | ||
1312 | } | ||
1313 | |||
1314 | static int smsc9420_open(struct net_device *dev) | ||
1315 | { | ||
1316 | struct smsc9420_pdata *pd; | ||
1317 | u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl; | ||
1318 | unsigned long flags; | ||
1319 | int result = 0, timeout; | ||
1320 | |||
1321 | BUG_ON(!dev); | ||
1322 | pd = netdev_priv(dev); | ||
1323 | BUG_ON(!pd); | ||
1324 | |||
1325 | if (!is_valid_ether_addr(dev->dev_addr)) { | ||
1326 | smsc_warn(IFUP, "dev_addr is not a valid MAC address"); | ||
1327 | result = -EADDRNOTAVAIL; | ||
1328 | goto out_0; | ||
1329 | } | ||
1330 | |||
1331 | netif_carrier_off(dev); | ||
1332 | |||
1333 | /* disable, mask and acknowlege all interrupts */ | ||
1334 | spin_lock_irqsave(&pd->int_lock, flags); | ||
1335 | int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); | ||
1336 | smsc9420_reg_write(pd, INT_CFG, int_cfg); | ||
1337 | smsc9420_reg_write(pd, INT_CTL, 0); | ||
1338 | spin_unlock_irqrestore(&pd->int_lock, flags); | ||
1339 | smsc9420_reg_write(pd, DMAC_INTR_ENA, 0); | ||
1340 | smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF); | ||
1341 | smsc9420_pci_flush_write(pd); | ||
1342 | |||
1343 | if (request_irq(dev->irq, smsc9420_isr, IRQF_SHARED | IRQF_DISABLED, | ||
1344 | DRV_NAME, pd)) { | ||
1345 | smsc_warn(IFUP, "Unable to use IRQ = %d", dev->irq); | ||
1346 | result = -ENODEV; | ||
1347 | goto out_0; | ||
1348 | } | ||
1349 | |||
1350 | smsc9420_dmac_soft_reset(pd); | ||
1351 | |||
1352 | /* make sure MAC_CR is sane */ | ||
1353 | smsc9420_reg_write(pd, MAC_CR, 0); | ||
1354 | |||
1355 | smsc9420_set_mac_address(dev); | ||
1356 | |||
1357 | /* Configure GPIO pins to drive LEDs */ | ||
1358 | smsc9420_reg_write(pd, GPIO_CFG, | ||
1359 | (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_)); | ||
1360 | |||
1361 | bus_mode = BUS_MODE_DMA_BURST_LENGTH_16; | ||
1362 | |||
1363 | #ifdef __BIG_ENDIAN | ||
1364 | bus_mode |= BUS_MODE_DBO_; | ||
1365 | #endif | ||
1366 | |||
1367 | smsc9420_reg_write(pd, BUS_MODE, bus_mode); | ||
1368 | |||
1369 | smsc9420_pci_flush_write(pd); | ||
1370 | |||
1371 | /* set bus master bridge arbitration priority for Rx and TX DMA */ | ||
1372 | smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1); | ||
1373 | |||
1374 | smsc9420_reg_write(pd, DMAC_CONTROL, | ||
1375 | (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_)); | ||
1376 | |||
1377 | smsc9420_pci_flush_write(pd); | ||
1378 | |||
1379 | /* test the IRQ connection to the ISR */ | ||
1380 | smsc_dbg(IFUP, "Testing ISR using IRQ %d", dev->irq); | ||
1381 | |||
1382 | spin_lock_irqsave(&pd->int_lock, flags); | ||
1383 | /* configure interrupt deassertion timer and enable interrupts */ | ||
1384 | int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_; | ||
1385 | int_cfg &= ~(INT_CFG_INT_DEAS_MASK); | ||
1386 | int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK); | ||
1387 | smsc9420_reg_write(pd, INT_CFG, int_cfg); | ||
1388 | |||
1389 | /* unmask software interrupt */ | ||
1390 | int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_; | ||
1391 | smsc9420_reg_write(pd, INT_CTL, int_ctl); | ||
1392 | spin_unlock_irqrestore(&pd->int_lock, flags); | ||
1393 | smsc9420_pci_flush_write(pd); | ||
1394 | |||
1395 | timeout = 1000; | ||
1396 | pd->software_irq_signal = false; | ||
1397 | smp_wmb(); | ||
1398 | while (timeout--) { | ||
1399 | if (pd->software_irq_signal) | ||
1400 | break; | ||
1401 | msleep(1); | ||
1402 | } | ||
1403 | |||
1404 | /* disable interrupts */ | ||
1405 | spin_lock_irqsave(&pd->int_lock, flags); | ||
1406 | int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); | ||
1407 | smsc9420_reg_write(pd, INT_CFG, int_cfg); | ||
1408 | spin_unlock_irqrestore(&pd->int_lock, flags); | ||
1409 | |||
1410 | if (!pd->software_irq_signal) { | ||
1411 | smsc_warn(IFUP, "ISR failed signaling test"); | ||
1412 | result = -ENODEV; | ||
1413 | goto out_free_irq_1; | ||
1414 | } | ||
1415 | |||
1416 | smsc_dbg(IFUP, "ISR passed test using IRQ %d", dev->irq); | ||
1417 | |||
1418 | result = smsc9420_alloc_tx_ring(pd); | ||
1419 | if (result) { | ||
1420 | smsc_warn(IFUP, "Failed to Initialize tx dma ring"); | ||
1421 | result = -ENOMEM; | ||
1422 | goto out_free_irq_1; | ||
1423 | } | ||
1424 | |||
1425 | result = smsc9420_alloc_rx_ring(pd); | ||
1426 | if (result) { | ||
1427 | smsc_warn(IFUP, "Failed to Initialize rx dma ring"); | ||
1428 | result = -ENOMEM; | ||
1429 | goto out_free_tx_ring_2; | ||
1430 | } | ||
1431 | |||
1432 | result = smsc9420_mii_init(dev); | ||
1433 | if (result) { | ||
1434 | smsc_warn(IFUP, "Failed to initialize Phy"); | ||
1435 | result = -ENODEV; | ||
1436 | goto out_free_rx_ring_3; | ||
1437 | } | ||
1438 | |||
1439 | /* Bring the PHY up */ | ||
1440 | phy_start(pd->phy_dev); | ||
1441 | |||
1442 | napi_enable(&pd->napi); | ||
1443 | |||
1444 | /* start tx and rx */ | ||
1445 | mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_; | ||
1446 | smsc9420_reg_write(pd, MAC_CR, mac_cr); | ||
1447 | |||
1448 | dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); | ||
1449 | dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_; | ||
1450 | smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); | ||
1451 | smsc9420_pci_flush_write(pd); | ||
1452 | |||
1453 | dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); | ||
1454 | dma_intr_ena |= | ||
1455 | (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_); | ||
1456 | smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); | ||
1457 | smsc9420_pci_flush_write(pd); | ||
1458 | |||
1459 | netif_wake_queue(dev); | ||
1460 | |||
1461 | smsc9420_reg_write(pd, RX_POLL_DEMAND, 1); | ||
1462 | |||
1463 | /* enable interrupts */ | ||
1464 | spin_lock_irqsave(&pd->int_lock, flags); | ||
1465 | int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_; | ||
1466 | smsc9420_reg_write(pd, INT_CFG, int_cfg); | ||
1467 | spin_unlock_irqrestore(&pd->int_lock, flags); | ||
1468 | |||
1469 | return 0; | ||
1470 | |||
1471 | out_free_rx_ring_3: | ||
1472 | smsc9420_free_rx_ring(pd); | ||
1473 | out_free_tx_ring_2: | ||
1474 | smsc9420_free_tx_ring(pd); | ||
1475 | out_free_irq_1: | ||
1476 | free_irq(dev->irq, pd); | ||
1477 | out_0: | ||
1478 | return result; | ||
1479 | } | ||
1480 | |||
1481 | #ifdef CONFIG_PM | ||
1482 | |||
1483 | static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state) | ||
1484 | { | ||
1485 | struct net_device *dev = pci_get_drvdata(pdev); | ||
1486 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
1487 | u32 int_cfg; | ||
1488 | ulong flags; | ||
1489 | |||
1490 | /* disable interrupts */ | ||
1491 | spin_lock_irqsave(&pd->int_lock, flags); | ||
1492 | int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); | ||
1493 | smsc9420_reg_write(pd, INT_CFG, int_cfg); | ||
1494 | spin_unlock_irqrestore(&pd->int_lock, flags); | ||
1495 | |||
1496 | if (netif_running(dev)) { | ||
1497 | netif_tx_disable(dev); | ||
1498 | smsc9420_stop_tx(pd); | ||
1499 | smsc9420_free_tx_ring(pd); | ||
1500 | |||
1501 | napi_disable(&pd->napi); | ||
1502 | smsc9420_stop_rx(pd); | ||
1503 | smsc9420_free_rx_ring(pd); | ||
1504 | |||
1505 | free_irq(dev->irq, pd); | ||
1506 | |||
1507 | netif_device_detach(dev); | ||
1508 | } | ||
1509 | |||
1510 | pci_save_state(pdev); | ||
1511 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); | ||
1512 | pci_disable_device(pdev); | ||
1513 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | ||
1514 | |||
1515 | return 0; | ||
1516 | } | ||
1517 | |||
1518 | static int smsc9420_resume(struct pci_dev *pdev) | ||
1519 | { | ||
1520 | struct net_device *dev = pci_get_drvdata(pdev); | ||
1521 | struct smsc9420_pdata *pd = netdev_priv(dev); | ||
1522 | int err; | ||
1523 | |||
1524 | pci_set_power_state(pdev, PCI_D0); | ||
1525 | pci_restore_state(pdev); | ||
1526 | |||
1527 | err = pci_enable_device(pdev); | ||
1528 | if (err) | ||
1529 | return err; | ||
1530 | |||
1531 | pci_set_master(pdev); | ||
1532 | |||
1533 | err = pci_enable_wake(pdev, 0, 0); | ||
1534 | if (err) | ||
1535 | smsc_warn(IFUP, "pci_enable_wake failed: %d", err); | ||
1536 | |||
1537 | if (netif_running(dev)) { | ||
1538 | err = smsc9420_open(dev); | ||
1539 | netif_device_attach(dev); | ||
1540 | } | ||
1541 | return err; | ||
1542 | } | ||
1543 | |||
1544 | #endif /* CONFIG_PM */ | ||
1545 | |||
1546 | static const struct net_device_ops smsc9420_netdev_ops = { | ||
1547 | .ndo_open = smsc9420_open, | ||
1548 | .ndo_stop = smsc9420_stop, | ||
1549 | .ndo_start_xmit = smsc9420_hard_start_xmit, | ||
1550 | .ndo_get_stats = smsc9420_get_stats, | ||
1551 | .ndo_set_multicast_list = smsc9420_set_multicast_list, | ||
1552 | .ndo_do_ioctl = smsc9420_do_ioctl, | ||
1553 | .ndo_validate_addr = eth_validate_addr, | ||
1554 | #ifdef CONFIG_NET_POLL_CONTROLLER | ||
1555 | .ndo_poll_controller = smsc9420_poll_controller, | ||
1556 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | ||
1557 | }; | ||
1558 | |||
1559 | static int __devinit | ||
1560 | smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id) | ||
1561 | { | ||
1562 | struct net_device *dev; | ||
1563 | struct smsc9420_pdata *pd; | ||
1564 | void __iomem *virt_addr; | ||
1565 | int result = 0; | ||
1566 | u32 id_rev; | ||
1567 | |||
1568 | printk(KERN_INFO DRV_DESCRIPTION " version " DRV_VERSION "\n"); | ||
1569 | |||
1570 | /* First do the PCI initialisation */ | ||
1571 | result = pci_enable_device(pdev); | ||
1572 | if (unlikely(result)) { | ||
1573 | printk(KERN_ERR "Cannot enable smsc9420\n"); | ||
1574 | goto out_0; | ||
1575 | } | ||
1576 | |||
1577 | pci_set_master(pdev); | ||
1578 | |||
1579 | dev = alloc_etherdev(sizeof(*pd)); | ||
1580 | if (!dev) { | ||
1581 | printk(KERN_ERR "ether device alloc failed\n"); | ||
1582 | goto out_disable_pci_device_1; | ||
1583 | } | ||
1584 | |||
1585 | SET_NETDEV_DEV(dev, &pdev->dev); | ||
1586 | |||
1587 | if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) { | ||
1588 | printk(KERN_ERR "Cannot find PCI device base address\n"); | ||
1589 | goto out_free_netdev_2; | ||
1590 | } | ||
1591 | |||
1592 | if ((pci_request_regions(pdev, DRV_NAME))) { | ||
1593 | printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n"); | ||
1594 | goto out_free_netdev_2; | ||
1595 | } | ||
1596 | |||
1597 | if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { | ||
1598 | printk(KERN_ERR "No usable DMA configuration, aborting.\n"); | ||
1599 | goto out_free_regions_3; | ||
1600 | } | ||
1601 | |||
1602 | virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR), | ||
1603 | pci_resource_len(pdev, SMSC_BAR)); | ||
1604 | if (!virt_addr) { | ||
1605 | printk(KERN_ERR "Cannot map device registers, aborting.\n"); | ||
1606 | goto out_free_regions_3; | ||
1607 | } | ||
1608 | |||
1609 | /* registers are double mapped with 0 offset for LE and 0x200 for BE */ | ||
1610 | virt_addr += LAN9420_CPSR_ENDIAN_OFFSET; | ||
1611 | |||
1612 | dev->base_addr = (ulong)virt_addr; | ||
1613 | |||
1614 | pd = netdev_priv(dev); | ||
1615 | |||
1616 | /* pci descriptors are created in the PCI consistent area */ | ||
1617 | pd->rx_ring = pci_alloc_consistent(pdev, | ||
1618 | sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE + | ||
1619 | sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE, | ||
1620 | &pd->rx_dma_addr); | ||
1621 | |||
1622 | if (!pd->rx_ring) | ||
1623 | goto out_free_io_4; | ||
1624 | |||
1625 | /* descriptors are aligned due to the nature of pci_alloc_consistent */ | ||
1626 | pd->tx_ring = (struct smsc9420_dma_desc *) | ||
1627 | (pd->rx_ring + RX_RING_SIZE); | ||
1628 | pd->tx_dma_addr = pd->rx_dma_addr + | ||
1629 | sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE; | ||
1630 | |||
1631 | pd->pdev = pdev; | ||
1632 | pd->dev = dev; | ||
1633 | pd->base_addr = virt_addr; | ||
1634 | pd->msg_enable = smsc_debug; | ||
1635 | pd->rx_csum = true; | ||
1636 | |||
1637 | smsc_dbg(PROBE, "lan_base=0x%08lx", (ulong)virt_addr); | ||
1638 | |||
1639 | id_rev = smsc9420_reg_read(pd, ID_REV); | ||
1640 | switch (id_rev & 0xFFFF0000) { | ||
1641 | case 0x94200000: | ||
1642 | smsc_info(PROBE, "LAN9420 identified, ID_REV=0x%08X", id_rev); | ||
1643 | break; | ||
1644 | default: | ||
1645 | smsc_warn(PROBE, "LAN9420 NOT identified"); | ||
1646 | smsc_warn(PROBE, "ID_REV=0x%08X", id_rev); | ||
1647 | goto out_free_dmadesc_5; | ||
1648 | } | ||
1649 | |||
1650 | smsc9420_dmac_soft_reset(pd); | ||
1651 | smsc9420_eeprom_reload(pd); | ||
1652 | smsc9420_check_mac_address(dev); | ||
1653 | |||
1654 | dev->netdev_ops = &smsc9420_netdev_ops; | ||
1655 | dev->ethtool_ops = &smsc9420_ethtool_ops; | ||
1656 | dev->irq = pdev->irq; | ||
1657 | |||
1658 | netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT); | ||
1659 | |||
1660 | result = register_netdev(dev); | ||
1661 | if (result) { | ||
1662 | smsc_warn(PROBE, "error %i registering device", result); | ||
1663 | goto out_free_dmadesc_5; | ||
1664 | } | ||
1665 | |||
1666 | pci_set_drvdata(pdev, dev); | ||
1667 | |||
1668 | spin_lock_init(&pd->int_lock); | ||
1669 | spin_lock_init(&pd->phy_lock); | ||
1670 | |||
1671 | dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr); | ||
1672 | |||
1673 | return 0; | ||
1674 | |||
1675 | out_free_dmadesc_5: | ||
1676 | pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) * | ||
1677 | (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr); | ||
1678 | out_free_io_4: | ||
1679 | iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET); | ||
1680 | out_free_regions_3: | ||
1681 | pci_release_regions(pdev); | ||
1682 | out_free_netdev_2: | ||
1683 | free_netdev(dev); | ||
1684 | out_disable_pci_device_1: | ||
1685 | pci_disable_device(pdev); | ||
1686 | out_0: | ||
1687 | return -ENODEV; | ||
1688 | } | ||
1689 | |||
1690 | static void __devexit smsc9420_remove(struct pci_dev *pdev) | ||
1691 | { | ||
1692 | struct net_device *dev; | ||
1693 | struct smsc9420_pdata *pd; | ||
1694 | |||
1695 | dev = pci_get_drvdata(pdev); | ||
1696 | if (!dev) | ||
1697 | return; | ||
1698 | |||
1699 | pci_set_drvdata(pdev, NULL); | ||
1700 | |||
1701 | pd = netdev_priv(dev); | ||
1702 | unregister_netdev(dev); | ||
1703 | |||
1704 | /* tx_buffers and rx_buffers are freed in stop */ | ||
1705 | BUG_ON(pd->tx_buffers); | ||
1706 | BUG_ON(pd->rx_buffers); | ||
1707 | |||
1708 | BUG_ON(!pd->tx_ring); | ||
1709 | BUG_ON(!pd->rx_ring); | ||
1710 | |||
1711 | pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) * | ||
1712 | (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr); | ||
1713 | |||
1714 | iounmap(pd->base_addr - LAN9420_CPSR_ENDIAN_OFFSET); | ||
1715 | pci_release_regions(pdev); | ||
1716 | free_netdev(dev); | ||
1717 | pci_disable_device(pdev); | ||
1718 | } | ||
1719 | |||
1720 | static struct pci_driver smsc9420_driver = { | ||
1721 | .name = DRV_NAME, | ||
1722 | .id_table = smsc9420_id_table, | ||
1723 | .probe = smsc9420_probe, | ||
1724 | .remove = __devexit_p(smsc9420_remove), | ||
1725 | #ifdef CONFIG_PM | ||
1726 | .suspend = smsc9420_suspend, | ||
1727 | .resume = smsc9420_resume, | ||
1728 | #endif /* CONFIG_PM */ | ||
1729 | }; | ||
1730 | |||
1731 | static int __init smsc9420_init_module(void) | ||
1732 | { | ||
1733 | smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT); | ||
1734 | |||
1735 | return pci_register_driver(&smsc9420_driver); | ||
1736 | } | ||
1737 | |||
1738 | static void __exit smsc9420_exit_module(void) | ||
1739 | { | ||
1740 | pci_unregister_driver(&smsc9420_driver); | ||
1741 | } | ||
1742 | |||
1743 | module_init(smsc9420_init_module); | ||
1744 | module_exit(smsc9420_exit_module); | ||