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-rw-r--r--drivers/net/smc91x.h331
1 files changed, 160 insertions, 171 deletions
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index 51d4134b37b1..69e97a1cb1c4 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -34,6 +34,7 @@
34#ifndef _SMC91X_H_ 34#ifndef _SMC91X_H_
35#define _SMC91X_H_ 35#define _SMC91X_H_
36 36
37#include <linux/smc91x.h>
37 38
38/* 39/*
39 * Define your architecture specific bus configuration parameters here. 40 * Define your architecture specific bus configuration parameters here.
@@ -291,36 +292,6 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
291#define SMC_insw(a, r, p, l) insw((a) + (r), p, l) 292#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
292#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) 293#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
293 294
294#elif defined(CONFIG_SUPERH)
295
296#ifdef CONFIG_SOLUTION_ENGINE
297#define SMC_IRQ_FLAGS (0)
298#define SMC_CAN_USE_8BIT 0
299#define SMC_CAN_USE_16BIT 1
300#define SMC_CAN_USE_32BIT 0
301#define SMC_IO_SHIFT 0
302#define SMC_NOWAIT 1
303
304#define SMC_inw(a, r) inw((a) + (r))
305#define SMC_outw(v, a, r) outw(v, (a) + (r))
306#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
307#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
308
309#else /* BOARDS */
310
311#define SMC_CAN_USE_8BIT 1
312#define SMC_CAN_USE_16BIT 1
313#define SMC_CAN_USE_32BIT 0
314
315#define SMC_inb(a, r) inb((a) + (r))
316#define SMC_inw(a, r) inw((a) + (r))
317#define SMC_outb(v, a, r) outb(v, (a) + (r))
318#define SMC_outw(v, a, r) outw(v, (a) + (r))
319#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
320#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
321
322#endif /* BOARDS */
323
324#elif defined(CONFIG_M32R) 295#elif defined(CONFIG_M32R)
325 296
326#define SMC_CAN_USE_8BIT 0 297#define SMC_CAN_USE_8BIT 0
@@ -475,12 +446,15 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
475#define SMC_outb(v, a, r) writeb(v, (a) + (r)) 446#define SMC_outb(v, a, r) writeb(v, (a) + (r))
476#define SMC_outw(v, a, r) writew(v, (a) + (r)) 447#define SMC_outw(v, a, r) writew(v, (a) + (r))
477#define SMC_outl(v, a, r) writel(v, (a) + (r)) 448#define SMC_outl(v, a, r) writel(v, (a) + (r))
449#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
450#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
478#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) 451#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
479#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) 452#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
480 453
481#define RPC_LSA_DEFAULT RPC_LED_100_10 454#define RPC_LSA_DEFAULT RPC_LED_100_10
482#define RPC_LSB_DEFAULT RPC_LED_TX_RX 455#define RPC_LSB_DEFAULT RPC_LED_TX_RX
483 456
457#define SMC_DYNAMIC_BUS_CONFIG
484#endif 458#endif
485 459
486 460
@@ -526,8 +500,19 @@ struct smc_local {
526#endif 500#endif
527 void __iomem *base; 501 void __iomem *base;
528 void __iomem *datacs; 502 void __iomem *datacs;
503
504 struct smc91x_platdata cfg;
529}; 505};
530 506
507#ifdef SMC_DYNAMIC_BUS_CONFIG
508#define SMC_8BIT(p) (((p)->cfg.flags & SMC91X_USE_8BIT) && SMC_CAN_USE_8BIT)
509#define SMC_16BIT(p) (((p)->cfg.flags & SMC91X_USE_16BIT) && SMC_CAN_USE_16BIT)
510#define SMC_32BIT(p) (((p)->cfg.flags & SMC91X_USE_32BIT) && SMC_CAN_USE_32BIT)
511#else
512#define SMC_8BIT(p) SMC_CAN_USE_8BIT
513#define SMC_16BIT(p) SMC_CAN_USE_16BIT
514#define SMC_32BIT(p) SMC_CAN_USE_32BIT
515#endif
531 516
532#ifdef SMC_USE_PXA_DMA 517#ifdef SMC_USE_PXA_DMA
533/* 518/*
@@ -720,7 +705,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
720 705
721// Transmit Control Register 706// Transmit Control Register
722/* BANK 0 */ 707/* BANK 0 */
723#define TCR_REG SMC_REG(0x0000, 0) 708#define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
724#define TCR_ENABLE 0x0001 // When 1 we can transmit 709#define TCR_ENABLE 0x0001 // When 1 we can transmit
725#define TCR_LOOP 0x0002 // Controls output pin LBK 710#define TCR_LOOP 0x0002 // Controls output pin LBK
726#define TCR_FORCOL 0x0004 // When 1 will force a collision 711#define TCR_FORCOL 0x0004 // When 1 will force a collision
@@ -739,7 +724,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
739 724
740// EPH Status Register 725// EPH Status Register
741/* BANK 0 */ 726/* BANK 0 */
742#define EPH_STATUS_REG SMC_REG(0x0002, 0) 727#define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
743#define ES_TX_SUC 0x0001 // Last TX was successful 728#define ES_TX_SUC 0x0001 // Last TX was successful
744#define ES_SNGL_COL 0x0002 // Single collision detected for last tx 729#define ES_SNGL_COL 0x0002 // Single collision detected for last tx
745#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx 730#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
@@ -758,7 +743,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
758 743
759// Receive Control Register 744// Receive Control Register
760/* BANK 0 */ 745/* BANK 0 */
761#define RCR_REG SMC_REG(0x0004, 0) 746#define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
762#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted 747#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
763#define RCR_PRMS 0x0002 // Enable promiscuous mode 748#define RCR_PRMS 0x0002 // Enable promiscuous mode
764#define RCR_ALMUL 0x0004 // When set accepts all multicast frames 749#define RCR_ALMUL 0x0004 // When set accepts all multicast frames
@@ -775,17 +760,17 @@ smc_pxa_dma_irq(int dma, void *dummy)
775 760
776// Counter Register 761// Counter Register
777/* BANK 0 */ 762/* BANK 0 */
778#define COUNTER_REG SMC_REG(0x0006, 0) 763#define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
779 764
780 765
781// Memory Information Register 766// Memory Information Register
782/* BANK 0 */ 767/* BANK 0 */
783#define MIR_REG SMC_REG(0x0008, 0) 768#define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
784 769
785 770
786// Receive/Phy Control Register 771// Receive/Phy Control Register
787/* BANK 0 */ 772/* BANK 0 */
788#define RPC_REG SMC_REG(0x000A, 0) 773#define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
789#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. 774#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
790#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode 775#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
791#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode 776#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
@@ -819,7 +804,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
819 804
820// Configuration Reg 805// Configuration Reg
821/* BANK 1 */ 806/* BANK 1 */
822#define CONFIG_REG SMC_REG(0x0000, 1) 807#define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
823#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy 808#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
824#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL 809#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
825#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus 810#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
@@ -831,24 +816,24 @@ smc_pxa_dma_irq(int dma, void *dummy)
831 816
832// Base Address Register 817// Base Address Register
833/* BANK 1 */ 818/* BANK 1 */
834#define BASE_REG SMC_REG(0x0002, 1) 819#define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
835 820
836 821
837// Individual Address Registers 822// Individual Address Registers
838/* BANK 1 */ 823/* BANK 1 */
839#define ADDR0_REG SMC_REG(0x0004, 1) 824#define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
840#define ADDR1_REG SMC_REG(0x0006, 1) 825#define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
841#define ADDR2_REG SMC_REG(0x0008, 1) 826#define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
842 827
843 828
844// General Purpose Register 829// General Purpose Register
845/* BANK 1 */ 830/* BANK 1 */
846#define GP_REG SMC_REG(0x000A, 1) 831#define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
847 832
848 833
849// Control Register 834// Control Register
850/* BANK 1 */ 835/* BANK 1 */
851#define CTL_REG SMC_REG(0x000C, 1) 836#define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
852#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received 837#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
853#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically 838#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
854#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt 839#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
@@ -861,7 +846,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
861 846
862// MMU Command Register 847// MMU Command Register
863/* BANK 2 */ 848/* BANK 2 */
864#define MMU_CMD_REG SMC_REG(0x0000, 2) 849#define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
865#define MC_BUSY 1 // When 1 the last release has not completed 850#define MC_BUSY 1 // When 1 the last release has not completed
866#define MC_NOP (0<<5) // No Op 851#define MC_NOP (0<<5) // No Op
867#define MC_ALLOC (1<<5) // OR with number of 256 byte packets 852#define MC_ALLOC (1<<5) // OR with number of 256 byte packets
@@ -875,30 +860,30 @@ smc_pxa_dma_irq(int dma, void *dummy)
875 860
876// Packet Number Register 861// Packet Number Register
877/* BANK 2 */ 862/* BANK 2 */
878#define PN_REG SMC_REG(0x0002, 2) 863#define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
879 864
880 865
881// Allocation Result Register 866// Allocation Result Register
882/* BANK 2 */ 867/* BANK 2 */
883#define AR_REG SMC_REG(0x0003, 2) 868#define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
884#define AR_FAILED 0x80 // Alocation Failed 869#define AR_FAILED 0x80 // Alocation Failed
885 870
886 871
887// TX FIFO Ports Register 872// TX FIFO Ports Register
888/* BANK 2 */ 873/* BANK 2 */
889#define TXFIFO_REG SMC_REG(0x0004, 2) 874#define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
890#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty 875#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
891 876
892// RX FIFO Ports Register 877// RX FIFO Ports Register
893/* BANK 2 */ 878/* BANK 2 */
894#define RXFIFO_REG SMC_REG(0x0005, 2) 879#define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
895#define RXFIFO_REMPTY 0x80 // RX FIFO Empty 880#define RXFIFO_REMPTY 0x80 // RX FIFO Empty
896 881
897#define FIFO_REG SMC_REG(0x0004, 2) 882#define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
898 883
899// Pointer Register 884// Pointer Register
900/* BANK 2 */ 885/* BANK 2 */
901#define PTR_REG SMC_REG(0x0006, 2) 886#define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
902#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area 887#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
903#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access 888#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
904#define PTR_READ 0x2000 // When 1 the operation is a read 889#define PTR_READ 0x2000 // When 1 the operation is a read
@@ -906,17 +891,17 @@ smc_pxa_dma_irq(int dma, void *dummy)
906 891
907// Data Register 892// Data Register
908/* BANK 2 */ 893/* BANK 2 */
909#define DATA_REG SMC_REG(0x0008, 2) 894#define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
910 895
911 896
912// Interrupt Status/Acknowledge Register 897// Interrupt Status/Acknowledge Register
913/* BANK 2 */ 898/* BANK 2 */
914#define INT_REG SMC_REG(0x000C, 2) 899#define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
915 900
916 901
917// Interrupt Mask Register 902// Interrupt Mask Register
918/* BANK 2 */ 903/* BANK 2 */
919#define IM_REG SMC_REG(0x000D, 2) 904#define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
920#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt 905#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
921#define IM_ERCV_INT 0x40 // Early Receive Interrupt 906#define IM_ERCV_INT 0x40 // Early Receive Interrupt
922#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section 907#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
@@ -929,15 +914,15 @@ smc_pxa_dma_irq(int dma, void *dummy)
929 914
930// Multicast Table Registers 915// Multicast Table Registers
931/* BANK 3 */ 916/* BANK 3 */
932#define MCAST_REG1 SMC_REG(0x0000, 3) 917#define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
933#define MCAST_REG2 SMC_REG(0x0002, 3) 918#define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
934#define MCAST_REG3 SMC_REG(0x0004, 3) 919#define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
935#define MCAST_REG4 SMC_REG(0x0006, 3) 920#define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
936 921
937 922
938// Management Interface Register (MII) 923// Management Interface Register (MII)
939/* BANK 3 */ 924/* BANK 3 */
940#define MII_REG SMC_REG(0x0008, 3) 925#define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
941#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup 926#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
942#define MII_MDOE 0x0008 // MII Output Enable 927#define MII_MDOE 0x0008 // MII Output Enable
943#define MII_MCLK 0x0004 // MII Clock, pin MDCLK 928#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
@@ -948,20 +933,20 @@ smc_pxa_dma_irq(int dma, void *dummy)
948// Revision Register 933// Revision Register
949/* BANK 3 */ 934/* BANK 3 */
950/* ( hi: chip id low: rev # ) */ 935/* ( hi: chip id low: rev # ) */
951#define REV_REG SMC_REG(0x000A, 3) 936#define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
952 937
953 938
954// Early RCV Register 939// Early RCV Register
955/* BANK 3 */ 940/* BANK 3 */
956/* this is NOT on SMC9192 */ 941/* this is NOT on SMC9192 */
957#define ERCV_REG SMC_REG(0x000C, 3) 942#define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
958#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received 943#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
959#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask 944#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
960 945
961 946
962// External Register 947// External Register
963/* BANK 7 */ 948/* BANK 7 */
964#define EXT_REG SMC_REG(0x0000, 7) 949#define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
965 950
966 951
967#define CHIP_9192 3 952#define CHIP_9192 3
@@ -1085,9 +1070,9 @@ static const char * chip_ids[ 16 ] = {
1085 */ 1070 */
1086 1071
1087#if SMC_DEBUG > 0 1072#if SMC_DEBUG > 0
1088#define SMC_REG(reg, bank) \ 1073#define SMC_REG(lp, reg, bank) \
1089 ({ \ 1074 ({ \
1090 int __b = SMC_CURRENT_BANK(); \ 1075 int __b = SMC_CURRENT_BANK(lp); \
1091 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ 1076 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1092 printk( "%s: bank reg screwed (0x%04x)\n", \ 1077 printk( "%s: bank reg screwed (0x%04x)\n", \
1093 CARDNAME, __b ); \ 1078 CARDNAME, __b ); \
@@ -1096,7 +1081,7 @@ static const char * chip_ids[ 16 ] = {
1096 reg<<SMC_IO_SHIFT; \ 1081 reg<<SMC_IO_SHIFT; \
1097 }) 1082 })
1098#else 1083#else
1099#define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT) 1084#define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
1100#endif 1085#endif
1101 1086
1102/* 1087/*
@@ -1108,212 +1093,215 @@ static const char * chip_ids[ 16 ] = {
1108 * 1093 *
1109 * Enforce it on any 32-bit capable setup for now. 1094 * Enforce it on any 32-bit capable setup for now.
1110 */ 1095 */
1111#define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT 1096#define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
1112 1097
1113#define SMC_GET_PN() \ 1098#define SMC_GET_PN(lp) \
1114 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \ 1099 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
1115 : (SMC_inw(ioaddr, PN_REG) & 0xFF) ) 1100 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
1116 1101
1117#define SMC_SET_PN(x) \ 1102#define SMC_SET_PN(lp, x) \
1118 do { \ 1103 do { \
1119 if (SMC_MUST_ALIGN_WRITE) \ 1104 if (SMC_MUST_ALIGN_WRITE(lp)) \
1120 SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \ 1105 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
1121 else if (SMC_CAN_USE_8BIT) \ 1106 else if (SMC_8BIT(lp)) \
1122 SMC_outb(x, ioaddr, PN_REG); \ 1107 SMC_outb(x, ioaddr, PN_REG(lp)); \
1123 else \ 1108 else \
1124 SMC_outw(x, ioaddr, PN_REG); \ 1109 SMC_outw(x, ioaddr, PN_REG(lp)); \
1125 } while (0) 1110 } while (0)
1126 1111
1127#define SMC_GET_AR() \ 1112#define SMC_GET_AR(lp) \
1128 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \ 1113 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
1129 : (SMC_inw(ioaddr, PN_REG) >> 8) ) 1114 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
1130 1115
1131#define SMC_GET_TXFIFO() \ 1116#define SMC_GET_TXFIFO(lp) \
1132 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \ 1117 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
1133 : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) ) 1118 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
1134 1119
1135#define SMC_GET_RXFIFO() \ 1120#define SMC_GET_RXFIFO(lp) \
1136 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \ 1121 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
1137 : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) ) 1122 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
1138 1123
1139#define SMC_GET_INT() \ 1124#define SMC_GET_INT(lp) \
1140 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \ 1125 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
1141 : (SMC_inw(ioaddr, INT_REG) & 0xFF) ) 1126 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
1142 1127
1143#define SMC_ACK_INT(x) \ 1128#define SMC_ACK_INT(lp, x) \
1144 do { \ 1129 do { \
1145 if (SMC_CAN_USE_8BIT) \ 1130 if (SMC_8BIT(lp)) \
1146 SMC_outb(x, ioaddr, INT_REG); \ 1131 SMC_outb(x, ioaddr, INT_REG(lp)); \
1147 else { \ 1132 else { \
1148 unsigned long __flags; \ 1133 unsigned long __flags; \
1149 int __mask; \ 1134 int __mask; \
1150 local_irq_save(__flags); \ 1135 local_irq_save(__flags); \
1151 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \ 1136 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1152 SMC_outw( __mask | (x), ioaddr, INT_REG ); \ 1137 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
1153 local_irq_restore(__flags); \ 1138 local_irq_restore(__flags); \
1154 } \ 1139 } \
1155 } while (0) 1140 } while (0)
1156 1141
1157#define SMC_GET_INT_MASK() \ 1142#define SMC_GET_INT_MASK(lp) \
1158 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \ 1143 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
1159 : (SMC_inw( ioaddr, INT_REG ) >> 8) ) 1144 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
1160 1145
1161#define SMC_SET_INT_MASK(x) \ 1146#define SMC_SET_INT_MASK(lp, x) \
1162 do { \ 1147 do { \
1163 if (SMC_CAN_USE_8BIT) \ 1148 if (SMC_8BIT(lp)) \
1164 SMC_outb(x, ioaddr, IM_REG); \ 1149 SMC_outb(x, ioaddr, IM_REG(lp)); \
1165 else \ 1150 else \
1166 SMC_outw((x) << 8, ioaddr, INT_REG); \ 1151 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
1167 } while (0) 1152 } while (0)
1168 1153
1169#define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT) 1154#define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
1170 1155
1171#define SMC_SELECT_BANK(x) \ 1156#define SMC_SELECT_BANK(lp, x) \
1172 do { \ 1157 do { \
1173 if (SMC_MUST_ALIGN_WRITE) \ 1158 if (SMC_MUST_ALIGN_WRITE(lp)) \
1174 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \ 1159 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1175 else \ 1160 else \
1176 SMC_outw(x, ioaddr, BANK_SELECT); \ 1161 SMC_outw(x, ioaddr, BANK_SELECT); \
1177 } while (0) 1162 } while (0)
1178 1163
1179#define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG) 1164#define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
1180 1165
1181#define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG) 1166#define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
1182 1167
1183#define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG) 1168#define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
1184 1169
1185#define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG) 1170#define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
1186 1171
1187#define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG) 1172#define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
1188 1173
1189#define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG) 1174#define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
1190 1175
1191#define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG) 1176#define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
1192 1177
1193#define SMC_GET_MII() SMC_inw(ioaddr, MII_REG) 1178#define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
1194 1179
1195#define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG) 1180#define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
1196 1181
1197#define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG) 1182#define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
1198 1183
1199#define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG) 1184#define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
1200 1185
1201#define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG) 1186#define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
1202 1187
1203#define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG) 1188#define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1204 1189
1205#define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG) 1190#define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
1206 1191
1207#define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG) 1192#define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
1208 1193
1209#define SMC_SET_PTR(x) \ 1194#define SMC_SET_PTR(lp, x) \
1210 do { \ 1195 do { \
1211 if (SMC_MUST_ALIGN_WRITE) \ 1196 if (SMC_MUST_ALIGN_WRITE(lp)) \
1212 SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \ 1197 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1213 else \ 1198 else \
1214 SMC_outw(x, ioaddr, PTR_REG); \ 1199 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1215 } while (0) 1200 } while (0)
1216 1201
1217#define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG) 1202#define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1218 1203
1219#define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG) 1204#define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1220 1205
1221#define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG) 1206#define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
1222 1207
1223#define SMC_GET_REV() SMC_inw(ioaddr, REV_REG) 1208#define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1224 1209
1225#define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG) 1210#define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1226 1211
1227#define SMC_SET_RPC(x) \ 1212#define SMC_SET_RPC(lp, x) \
1228 do { \ 1213 do { \
1229 if (SMC_MUST_ALIGN_WRITE) \ 1214 if (SMC_MUST_ALIGN_WRITE(lp)) \
1230 SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \ 1215 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1231 else \ 1216 else \
1232 SMC_outw(x, ioaddr, RPC_REG); \ 1217 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1233 } while (0) 1218 } while (0)
1234 1219
1235#define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG) 1220#define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1236 1221
1237#define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG) 1222#define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1238 1223
1239#ifndef SMC_GET_MAC_ADDR 1224#ifndef SMC_GET_MAC_ADDR
1240#define SMC_GET_MAC_ADDR(addr) \ 1225#define SMC_GET_MAC_ADDR(lp, addr) \
1241 do { \ 1226 do { \
1242 unsigned int __v; \ 1227 unsigned int __v; \
1243 __v = SMC_inw( ioaddr, ADDR0_REG ); \ 1228 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1244 addr[0] = __v; addr[1] = __v >> 8; \ 1229 addr[0] = __v; addr[1] = __v >> 8; \
1245 __v = SMC_inw( ioaddr, ADDR1_REG ); \ 1230 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1246 addr[2] = __v; addr[3] = __v >> 8; \ 1231 addr[2] = __v; addr[3] = __v >> 8; \
1247 __v = SMC_inw( ioaddr, ADDR2_REG ); \ 1232 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1248 addr[4] = __v; addr[5] = __v >> 8; \ 1233 addr[4] = __v; addr[5] = __v >> 8; \
1249 } while (0) 1234 } while (0)
1250#endif 1235#endif
1251 1236
1252#define SMC_SET_MAC_ADDR(addr) \ 1237#define SMC_SET_MAC_ADDR(lp, addr) \
1253 do { \ 1238 do { \
1254 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \ 1239 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1255 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \ 1240 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1256 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \ 1241 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1257 } while (0) 1242 } while (0)
1258 1243
1259#define SMC_SET_MCAST(x) \ 1244#define SMC_SET_MCAST(lp, x) \
1260 do { \ 1245 do { \
1261 const unsigned char *mt = (x); \ 1246 const unsigned char *mt = (x); \
1262 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \ 1247 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1263 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \ 1248 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1264 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \ 1249 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1265 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \ 1250 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1266 } while (0) 1251 } while (0)
1267 1252
1268#define SMC_PUT_PKT_HDR(status, length) \ 1253#define SMC_PUT_PKT_HDR(lp, status, length) \
1269 do { \ 1254 do { \
1270 if (SMC_CAN_USE_32BIT) \ 1255 if (SMC_32BIT(lp)) \
1271 SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \ 1256 SMC_outl((status) | (length)<<16, ioaddr, \
1257 DATA_REG(lp)); \
1272 else { \ 1258 else { \
1273 SMC_outw(status, ioaddr, DATA_REG); \ 1259 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1274 SMC_outw(length, ioaddr, DATA_REG); \ 1260 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1275 } \ 1261 } \
1276 } while (0) 1262 } while (0)
1277 1263
1278#define SMC_GET_PKT_HDR(status, length) \ 1264#define SMC_GET_PKT_HDR(lp, status, length) \
1279 do { \ 1265 do { \
1280 if (SMC_CAN_USE_32BIT) { \ 1266 if (SMC_32BIT(lp)) { \
1281 unsigned int __val = SMC_inl(ioaddr, DATA_REG); \ 1267 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1282 (status) = __val & 0xffff; \ 1268 (status) = __val & 0xffff; \
1283 (length) = __val >> 16; \ 1269 (length) = __val >> 16; \
1284 } else { \ 1270 } else { \
1285 (status) = SMC_inw(ioaddr, DATA_REG); \ 1271 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1286 (length) = SMC_inw(ioaddr, DATA_REG); \ 1272 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1287 } \ 1273 } \
1288 } while (0) 1274 } while (0)
1289 1275
1290#define SMC_PUSH_DATA(p, l) \ 1276#define SMC_PUSH_DATA(lp, p, l) \
1291 do { \ 1277 do { \
1292 if (SMC_CAN_USE_32BIT) { \ 1278 if (SMC_32BIT(lp)) { \
1293 void *__ptr = (p); \ 1279 void *__ptr = (p); \
1294 int __len = (l); \ 1280 int __len = (l); \
1295 void __iomem *__ioaddr = ioaddr; \ 1281 void __iomem *__ioaddr = ioaddr; \
1296 if (__len >= 2 && (unsigned long)__ptr & 2) { \ 1282 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1297 __len -= 2; \ 1283 __len -= 2; \
1298 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \ 1284 SMC_outw(*(u16 *)__ptr, ioaddr, \
1285 DATA_REG(lp)); \
1299 __ptr += 2; \ 1286 __ptr += 2; \
1300 } \ 1287 } \
1301 if (SMC_CAN_USE_DATACS && lp->datacs) \ 1288 if (SMC_CAN_USE_DATACS && lp->datacs) \
1302 __ioaddr = lp->datacs; \ 1289 __ioaddr = lp->datacs; \
1303 SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \ 1290 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1304 if (__len & 2) { \ 1291 if (__len & 2) { \
1305 __ptr += (__len & ~3); \ 1292 __ptr += (__len & ~3); \
1306 SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \ 1293 SMC_outw(*((u16 *)__ptr), ioaddr, \
1294 DATA_REG(lp)); \
1307 } \ 1295 } \
1308 } else if (SMC_CAN_USE_16BIT) \ 1296 } else if (SMC_16BIT(lp)) \
1309 SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \ 1297 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1310 else if (SMC_CAN_USE_8BIT) \ 1298 else if (SMC_8BIT(lp)) \
1311 SMC_outsb(ioaddr, DATA_REG, p, l); \ 1299 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1312 } while (0) 1300 } while (0)
1313 1301
1314#define SMC_PULL_DATA(p, l) \ 1302#define SMC_PULL_DATA(lp, p, l) \
1315 do { \ 1303 do { \
1316 if (SMC_CAN_USE_32BIT) { \ 1304 if (SMC_32BIT(lp)) { \
1317 void *__ptr = (p); \ 1305 void *__ptr = (p); \
1318 int __len = (l); \ 1306 int __len = (l); \
1319 void __iomem *__ioaddr = ioaddr; \ 1307 void __iomem *__ioaddr = ioaddr; \
@@ -1333,16 +1321,17 @@ static const char * chip_ids[ 16 ] = {
1333 */ \ 1321 */ \
1334 __ptr -= 2; \ 1322 __ptr -= 2; \
1335 __len += 2; \ 1323 __len += 2; \
1336 SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \ 1324 SMC_SET_PTR(lp, \
1325 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1337 } \ 1326 } \
1338 if (SMC_CAN_USE_DATACS && lp->datacs) \ 1327 if (SMC_CAN_USE_DATACS && lp->datacs) \
1339 __ioaddr = lp->datacs; \ 1328 __ioaddr = lp->datacs; \
1340 __len += 2; \ 1329 __len += 2; \
1341 SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \ 1330 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1342 } else if (SMC_CAN_USE_16BIT) \ 1331 } else if (SMC_16BIT(lp)) \
1343 SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \ 1332 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1344 else if (SMC_CAN_USE_8BIT) \ 1333 else if (SMC_8BIT(lp)) \
1345 SMC_insb(ioaddr, DATA_REG, p, l); \ 1334 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1346 } while (0) 1335 } while (0)
1347 1336
1348#endif /* _SMC91X_H_ */ 1337#endif /* _SMC91X_H_ */
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