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-rw-r--r--drivers/net/smc91x.h254
1 files changed, 129 insertions, 125 deletions
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index 51d4134b37b1..92ff9c42367e 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -720,7 +720,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
720 720
721// Transmit Control Register 721// Transmit Control Register
722/* BANK 0 */ 722/* BANK 0 */
723#define TCR_REG SMC_REG(0x0000, 0) 723#define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
724#define TCR_ENABLE 0x0001 // When 1 we can transmit 724#define TCR_ENABLE 0x0001 // When 1 we can transmit
725#define TCR_LOOP 0x0002 // Controls output pin LBK 725#define TCR_LOOP 0x0002 // Controls output pin LBK
726#define TCR_FORCOL 0x0004 // When 1 will force a collision 726#define TCR_FORCOL 0x0004 // When 1 will force a collision
@@ -739,7 +739,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
739 739
740// EPH Status Register 740// EPH Status Register
741/* BANK 0 */ 741/* BANK 0 */
742#define EPH_STATUS_REG SMC_REG(0x0002, 0) 742#define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
743#define ES_TX_SUC 0x0001 // Last TX was successful 743#define ES_TX_SUC 0x0001 // Last TX was successful
744#define ES_SNGL_COL 0x0002 // Single collision detected for last tx 744#define ES_SNGL_COL 0x0002 // Single collision detected for last tx
745#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx 745#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
@@ -758,7 +758,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
758 758
759// Receive Control Register 759// Receive Control Register
760/* BANK 0 */ 760/* BANK 0 */
761#define RCR_REG SMC_REG(0x0004, 0) 761#define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
762#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted 762#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
763#define RCR_PRMS 0x0002 // Enable promiscuous mode 763#define RCR_PRMS 0x0002 // Enable promiscuous mode
764#define RCR_ALMUL 0x0004 // When set accepts all multicast frames 764#define RCR_ALMUL 0x0004 // When set accepts all multicast frames
@@ -775,17 +775,17 @@ smc_pxa_dma_irq(int dma, void *dummy)
775 775
776// Counter Register 776// Counter Register
777/* BANK 0 */ 777/* BANK 0 */
778#define COUNTER_REG SMC_REG(0x0006, 0) 778#define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
779 779
780 780
781// Memory Information Register 781// Memory Information Register
782/* BANK 0 */ 782/* BANK 0 */
783#define MIR_REG SMC_REG(0x0008, 0) 783#define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
784 784
785 785
786// Receive/Phy Control Register 786// Receive/Phy Control Register
787/* BANK 0 */ 787/* BANK 0 */
788#define RPC_REG SMC_REG(0x000A, 0) 788#define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
789#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. 789#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
790#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode 790#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
791#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode 791#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
@@ -819,7 +819,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
819 819
820// Configuration Reg 820// Configuration Reg
821/* BANK 1 */ 821/* BANK 1 */
822#define CONFIG_REG SMC_REG(0x0000, 1) 822#define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
823#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy 823#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
824#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL 824#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
825#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus 825#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
@@ -831,24 +831,24 @@ smc_pxa_dma_irq(int dma, void *dummy)
831 831
832// Base Address Register 832// Base Address Register
833/* BANK 1 */ 833/* BANK 1 */
834#define BASE_REG SMC_REG(0x0002, 1) 834#define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
835 835
836 836
837// Individual Address Registers 837// Individual Address Registers
838/* BANK 1 */ 838/* BANK 1 */
839#define ADDR0_REG SMC_REG(0x0004, 1) 839#define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
840#define ADDR1_REG SMC_REG(0x0006, 1) 840#define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
841#define ADDR2_REG SMC_REG(0x0008, 1) 841#define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
842 842
843 843
844// General Purpose Register 844// General Purpose Register
845/* BANK 1 */ 845/* BANK 1 */
846#define GP_REG SMC_REG(0x000A, 1) 846#define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
847 847
848 848
849// Control Register 849// Control Register
850/* BANK 1 */ 850/* BANK 1 */
851#define CTL_REG SMC_REG(0x000C, 1) 851#define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
852#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received 852#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
853#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically 853#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
854#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt 854#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
@@ -861,7 +861,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
861 861
862// MMU Command Register 862// MMU Command Register
863/* BANK 2 */ 863/* BANK 2 */
864#define MMU_CMD_REG SMC_REG(0x0000, 2) 864#define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
865#define MC_BUSY 1 // When 1 the last release has not completed 865#define MC_BUSY 1 // When 1 the last release has not completed
866#define MC_NOP (0<<5) // No Op 866#define MC_NOP (0<<5) // No Op
867#define MC_ALLOC (1<<5) // OR with number of 256 byte packets 867#define MC_ALLOC (1<<5) // OR with number of 256 byte packets
@@ -875,30 +875,30 @@ smc_pxa_dma_irq(int dma, void *dummy)
875 875
876// Packet Number Register 876// Packet Number Register
877/* BANK 2 */ 877/* BANK 2 */
878#define PN_REG SMC_REG(0x0002, 2) 878#define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
879 879
880 880
881// Allocation Result Register 881// Allocation Result Register
882/* BANK 2 */ 882/* BANK 2 */
883#define AR_REG SMC_REG(0x0003, 2) 883#define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
884#define AR_FAILED 0x80 // Alocation Failed 884#define AR_FAILED 0x80 // Alocation Failed
885 885
886 886
887// TX FIFO Ports Register 887// TX FIFO Ports Register
888/* BANK 2 */ 888/* BANK 2 */
889#define TXFIFO_REG SMC_REG(0x0004, 2) 889#define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
890#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty 890#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
891 891
892// RX FIFO Ports Register 892// RX FIFO Ports Register
893/* BANK 2 */ 893/* BANK 2 */
894#define RXFIFO_REG SMC_REG(0x0005, 2) 894#define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
895#define RXFIFO_REMPTY 0x80 // RX FIFO Empty 895#define RXFIFO_REMPTY 0x80 // RX FIFO Empty
896 896
897#define FIFO_REG SMC_REG(0x0004, 2) 897#define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
898 898
899// Pointer Register 899// Pointer Register
900/* BANK 2 */ 900/* BANK 2 */
901#define PTR_REG SMC_REG(0x0006, 2) 901#define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
902#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area 902#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
903#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access 903#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
904#define PTR_READ 0x2000 // When 1 the operation is a read 904#define PTR_READ 0x2000 // When 1 the operation is a read
@@ -906,17 +906,17 @@ smc_pxa_dma_irq(int dma, void *dummy)
906 906
907// Data Register 907// Data Register
908/* BANK 2 */ 908/* BANK 2 */
909#define DATA_REG SMC_REG(0x0008, 2) 909#define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
910 910
911 911
912// Interrupt Status/Acknowledge Register 912// Interrupt Status/Acknowledge Register
913/* BANK 2 */ 913/* BANK 2 */
914#define INT_REG SMC_REG(0x000C, 2) 914#define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
915 915
916 916
917// Interrupt Mask Register 917// Interrupt Mask Register
918/* BANK 2 */ 918/* BANK 2 */
919#define IM_REG SMC_REG(0x000D, 2) 919#define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
920#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt 920#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
921#define IM_ERCV_INT 0x40 // Early Receive Interrupt 921#define IM_ERCV_INT 0x40 // Early Receive Interrupt
922#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section 922#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
@@ -929,15 +929,15 @@ smc_pxa_dma_irq(int dma, void *dummy)
929 929
930// Multicast Table Registers 930// Multicast Table Registers
931/* BANK 3 */ 931/* BANK 3 */
932#define MCAST_REG1 SMC_REG(0x0000, 3) 932#define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
933#define MCAST_REG2 SMC_REG(0x0002, 3) 933#define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
934#define MCAST_REG3 SMC_REG(0x0004, 3) 934#define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
935#define MCAST_REG4 SMC_REG(0x0006, 3) 935#define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
936 936
937 937
938// Management Interface Register (MII) 938// Management Interface Register (MII)
939/* BANK 3 */ 939/* BANK 3 */
940#define MII_REG SMC_REG(0x0008, 3) 940#define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
941#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup 941#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
942#define MII_MDOE 0x0008 // MII Output Enable 942#define MII_MDOE 0x0008 // MII Output Enable
943#define MII_MCLK 0x0004 // MII Clock, pin MDCLK 943#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
@@ -948,20 +948,20 @@ smc_pxa_dma_irq(int dma, void *dummy)
948// Revision Register 948// Revision Register
949/* BANK 3 */ 949/* BANK 3 */
950/* ( hi: chip id low: rev # ) */ 950/* ( hi: chip id low: rev # ) */
951#define REV_REG SMC_REG(0x000A, 3) 951#define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
952 952
953 953
954// Early RCV Register 954// Early RCV Register
955/* BANK 3 */ 955/* BANK 3 */
956/* this is NOT on SMC9192 */ 956/* this is NOT on SMC9192 */
957#define ERCV_REG SMC_REG(0x000C, 3) 957#define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
958#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received 958#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
959#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask 959#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
960 960
961 961
962// External Register 962// External Register
963/* BANK 7 */ 963/* BANK 7 */
964#define EXT_REG SMC_REG(0x0000, 7) 964#define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
965 965
966 966
967#define CHIP_9192 3 967#define CHIP_9192 3
@@ -1085,9 +1085,9 @@ static const char * chip_ids[ 16 ] = {
1085 */ 1085 */
1086 1086
1087#if SMC_DEBUG > 0 1087#if SMC_DEBUG > 0
1088#define SMC_REG(reg, bank) \ 1088#define SMC_REG(lp, reg, bank) \
1089 ({ \ 1089 ({ \
1090 int __b = SMC_CURRENT_BANK(); \ 1090 int __b = SMC_CURRENT_BANK(lp); \
1091 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ 1091 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1092 printk( "%s: bank reg screwed (0x%04x)\n", \ 1092 printk( "%s: bank reg screwed (0x%04x)\n", \
1093 CARDNAME, __b ); \ 1093 CARDNAME, __b ); \
@@ -1096,7 +1096,7 @@ static const char * chip_ids[ 16 ] = {
1096 reg<<SMC_IO_SHIFT; \ 1096 reg<<SMC_IO_SHIFT; \
1097 }) 1097 })
1098#else 1098#else
1099#define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT) 1099#define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
1100#endif 1100#endif
1101 1101
1102/* 1102/*
@@ -1110,65 +1110,65 @@ static const char * chip_ids[ 16 ] = {
1110 */ 1110 */
1111#define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT 1111#define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
1112 1112
1113#define SMC_GET_PN() \ 1113#define SMC_GET_PN(lp) \
1114 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \ 1114 (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG(lp))) \
1115 : (SMC_inw(ioaddr, PN_REG) & 0xFF) ) 1115 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
1116 1116
1117#define SMC_SET_PN(x) \ 1117#define SMC_SET_PN(lp, x) \
1118 do { \ 1118 do { \
1119 if (SMC_MUST_ALIGN_WRITE) \ 1119 if (SMC_MUST_ALIGN_WRITE) \
1120 SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \ 1120 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
1121 else if (SMC_CAN_USE_8BIT) \ 1121 else if (SMC_CAN_USE_8BIT) \
1122 SMC_outb(x, ioaddr, PN_REG); \ 1122 SMC_outb(x, ioaddr, PN_REG(lp)); \
1123 else \ 1123 else \
1124 SMC_outw(x, ioaddr, PN_REG); \ 1124 SMC_outw(x, ioaddr, PN_REG(lp)); \
1125 } while (0) 1125 } while (0)
1126 1126
1127#define SMC_GET_AR() \ 1127#define SMC_GET_AR(lp) \
1128 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \ 1128 (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG(lp))) \
1129 : (SMC_inw(ioaddr, PN_REG) >> 8) ) 1129 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
1130 1130
1131#define SMC_GET_TXFIFO() \ 1131#define SMC_GET_TXFIFO(lp) \
1132 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \ 1132 (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
1133 : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) ) 1133 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
1134 1134
1135#define SMC_GET_RXFIFO() \ 1135#define SMC_GET_RXFIFO(lp) \
1136 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \ 1136 (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
1137 : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) ) 1137 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
1138 1138
1139#define SMC_GET_INT() \ 1139#define SMC_GET_INT(lp) \
1140 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \ 1140 (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG(lp))) \
1141 : (SMC_inw(ioaddr, INT_REG) & 0xFF) ) 1141 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
1142 1142
1143#define SMC_ACK_INT(x) \ 1143#define SMC_ACK_INT(lp, x) \
1144 do { \ 1144 do { \
1145 if (SMC_CAN_USE_8BIT) \ 1145 if (SMC_CAN_USE_8BIT) \
1146 SMC_outb(x, ioaddr, INT_REG); \ 1146 SMC_outb(x, ioaddr, INT_REG(lp)); \
1147 else { \ 1147 else { \
1148 unsigned long __flags; \ 1148 unsigned long __flags; \
1149 int __mask; \ 1149 int __mask; \
1150 local_irq_save(__flags); \ 1150 local_irq_save(__flags); \
1151 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \ 1151 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1152 SMC_outw( __mask | (x), ioaddr, INT_REG ); \ 1152 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
1153 local_irq_restore(__flags); \ 1153 local_irq_restore(__flags); \
1154 } \ 1154 } \
1155 } while (0) 1155 } while (0)
1156 1156
1157#define SMC_GET_INT_MASK() \ 1157#define SMC_GET_INT_MASK(lp) \
1158 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \ 1158 (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG(lp))) \
1159 : (SMC_inw( ioaddr, INT_REG ) >> 8) ) 1159 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
1160 1160
1161#define SMC_SET_INT_MASK(x) \ 1161#define SMC_SET_INT_MASK(lp, x) \
1162 do { \ 1162 do { \
1163 if (SMC_CAN_USE_8BIT) \ 1163 if (SMC_CAN_USE_8BIT) \
1164 SMC_outb(x, ioaddr, IM_REG); \ 1164 SMC_outb(x, ioaddr, IM_REG(lp)); \
1165 else \ 1165 else \
1166 SMC_outw((x) << 8, ioaddr, INT_REG); \ 1166 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
1167 } while (0) 1167 } while (0)
1168 1168
1169#define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT) 1169#define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
1170 1170
1171#define SMC_SELECT_BANK(x) \ 1171#define SMC_SELECT_BANK(lp, x) \
1172 do { \ 1172 do { \
1173 if (SMC_MUST_ALIGN_WRITE) \ 1173 if (SMC_MUST_ALIGN_WRITE) \
1174 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \ 1174 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
@@ -1176,118 +1176,119 @@ static const char * chip_ids[ 16 ] = {
1176 SMC_outw(x, ioaddr, BANK_SELECT); \ 1176 SMC_outw(x, ioaddr, BANK_SELECT); \
1177 } while (0) 1177 } while (0)
1178 1178
1179#define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG) 1179#define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
1180 1180
1181#define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG) 1181#define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
1182 1182
1183#define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG) 1183#define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
1184 1184
1185#define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG) 1185#define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
1186 1186
1187#define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG) 1187#define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
1188 1188
1189#define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG) 1189#define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
1190 1190
1191#define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG) 1191#define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
1192 1192
1193#define SMC_GET_MII() SMC_inw(ioaddr, MII_REG) 1193#define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
1194 1194
1195#define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG) 1195#define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
1196 1196
1197#define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG) 1197#define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
1198 1198
1199#define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG) 1199#define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
1200 1200
1201#define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG) 1201#define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
1202 1202
1203#define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG) 1203#define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1204 1204
1205#define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG) 1205#define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
1206 1206
1207#define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG) 1207#define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
1208 1208
1209#define SMC_SET_PTR(x) \ 1209#define SMC_SET_PTR(lp, x) \
1210 do { \ 1210 do { \
1211 if (SMC_MUST_ALIGN_WRITE) \ 1211 if (SMC_MUST_ALIGN_WRITE) \
1212 SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \ 1212 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1213 else \ 1213 else \
1214 SMC_outw(x, ioaddr, PTR_REG); \ 1214 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1215 } while (0) 1215 } while (0)
1216 1216
1217#define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG) 1217#define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1218 1218
1219#define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG) 1219#define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1220 1220
1221#define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG) 1221#define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
1222 1222
1223#define SMC_GET_REV() SMC_inw(ioaddr, REV_REG) 1223#define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1224 1224
1225#define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG) 1225#define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1226 1226
1227#define SMC_SET_RPC(x) \ 1227#define SMC_SET_RPC(lp, x) \
1228 do { \ 1228 do { \
1229 if (SMC_MUST_ALIGN_WRITE) \ 1229 if (SMC_MUST_ALIGN_WRITE) \
1230 SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \ 1230 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1231 else \ 1231 else \
1232 SMC_outw(x, ioaddr, RPC_REG); \ 1232 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1233 } while (0) 1233 } while (0)
1234 1234
1235#define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG) 1235#define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1236 1236
1237#define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG) 1237#define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1238 1238
1239#ifndef SMC_GET_MAC_ADDR 1239#ifndef SMC_GET_MAC_ADDR
1240#define SMC_GET_MAC_ADDR(addr) \ 1240#define SMC_GET_MAC_ADDR(lp, addr) \
1241 do { \ 1241 do { \
1242 unsigned int __v; \ 1242 unsigned int __v; \
1243 __v = SMC_inw( ioaddr, ADDR0_REG ); \ 1243 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1244 addr[0] = __v; addr[1] = __v >> 8; \ 1244 addr[0] = __v; addr[1] = __v >> 8; \
1245 __v = SMC_inw( ioaddr, ADDR1_REG ); \ 1245 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1246 addr[2] = __v; addr[3] = __v >> 8; \ 1246 addr[2] = __v; addr[3] = __v >> 8; \
1247 __v = SMC_inw( ioaddr, ADDR2_REG ); \ 1247 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1248 addr[4] = __v; addr[5] = __v >> 8; \ 1248 addr[4] = __v; addr[5] = __v >> 8; \
1249 } while (0) 1249 } while (0)
1250#endif 1250#endif
1251 1251
1252#define SMC_SET_MAC_ADDR(addr) \ 1252#define SMC_SET_MAC_ADDR(lp, addr) \
1253 do { \ 1253 do { \
1254 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \ 1254 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1255 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \ 1255 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1256 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \ 1256 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1257 } while (0) 1257 } while (0)
1258 1258
1259#define SMC_SET_MCAST(x) \ 1259#define SMC_SET_MCAST(lp, x) \
1260 do { \ 1260 do { \
1261 const unsigned char *mt = (x); \ 1261 const unsigned char *mt = (x); \
1262 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \ 1262 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1263 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \ 1263 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1264 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \ 1264 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1265 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \ 1265 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1266 } while (0) 1266 } while (0)
1267 1267
1268#define SMC_PUT_PKT_HDR(status, length) \ 1268#define SMC_PUT_PKT_HDR(lp, status, length) \
1269 do { \ 1269 do { \
1270 if (SMC_CAN_USE_32BIT) \ 1270 if (SMC_CAN_USE_32BIT) \
1271 SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \ 1271 SMC_outl((status) | (length)<<16, ioaddr, \
1272 DATA_REG(lp)); \
1272 else { \ 1273 else { \
1273 SMC_outw(status, ioaddr, DATA_REG); \ 1274 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1274 SMC_outw(length, ioaddr, DATA_REG); \ 1275 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1275 } \ 1276 } \
1276 } while (0) 1277 } while (0)
1277 1278
1278#define SMC_GET_PKT_HDR(status, length) \ 1279#define SMC_GET_PKT_HDR(lp, status, length) \
1279 do { \ 1280 do { \
1280 if (SMC_CAN_USE_32BIT) { \ 1281 if (SMC_CAN_USE_32BIT) { \
1281 unsigned int __val = SMC_inl(ioaddr, DATA_REG); \ 1282 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1282 (status) = __val & 0xffff; \ 1283 (status) = __val & 0xffff; \
1283 (length) = __val >> 16; \ 1284 (length) = __val >> 16; \
1284 } else { \ 1285 } else { \
1285 (status) = SMC_inw(ioaddr, DATA_REG); \ 1286 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1286 (length) = SMC_inw(ioaddr, DATA_REG); \ 1287 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1287 } \ 1288 } \
1288 } while (0) 1289 } while (0)
1289 1290
1290#define SMC_PUSH_DATA(p, l) \ 1291#define SMC_PUSH_DATA(lp, p, l) \
1291 do { \ 1292 do { \
1292 if (SMC_CAN_USE_32BIT) { \ 1293 if (SMC_CAN_USE_32BIT) { \
1293 void *__ptr = (p); \ 1294 void *__ptr = (p); \
@@ -1295,23 +1296,25 @@ static const char * chip_ids[ 16 ] = {
1295 void __iomem *__ioaddr = ioaddr; \ 1296 void __iomem *__ioaddr = ioaddr; \
1296 if (__len >= 2 && (unsigned long)__ptr & 2) { \ 1297 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1297 __len -= 2; \ 1298 __len -= 2; \
1298 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \ 1299 SMC_outw(*(u16 *)__ptr, ioaddr, \
1300 DATA_REG(lp)); \
1299 __ptr += 2; \ 1301 __ptr += 2; \
1300 } \ 1302 } \
1301 if (SMC_CAN_USE_DATACS && lp->datacs) \ 1303 if (SMC_CAN_USE_DATACS && lp->datacs) \
1302 __ioaddr = lp->datacs; \ 1304 __ioaddr = lp->datacs; \
1303 SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \ 1305 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1304 if (__len & 2) { \ 1306 if (__len & 2) { \
1305 __ptr += (__len & ~3); \ 1307 __ptr += (__len & ~3); \
1306 SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \ 1308 SMC_outw(*((u16 *)__ptr), ioaddr, \
1309 DATA_REG(lp)); \
1307 } \ 1310 } \
1308 } else if (SMC_CAN_USE_16BIT) \ 1311 } else if (SMC_CAN_USE_16BIT) \
1309 SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \ 1312 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1310 else if (SMC_CAN_USE_8BIT) \ 1313 else if (SMC_CAN_USE_8BIT) \
1311 SMC_outsb(ioaddr, DATA_REG, p, l); \ 1314 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1312 } while (0) 1315 } while (0)
1313 1316
1314#define SMC_PULL_DATA(p, l) \ 1317#define SMC_PULL_DATA(lp, p, l) \
1315 do { \ 1318 do { \
1316 if (SMC_CAN_USE_32BIT) { \ 1319 if (SMC_CAN_USE_32BIT) { \
1317 void *__ptr = (p); \ 1320 void *__ptr = (p); \
@@ -1333,16 +1336,17 @@ static const char * chip_ids[ 16 ] = {
1333 */ \ 1336 */ \
1334 __ptr -= 2; \ 1337 __ptr -= 2; \
1335 __len += 2; \ 1338 __len += 2; \
1336 SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \ 1339 SMC_SET_PTR(lp, \
1340 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1337 } \ 1341 } \
1338 if (SMC_CAN_USE_DATACS && lp->datacs) \ 1342 if (SMC_CAN_USE_DATACS && lp->datacs) \
1339 __ioaddr = lp->datacs; \ 1343 __ioaddr = lp->datacs; \
1340 __len += 2; \ 1344 __len += 2; \
1341 SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \ 1345 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1342 } else if (SMC_CAN_USE_16BIT) \ 1346 } else if (SMC_CAN_USE_16BIT) \
1343 SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \ 1347 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1344 else if (SMC_CAN_USE_8BIT) \ 1348 else if (SMC_CAN_USE_8BIT) \
1345 SMC_insb(ioaddr, DATA_REG, p, l); \ 1349 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1346 } while (0) 1350 } while (0)
1347 1351
1348#endif /* _SMC91X_H_ */ 1352#endif /* _SMC91X_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 08:19:33 -0400