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path: root/drivers/net/smc911x.h
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-rw-r--r--drivers/net/smc911x.h494
1 files changed, 278 insertions, 216 deletions
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index 7defa63b9c74..76c17c28fab4 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -29,6 +29,7 @@
29#ifndef _SMC911X_H_ 29#ifndef _SMC911X_H_
30#define _SMC911X_H_ 30#define _SMC911X_H_
31 31
32#include <linux/smc911x.h>
32/* 33/*
33 * Use the DMA feature on PXA chips 34 * Use the DMA feature on PXA chips
34 */ 35 */
@@ -38,42 +39,160 @@
38 #define SMC_USE_32BIT 1 39 #define SMC_USE_32BIT 1
39 #define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING 40 #define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING
40#elif defined(CONFIG_SH_MAGIC_PANEL_R2) 41#elif defined(CONFIG_SH_MAGIC_PANEL_R2)
41 #define SMC_USE_SH_DMA 0
42 #define SMC_USE_16BIT 0 42 #define SMC_USE_16BIT 0
43 #define SMC_USE_32BIT 1 43 #define SMC_USE_32BIT 1
44 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW 44 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
45#else
46/*
47 * Default configuration
48 */
49
50#define SMC_DYNAMIC_BUS_CONFIG
45#endif 51#endif
46 52
53/* store this information for the driver.. */
54struct smc911x_local {
55 /*
56 * If I have to wait until the DMA is finished and ready to reload a
57 * packet, I will store the skbuff here. Then, the DMA will send it
58 * out and free it.
59 */
60 struct sk_buff *pending_tx_skb;
61
62 /* version/revision of the SMC911x chip */
63 u16 version;
64 u16 revision;
65
66 /* FIFO sizes */
67 int tx_fifo_kb;
68 int tx_fifo_size;
69 int rx_fifo_size;
70 int afc_cfg;
71
72 /* Contains the current active receive/phy mode */
73 int ctl_rfduplx;
74 int ctl_rspeed;
75
76 u32 msg_enable;
77 u32 phy_type;
78 struct mii_if_info mii;
79
80 /* work queue */
81 struct work_struct phy_configure;
82
83 int tx_throttle;
84 spinlock_t lock;
85
86 struct net_device *netdev;
87
88#ifdef SMC_USE_DMA
89 /* DMA needs the physical address of the chip */
90 u_long physaddr;
91 int rxdma;
92 int txdma;
93 int rxdma_active;
94 int txdma_active;
95 struct sk_buff *current_rx_skb;
96 struct sk_buff *current_tx_skb;
97 struct device *dev;
98#endif
99 void __iomem *base;
100#ifdef SMC_DYNAMIC_BUS_CONFIG
101 struct smc911x_platdata cfg;
102#endif
103};
47 104
48/* 105/*
49 * Define the bus width specific IO macros 106 * Define the bus width specific IO macros
50 */ 107 */
51 108
109#ifdef SMC_DYNAMIC_BUS_CONFIG
110static inline unsigned int SMC_inl(struct smc911x_local *lp, int reg)
111{
112 void __iomem *ioaddr = lp->base + reg;
113
114 if (lp->cfg.flags & SMC911X_USE_32BIT)
115 return readl(ioaddr);
116
117 if (lp->cfg.flags & SMC911X_USE_16BIT)
118 return readw(ioaddr) | (readw(ioaddr + 2) << 16);
119
120 BUG();
121}
122
123static inline void SMC_outl(unsigned int value, struct smc911x_local *lp,
124 int reg)
125{
126 void __iomem *ioaddr = lp->base + reg;
127
128 if (lp->cfg.flags & SMC911X_USE_32BIT) {
129 writel(value, ioaddr);
130 return;
131 }
132
133 if (lp->cfg.flags & SMC911X_USE_16BIT) {
134 writew(value & 0xffff, ioaddr);
135 writew(value >> 16, ioaddr + 2);
136 return;
137 }
138
139 BUG();
140}
141
142static inline void SMC_insl(struct smc911x_local *lp, int reg,
143 void *addr, unsigned int count)
144{
145 void __iomem *ioaddr = lp->base + reg;
146
147 if (lp->cfg.flags & SMC911X_USE_32BIT) {
148 readsl(ioaddr, addr, count);
149 return;
150 }
151
152 if (lp->cfg.flags & SMC911X_USE_16BIT) {
153 readsw(ioaddr, addr, count * 2);
154 return;
155 }
156
157 BUG();
158}
159
160static inline void SMC_outsl(struct smc911x_local *lp, int reg,
161 void *addr, unsigned int count)
162{
163 void __iomem *ioaddr = lp->base + reg;
164
165 if (lp->cfg.flags & SMC911X_USE_32BIT) {
166 writesl(ioaddr, addr, count);
167 return;
168 }
169
170 if (lp->cfg.flags & SMC911X_USE_16BIT) {
171 writesw(ioaddr, addr, count * 2);
172 return;
173 }
174
175 BUG();
176}
177#else
52#if SMC_USE_16BIT 178#if SMC_USE_16BIT
53#define SMC_inb(a, r) readb((a) + (r)) 179#define SMC_inl(lp, r) ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))
54#define SMC_inw(a, r) readw((a) + (r)) 180#define SMC_outl(v, lp, r) \
55#define SMC_inl(a, r) ((SMC_inw(a, r) & 0xFFFF)+(SMC_inw(a+2, r)<<16))
56#define SMC_outb(v, a, r) writeb(v, (a) + (r))
57#define SMC_outw(v, a, r) writew(v, (a) + (r))
58#define SMC_outl(v, a, r) \
59 do{ \ 181 do{ \
60 writel(v & 0xFFFF, (a) + (r)); \ 182 writew(v & 0xFFFF, (lp)->base + (r)); \
61 writel(v >> 16, (a) + (r) + 2); \ 183 writew(v >> 16, (lp)->base + (r) + 2); \
62 } while (0) 184 } while (0)
63#define SMC_insl(a, r, p, l) readsw((short*)((a) + (r)), p, l*2) 185#define SMC_insl(lp, r, p, l) readsw((short*)((lp)->base + (r)), p, l*2)
64#define SMC_outsl(a, r, p, l) writesw((short*)((a) + (r)), p, l*2) 186#define SMC_outsl(lp, r, p, l) writesw((short*)((lp)->base + (r)), p, l*2)
65 187
66#elif SMC_USE_32BIT 188#elif SMC_USE_32BIT
67#define SMC_inb(a, r) readb((a) + (r)) 189#define SMC_inl(lp, r) readl((lp)->base + (r))
68#define SMC_inw(a, r) readw((a) + (r)) 190#define SMC_outl(v, lp, r) writel(v, (lp)->base + (r))
69#define SMC_inl(a, r) readl((a) + (r)) 191#define SMC_insl(lp, r, p, l) readsl((int*)((lp)->base + (r)), p, l)
70#define SMC_outb(v, a, r) writeb(v, (a) + (r)) 192#define SMC_outsl(lp, r, p, l) writesl((int*)((lp)->base + (r)), p, l)
71#define SMC_outl(v, a, r) writel(v, (a) + (r))
72#define SMC_insl(a, r, p, l) readsl((int*)((a) + (r)), p, l)
73#define SMC_outsl(a, r, p, l) writesl((int*)((a) + (r)), p, l)
74 193
75#endif /* SMC_USE_16BIT */ 194#endif /* SMC_USE_16BIT */
76 195#endif /* SMC_DYNAMIC_BUS_CONFIG */
77 196
78 197
79#ifdef SMC_USE_PXA_DMA 198#ifdef SMC_USE_PXA_DMA
@@ -110,22 +229,22 @@ static int rx_dmalen, tx_dmalen;
110 229
111#ifdef SMC_insl 230#ifdef SMC_insl
112#undef SMC_insl 231#undef SMC_insl
113#define SMC_insl(a, r, p, l) \ 232#define SMC_insl(lp, r, p, l) \
114 smc_pxa_dma_insl(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l) 233 smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
115 234
116static inline void 235static inline void
117smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr, 236smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,
118 int reg, int dma, u_char *buf, int len) 237 int reg, int dma, u_char *buf, int len)
119{ 238{
120 /* 64 bit alignment is required for memory to memory DMA */ 239 /* 64 bit alignment is required for memory to memory DMA */
121 if ((long)buf & 4) { 240 if ((long)buf & 4) {
122 *((u32 *)buf) = SMC_inl(ioaddr, reg); 241 *((u32 *)buf) = SMC_inl(lp, reg);
123 buf += 4; 242 buf += 4;
124 len--; 243 len--;
125 } 244 }
126 245
127 len *= 4; 246 len *= 4;
128 rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE); 247 rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);
129 rx_dmalen = len; 248 rx_dmalen = len;
130 DCSR(dma) = DCSR_NODESC; 249 DCSR(dma) = DCSR_NODESC;
131 DTADR(dma) = rx_dmabuf; 250 DTADR(dma) = rx_dmabuf;
@@ -136,52 +255,24 @@ smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr,
136} 255}
137#endif 256#endif
138 257
139#ifdef SMC_insw
140#undef SMC_insw
141#define SMC_insw(a, r, p, l) \
142 smc_pxa_dma_insw(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
143
144static inline void
145smc_pxa_dma_insw(struct device *dev, u_long ioaddr, u_long physaddr,
146 int reg, int dma, u_char *buf, int len)
147{
148 /* 64 bit alignment is required for memory to memory DMA */
149 while ((long)buf & 6) {
150 *((u16 *)buf) = SMC_inw(ioaddr, reg);
151 buf += 2;
152 len--;
153 }
154
155 len *= 2;
156 rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
157 rx_dmalen = len;
158 DCSR(dma) = DCSR_NODESC;
159 DTADR(dma) = rx_dmabuf;
160 DSADR(dma) = physaddr + reg;
161 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
162 DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
163 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
164}
165#endif
166
167#ifdef SMC_outsl 258#ifdef SMC_outsl
168#undef SMC_outsl 259#undef SMC_outsl
169#define SMC_outsl(a, r, p, l) \ 260#define SMC_outsl(lp, r, p, l) \
170 smc_pxa_dma_outsl(lp->dev, a, lp->physaddr, r, lp->txdma, p, l) 261 smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
171 262
172static inline void 263static inline void
173smc_pxa_dma_outsl(struct device *dev, u_long ioaddr, u_long physaddr, 264smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,
174 int reg, int dma, u_char *buf, int len) 265 int reg, int dma, u_char *buf, int len)
175{ 266{
176 /* 64 bit alignment is required for memory to memory DMA */ 267 /* 64 bit alignment is required for memory to memory DMA */
177 if ((long)buf & 4) { 268 if ((long)buf & 4) {
178 SMC_outl(*((u32 *)buf), ioaddr, reg); 269 SMC_outl(*((u32 *)buf), lp, reg);
179 buf += 4; 270 buf += 4;
180 len--; 271 len--;
181 } 272 }
182 273
183 len *= 4; 274 len *= 4;
184 tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE); 275 tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);
185 tx_dmalen = len; 276 tx_dmalen = len;
186 DCSR(dma) = DCSR_NODESC; 277 DCSR(dma) = DCSR_NODESC;
187 DSADR(dma) = tx_dmabuf; 278 DSADR(dma) = tx_dmabuf;
@@ -191,35 +282,6 @@ smc_pxa_dma_outsl(struct device *dev, u_long ioaddr, u_long physaddr,
191 DCSR(dma) = DCSR_NODESC | DCSR_RUN; 282 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
192} 283}
193#endif 284#endif
194
195#ifdef SMC_outsw
196#undef SMC_outsw
197#define SMC_outsw(a, r, p, l) \
198 smc_pxa_dma_outsw(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
199
200static inline void
201smc_pxa_dma_outsw(struct device *dev, u_long ioaddr, u_long physaddr,
202 int reg, int dma, u_char *buf, int len)
203{
204 /* 64 bit alignment is required for memory to memory DMA */
205 while ((long)buf & 6) {
206 SMC_outw(*((u16 *)buf), ioaddr, reg);
207 buf += 2;
208 len--;
209 }
210
211 len *= 2;
212 tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
213 tx_dmalen = len;
214 DCSR(dma) = DCSR_NODESC;
215 DSADR(dma) = tx_dmabuf;
216 DTADR(dma) = physaddr + reg;
217 DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
218 DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
219 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
220}
221#endif
222
223#endif /* SMC_USE_PXA_DMA */ 285#endif /* SMC_USE_PXA_DMA */
224 286
225 287
@@ -629,213 +691,213 @@ static const struct chip_id chip_ids[] = {
629 * capabilities. Please use those and not the in/out primitives. 691 * capabilities. Please use those and not the in/out primitives.
630 */ 692 */
631/* FIFO read/write macros */ 693/* FIFO read/write macros */
632#define SMC_PUSH_DATA(p, l) SMC_outsl( ioaddr, TX_DATA_FIFO, p, (l) >> 2 ) 694#define SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )
633#define SMC_PULL_DATA(p, l) SMC_insl ( ioaddr, RX_DATA_FIFO, p, (l) >> 2 ) 695#define SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )
634#define SMC_SET_TX_FIFO(x) SMC_outl( x, ioaddr, TX_DATA_FIFO ) 696#define SMC_SET_TX_FIFO(lp, x) SMC_outl( x, lp, TX_DATA_FIFO )
635#define SMC_GET_RX_FIFO() SMC_inl( ioaddr, RX_DATA_FIFO ) 697#define SMC_GET_RX_FIFO(lp) SMC_inl( lp, RX_DATA_FIFO )
636 698
637 699
638/* I/O mapped register read/write macros */ 700/* I/O mapped register read/write macros */
639#define SMC_GET_TX_STS_FIFO() SMC_inl( ioaddr, TX_STATUS_FIFO ) 701#define SMC_GET_TX_STS_FIFO(lp) SMC_inl( lp, TX_STATUS_FIFO )
640#define SMC_GET_RX_STS_FIFO() SMC_inl( ioaddr, RX_STATUS_FIFO ) 702#define SMC_GET_RX_STS_FIFO(lp) SMC_inl( lp, RX_STATUS_FIFO )
641#define SMC_GET_RX_STS_FIFO_PEEK() SMC_inl( ioaddr, RX_STATUS_FIFO_PEEK ) 703#define SMC_GET_RX_STS_FIFO_PEEK(lp) SMC_inl( lp, RX_STATUS_FIFO_PEEK )
642#define SMC_GET_PN() (SMC_inl( ioaddr, ID_REV ) >> 16) 704#define SMC_GET_PN(lp) (SMC_inl( lp, ID_REV ) >> 16)
643#define SMC_GET_REV() (SMC_inl( ioaddr, ID_REV ) & 0xFFFF) 705#define SMC_GET_REV(lp) (SMC_inl( lp, ID_REV ) & 0xFFFF)
644#define SMC_GET_IRQ_CFG() SMC_inl( ioaddr, INT_CFG ) 706#define SMC_GET_IRQ_CFG(lp) SMC_inl( lp, INT_CFG )
645#define SMC_SET_IRQ_CFG(x) SMC_outl( x, ioaddr, INT_CFG ) 707#define SMC_SET_IRQ_CFG(lp, x) SMC_outl( x, lp, INT_CFG )
646#define SMC_GET_INT() SMC_inl( ioaddr, INT_STS ) 708#define SMC_GET_INT(lp) SMC_inl( lp, INT_STS )
647#define SMC_ACK_INT(x) SMC_outl( x, ioaddr, INT_STS ) 709#define SMC_ACK_INT(lp, x) SMC_outl( x, lp, INT_STS )
648#define SMC_GET_INT_EN() SMC_inl( ioaddr, INT_EN ) 710#define SMC_GET_INT_EN(lp) SMC_inl( lp, INT_EN )
649#define SMC_SET_INT_EN(x) SMC_outl( x, ioaddr, INT_EN ) 711#define SMC_SET_INT_EN(lp, x) SMC_outl( x, lp, INT_EN )
650#define SMC_GET_BYTE_TEST() SMC_inl( ioaddr, BYTE_TEST ) 712#define SMC_GET_BYTE_TEST(lp) SMC_inl( lp, BYTE_TEST )
651#define SMC_SET_BYTE_TEST(x) SMC_outl( x, ioaddr, BYTE_TEST ) 713#define SMC_SET_BYTE_TEST(lp, x) SMC_outl( x, lp, BYTE_TEST )
652#define SMC_GET_FIFO_INT() SMC_inl( ioaddr, FIFO_INT ) 714#define SMC_GET_FIFO_INT(lp) SMC_inl( lp, FIFO_INT )
653#define SMC_SET_FIFO_INT(x) SMC_outl( x, ioaddr, FIFO_INT ) 715#define SMC_SET_FIFO_INT(lp, x) SMC_outl( x, lp, FIFO_INT )
654#define SMC_SET_FIFO_TDA(x) \ 716#define SMC_SET_FIFO_TDA(lp, x) \
655 do { \ 717 do { \
656 unsigned long __flags; \ 718 unsigned long __flags; \
657 int __mask; \ 719 int __mask; \
658 local_irq_save(__flags); \ 720 local_irq_save(__flags); \
659 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<24); \ 721 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24); \
660 SMC_SET_FIFO_INT( __mask | (x)<<24 ); \ 722 SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 ); \
661 local_irq_restore(__flags); \ 723 local_irq_restore(__flags); \
662 } while (0) 724 } while (0)
663#define SMC_SET_FIFO_TSL(x) \ 725#define SMC_SET_FIFO_TSL(lp, x) \
664 do { \ 726 do { \
665 unsigned long __flags; \ 727 unsigned long __flags; \
666 int __mask; \ 728 int __mask; \
667 local_irq_save(__flags); \ 729 local_irq_save(__flags); \
668 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<16); \ 730 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16); \
669 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<16)); \ 731 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16)); \
670 local_irq_restore(__flags); \ 732 local_irq_restore(__flags); \
671 } while (0) 733 } while (0)
672#define SMC_SET_FIFO_RSA(x) \ 734#define SMC_SET_FIFO_RSA(lp, x) \
673 do { \ 735 do { \
674 unsigned long __flags; \ 736 unsigned long __flags; \
675 int __mask; \ 737 int __mask; \
676 local_irq_save(__flags); \ 738 local_irq_save(__flags); \
677 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<8); \ 739 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8); \
678 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<8)); \ 740 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8)); \
679 local_irq_restore(__flags); \ 741 local_irq_restore(__flags); \
680 } while (0) 742 } while (0)
681#define SMC_SET_FIFO_RSL(x) \ 743#define SMC_SET_FIFO_RSL(lp, x) \
682 do { \ 744 do { \
683 unsigned long __flags; \ 745 unsigned long __flags; \
684 int __mask; \ 746 int __mask; \
685 local_irq_save(__flags); \ 747 local_irq_save(__flags); \
686 __mask = SMC_GET_FIFO_INT() & ~0xFF; \ 748 __mask = SMC_GET_FIFO_INT((lp)) & ~0xFF; \
687 SMC_SET_FIFO_INT( __mask | ((x) & 0xFF)); \ 749 SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF)); \
688 local_irq_restore(__flags); \ 750 local_irq_restore(__flags); \
689 } while (0) 751 } while (0)
690#define SMC_GET_RX_CFG() SMC_inl( ioaddr, RX_CFG ) 752#define SMC_GET_RX_CFG(lp) SMC_inl( lp, RX_CFG )
691#define SMC_SET_RX_CFG(x) SMC_outl( x, ioaddr, RX_CFG ) 753#define SMC_SET_RX_CFG(lp, x) SMC_outl( x, lp, RX_CFG )
692#define SMC_GET_TX_CFG() SMC_inl( ioaddr, TX_CFG ) 754#define SMC_GET_TX_CFG(lp) SMC_inl( lp, TX_CFG )
693#define SMC_SET_TX_CFG(x) SMC_outl( x, ioaddr, TX_CFG ) 755#define SMC_SET_TX_CFG(lp, x) SMC_outl( x, lp, TX_CFG )
694#define SMC_GET_HW_CFG() SMC_inl( ioaddr, HW_CFG ) 756#define SMC_GET_HW_CFG(lp) SMC_inl( lp, HW_CFG )
695#define SMC_SET_HW_CFG(x) SMC_outl( x, ioaddr, HW_CFG ) 757#define SMC_SET_HW_CFG(lp, x) SMC_outl( x, lp, HW_CFG )
696#define SMC_GET_RX_DP_CTRL() SMC_inl( ioaddr, RX_DP_CTRL ) 758#define SMC_GET_RX_DP_CTRL(lp) SMC_inl( lp, RX_DP_CTRL )
697#define SMC_SET_RX_DP_CTRL(x) SMC_outl( x, ioaddr, RX_DP_CTRL ) 759#define SMC_SET_RX_DP_CTRL(lp, x) SMC_outl( x, lp, RX_DP_CTRL )
698#define SMC_GET_PMT_CTRL() SMC_inl( ioaddr, PMT_CTRL ) 760#define SMC_GET_PMT_CTRL(lp) SMC_inl( lp, PMT_CTRL )
699#define SMC_SET_PMT_CTRL(x) SMC_outl( x, ioaddr, PMT_CTRL ) 761#define SMC_SET_PMT_CTRL(lp, x) SMC_outl( x, lp, PMT_CTRL )
700#define SMC_GET_GPIO_CFG() SMC_inl( ioaddr, GPIO_CFG ) 762#define SMC_GET_GPIO_CFG(lp) SMC_inl( lp, GPIO_CFG )
701#define SMC_SET_GPIO_CFG(x) SMC_outl( x, ioaddr, GPIO_CFG ) 763#define SMC_SET_GPIO_CFG(lp, x) SMC_outl( x, lp, GPIO_CFG )
702#define SMC_GET_RX_FIFO_INF() SMC_inl( ioaddr, RX_FIFO_INF ) 764#define SMC_GET_RX_FIFO_INF(lp) SMC_inl( lp, RX_FIFO_INF )
703#define SMC_SET_RX_FIFO_INF(x) SMC_outl( x, ioaddr, RX_FIFO_INF ) 765#define SMC_SET_RX_FIFO_INF(lp, x) SMC_outl( x, lp, RX_FIFO_INF )
704#define SMC_GET_TX_FIFO_INF() SMC_inl( ioaddr, TX_FIFO_INF ) 766#define SMC_GET_TX_FIFO_INF(lp) SMC_inl( lp, TX_FIFO_INF )
705#define SMC_SET_TX_FIFO_INF(x) SMC_outl( x, ioaddr, TX_FIFO_INF ) 767#define SMC_SET_TX_FIFO_INF(lp, x) SMC_outl( x, lp, TX_FIFO_INF )
706#define SMC_GET_GPT_CFG() SMC_inl( ioaddr, GPT_CFG ) 768#define SMC_GET_GPT_CFG(lp) SMC_inl( lp, GPT_CFG )
707#define SMC_SET_GPT_CFG(x) SMC_outl( x, ioaddr, GPT_CFG ) 769#define SMC_SET_GPT_CFG(lp, x) SMC_outl( x, lp, GPT_CFG )
708#define SMC_GET_RX_DROP() SMC_inl( ioaddr, RX_DROP ) 770#define SMC_GET_RX_DROP(lp) SMC_inl( lp, RX_DROP )
709#define SMC_SET_RX_DROP(x) SMC_outl( x, ioaddr, RX_DROP ) 771#define SMC_SET_RX_DROP(lp, x) SMC_outl( x, lp, RX_DROP )
710#define SMC_GET_MAC_CMD() SMC_inl( ioaddr, MAC_CSR_CMD ) 772#define SMC_GET_MAC_CMD(lp) SMC_inl( lp, MAC_CSR_CMD )
711#define SMC_SET_MAC_CMD(x) SMC_outl( x, ioaddr, MAC_CSR_CMD ) 773#define SMC_SET_MAC_CMD(lp, x) SMC_outl( x, lp, MAC_CSR_CMD )
712#define SMC_GET_MAC_DATA() SMC_inl( ioaddr, MAC_CSR_DATA ) 774#define SMC_GET_MAC_DATA(lp) SMC_inl( lp, MAC_CSR_DATA )
713#define SMC_SET_MAC_DATA(x) SMC_outl( x, ioaddr, MAC_CSR_DATA ) 775#define SMC_SET_MAC_DATA(lp, x) SMC_outl( x, lp, MAC_CSR_DATA )
714#define SMC_GET_AFC_CFG() SMC_inl( ioaddr, AFC_CFG ) 776#define SMC_GET_AFC_CFG(lp) SMC_inl( lp, AFC_CFG )
715#define SMC_SET_AFC_CFG(x) SMC_outl( x, ioaddr, AFC_CFG ) 777#define SMC_SET_AFC_CFG(lp, x) SMC_outl( x, lp, AFC_CFG )
716#define SMC_GET_E2P_CMD() SMC_inl( ioaddr, E2P_CMD ) 778#define SMC_GET_E2P_CMD(lp) SMC_inl( lp, E2P_CMD )
717#define SMC_SET_E2P_CMD(x) SMC_outl( x, ioaddr, E2P_CMD ) 779#define SMC_SET_E2P_CMD(lp, x) SMC_outl( x, lp, E2P_CMD )
718#define SMC_GET_E2P_DATA() SMC_inl( ioaddr, E2P_DATA ) 780#define SMC_GET_E2P_DATA(lp) SMC_inl( lp, E2P_DATA )
719#define SMC_SET_E2P_DATA(x) SMC_outl( x, ioaddr, E2P_DATA ) 781#define SMC_SET_E2P_DATA(lp, x) SMC_outl( x, lp, E2P_DATA )
720 782
721/* MAC register read/write macros */ 783/* MAC register read/write macros */
722#define SMC_GET_MAC_CSR(a,v) \ 784#define SMC_GET_MAC_CSR(lp,a,v) \
723 do { \ 785 do { \
724 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 786 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
725 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | \ 787 SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ | \
726 MAC_CSR_CMD_R_NOT_W_ | (a) ); \ 788 MAC_CSR_CMD_R_NOT_W_ | (a) ); \
727 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 789 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
728 v = SMC_GET_MAC_DATA(); \ 790 v = SMC_GET_MAC_DATA((lp)); \
729 } while (0) 791 } while (0)
730#define SMC_SET_MAC_CSR(a,v) \ 792#define SMC_SET_MAC_CSR(lp,a,v) \
731 do { \ 793 do { \
732 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 794 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
733 SMC_SET_MAC_DATA(v); \ 795 SMC_SET_MAC_DATA((lp), v); \
734 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | (a) ); \ 796 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) ); \
735 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 797 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
736 } while (0) 798 } while (0)
737#define SMC_GET_MAC_CR(x) SMC_GET_MAC_CSR( MAC_CR, x ) 799#define SMC_GET_MAC_CR(lp, x) SMC_GET_MAC_CSR( (lp), MAC_CR, x )
738#define SMC_SET_MAC_CR(x) SMC_SET_MAC_CSR( MAC_CR, x ) 800#define SMC_SET_MAC_CR(lp, x) SMC_SET_MAC_CSR( (lp), MAC_CR, x )
739#define SMC_GET_ADDRH(x) SMC_GET_MAC_CSR( ADDRH, x ) 801#define SMC_GET_ADDRH(lp, x) SMC_GET_MAC_CSR( (lp), ADDRH, x )
740#define SMC_SET_ADDRH(x) SMC_SET_MAC_CSR( ADDRH, x ) 802#define SMC_SET_ADDRH(lp, x) SMC_SET_MAC_CSR( (lp), ADDRH, x )
741#define SMC_GET_ADDRL(x) SMC_GET_MAC_CSR( ADDRL, x ) 803#define SMC_GET_ADDRL(lp, x) SMC_GET_MAC_CSR( (lp), ADDRL, x )
742#define SMC_SET_ADDRL(x) SMC_SET_MAC_CSR( ADDRL, x ) 804#define SMC_SET_ADDRL(lp, x) SMC_SET_MAC_CSR( (lp), ADDRL, x )
743#define SMC_GET_HASHH(x) SMC_GET_MAC_CSR( HASHH, x ) 805#define SMC_GET_HASHH(lp, x) SMC_GET_MAC_CSR( (lp), HASHH, x )
744#define SMC_SET_HASHH(x) SMC_SET_MAC_CSR( HASHH, x ) 806#define SMC_SET_HASHH(lp, x) SMC_SET_MAC_CSR( (lp), HASHH, x )
745#define SMC_GET_HASHL(x) SMC_GET_MAC_CSR( HASHL, x ) 807#define SMC_GET_HASHL(lp, x) SMC_GET_MAC_CSR( (lp), HASHL, x )
746#define SMC_SET_HASHL(x) SMC_SET_MAC_CSR( HASHL, x ) 808#define SMC_SET_HASHL(lp, x) SMC_SET_MAC_CSR( (lp), HASHL, x )
747#define SMC_GET_MII_ACC(x) SMC_GET_MAC_CSR( MII_ACC, x ) 809#define SMC_GET_MII_ACC(lp, x) SMC_GET_MAC_CSR( (lp), MII_ACC, x )
748#define SMC_SET_MII_ACC(x) SMC_SET_MAC_CSR( MII_ACC, x ) 810#define SMC_SET_MII_ACC(lp, x) SMC_SET_MAC_CSR( (lp), MII_ACC, x )
749#define SMC_GET_MII_DATA(x) SMC_GET_MAC_CSR( MII_DATA, x ) 811#define SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x )
750#define SMC_SET_MII_DATA(x) SMC_SET_MAC_CSR( MII_DATA, x ) 812#define SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x )
751#define SMC_GET_FLOW(x) SMC_GET_MAC_CSR( FLOW, x ) 813#define SMC_GET_FLOW(lp, x) SMC_GET_MAC_CSR( (lp), FLOW, x )
752#define SMC_SET_FLOW(x) SMC_SET_MAC_CSR( FLOW, x ) 814#define SMC_SET_FLOW(lp, x) SMC_SET_MAC_CSR( (lp), FLOW, x )
753#define SMC_GET_VLAN1(x) SMC_GET_MAC_CSR( VLAN1, x ) 815#define SMC_GET_VLAN1(lp, x) SMC_GET_MAC_CSR( (lp), VLAN1, x )
754#define SMC_SET_VLAN1(x) SMC_SET_MAC_CSR( VLAN1, x ) 816#define SMC_SET_VLAN1(lp, x) SMC_SET_MAC_CSR( (lp), VLAN1, x )
755#define SMC_GET_VLAN2(x) SMC_GET_MAC_CSR( VLAN2, x ) 817#define SMC_GET_VLAN2(lp, x) SMC_GET_MAC_CSR( (lp), VLAN2, x )
756#define SMC_SET_VLAN2(x) SMC_SET_MAC_CSR( VLAN2, x ) 818#define SMC_SET_VLAN2(lp, x) SMC_SET_MAC_CSR( (lp), VLAN2, x )
757#define SMC_SET_WUFF(x) SMC_SET_MAC_CSR( WUFF, x ) 819#define SMC_SET_WUFF(lp, x) SMC_SET_MAC_CSR( (lp), WUFF, x )
758#define SMC_GET_WUCSR(x) SMC_GET_MAC_CSR( WUCSR, x ) 820#define SMC_GET_WUCSR(lp, x) SMC_GET_MAC_CSR( (lp), WUCSR, x )
759#define SMC_SET_WUCSR(x) SMC_SET_MAC_CSR( WUCSR, x ) 821#define SMC_SET_WUCSR(lp, x) SMC_SET_MAC_CSR( (lp), WUCSR, x )
760 822
761/* PHY register read/write macros */ 823/* PHY register read/write macros */
762#define SMC_GET_MII(a,phy,v) \ 824#define SMC_GET_MII(lp,a,phy,v) \
763 do { \ 825 do { \
764 u32 __v; \ 826 u32 __v; \
765 do { \ 827 do { \
766 SMC_GET_MII_ACC(__v); \ 828 SMC_GET_MII_ACC((lp), __v); \
767 } while ( __v & MII_ACC_MII_BUSY_ ); \ 829 } while ( __v & MII_ACC_MII_BUSY_ ); \
768 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \ 830 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
769 MII_ACC_MII_BUSY_); \ 831 MII_ACC_MII_BUSY_); \
770 do { \ 832 do { \
771 SMC_GET_MII_ACC(__v); \ 833 SMC_GET_MII_ACC( (lp), __v); \
772 } while ( __v & MII_ACC_MII_BUSY_ ); \ 834 } while ( __v & MII_ACC_MII_BUSY_ ); \
773 SMC_GET_MII_DATA(v); \ 835 SMC_GET_MII_DATA((lp), v); \
774 } while (0) 836 } while (0)
775#define SMC_SET_MII(a,phy,v) \ 837#define SMC_SET_MII(lp,a,phy,v) \
776 do { \ 838 do { \
777 u32 __v; \ 839 u32 __v; \
778 do { \ 840 do { \
779 SMC_GET_MII_ACC(__v); \ 841 SMC_GET_MII_ACC((lp), __v); \
780 } while ( __v & MII_ACC_MII_BUSY_ ); \ 842 } while ( __v & MII_ACC_MII_BUSY_ ); \
781 SMC_SET_MII_DATA(v); \ 843 SMC_SET_MII_DATA((lp), v); \
782 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \ 844 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
783 MII_ACC_MII_BUSY_ | \ 845 MII_ACC_MII_BUSY_ | \
784 MII_ACC_MII_WRITE_ ); \ 846 MII_ACC_MII_WRITE_ ); \
785 do { \ 847 do { \
786 SMC_GET_MII_ACC(__v); \ 848 SMC_GET_MII_ACC((lp), __v); \
787 } while ( __v & MII_ACC_MII_BUSY_ ); \ 849 } while ( __v & MII_ACC_MII_BUSY_ ); \
788 } while (0) 850 } while (0)
789#define SMC_GET_PHY_BMCR(phy,x) SMC_GET_MII( MII_BMCR, phy, x ) 851#define SMC_GET_PHY_BMCR(lp,phy,x) SMC_GET_MII( (lp), MII_BMCR, phy, x )
790#define SMC_SET_PHY_BMCR(phy,x) SMC_SET_MII( MII_BMCR, phy, x ) 852#define SMC_SET_PHY_BMCR(lp,phy,x) SMC_SET_MII( (lp), MII_BMCR, phy, x )
791#define SMC_GET_PHY_BMSR(phy,x) SMC_GET_MII( MII_BMSR, phy, x ) 853#define SMC_GET_PHY_BMSR(lp,phy,x) SMC_GET_MII( (lp), MII_BMSR, phy, x )
792#define SMC_GET_PHY_ID1(phy,x) SMC_GET_MII( MII_PHYSID1, phy, x ) 854#define SMC_GET_PHY_ID1(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID1, phy, x )
793#define SMC_GET_PHY_ID2(phy,x) SMC_GET_MII( MII_PHYSID2, phy, x ) 855#define SMC_GET_PHY_ID2(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID2, phy, x )
794#define SMC_GET_PHY_MII_ADV(phy,x) SMC_GET_MII( MII_ADVERTISE, phy, x ) 856#define SMC_GET_PHY_MII_ADV(lp,phy,x) SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )
795#define SMC_SET_PHY_MII_ADV(phy,x) SMC_SET_MII( MII_ADVERTISE, phy, x ) 857#define SMC_SET_PHY_MII_ADV(lp,phy,x) SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )
796#define SMC_GET_PHY_MII_LPA(phy,x) SMC_GET_MII( MII_LPA, phy, x ) 858#define SMC_GET_PHY_MII_LPA(lp,phy,x) SMC_GET_MII( (lp), MII_LPA, phy, x )
797#define SMC_SET_PHY_MII_LPA(phy,x) SMC_SET_MII( MII_LPA, phy, x ) 859#define SMC_SET_PHY_MII_LPA(lp,phy,x) SMC_SET_MII( (lp), MII_LPA, phy, x )
798#define SMC_GET_PHY_CTRL_STS(phy,x) SMC_GET_MII( PHY_MODE_CTRL_STS, phy, x ) 860#define SMC_GET_PHY_CTRL_STS(lp,phy,x) SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
799#define SMC_SET_PHY_CTRL_STS(phy,x) SMC_SET_MII( PHY_MODE_CTRL_STS, phy, x ) 861#define SMC_SET_PHY_CTRL_STS(lp,phy,x) SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
800#define SMC_GET_PHY_INT_SRC(phy,x) SMC_GET_MII( PHY_INT_SRC, phy, x ) 862#define SMC_GET_PHY_INT_SRC(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )
801#define SMC_SET_PHY_INT_SRC(phy,x) SMC_SET_MII( PHY_INT_SRC, phy, x ) 863#define SMC_SET_PHY_INT_SRC(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )
802#define SMC_GET_PHY_INT_MASK(phy,x) SMC_GET_MII( PHY_INT_MASK, phy, x ) 864#define SMC_GET_PHY_INT_MASK(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )
803#define SMC_SET_PHY_INT_MASK(phy,x) SMC_SET_MII( PHY_INT_MASK, phy, x ) 865#define SMC_SET_PHY_INT_MASK(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )
804#define SMC_GET_PHY_SPECIAL(phy,x) SMC_GET_MII( PHY_SPECIAL, phy, x ) 866#define SMC_GET_PHY_SPECIAL(lp,phy,x) SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )
805 867
806 868
807 869
808/* Misc read/write macros */ 870/* Misc read/write macros */
809 871
810#ifndef SMC_GET_MAC_ADDR 872#ifndef SMC_GET_MAC_ADDR
811#define SMC_GET_MAC_ADDR(addr) \ 873#define SMC_GET_MAC_ADDR(lp, addr) \
812 do { \ 874 do { \
813 unsigned int __v; \ 875 unsigned int __v; \
814 \ 876 \
815 SMC_GET_MAC_CSR(ADDRL, __v); \ 877 SMC_GET_MAC_CSR((lp), ADDRL, __v); \
816 addr[0] = __v; addr[1] = __v >> 8; \ 878 addr[0] = __v; addr[1] = __v >> 8; \
817 addr[2] = __v >> 16; addr[3] = __v >> 24; \ 879 addr[2] = __v >> 16; addr[3] = __v >> 24; \
818 SMC_GET_MAC_CSR(ADDRH, __v); \ 880 SMC_GET_MAC_CSR((lp), ADDRH, __v); \
819 addr[4] = __v; addr[5] = __v >> 8; \ 881 addr[4] = __v; addr[5] = __v >> 8; \
820 } while (0) 882 } while (0)
821#endif 883#endif
822 884
823#define SMC_SET_MAC_ADDR(addr) \ 885#define SMC_SET_MAC_ADDR(lp, addr) \
824 do { \ 886 do { \
825 SMC_SET_MAC_CSR(ADDRL, \ 887 SMC_SET_MAC_CSR((lp), ADDRL, \
826 addr[0] | \ 888 addr[0] | \
827 (addr[1] << 8) | \ 889 (addr[1] << 8) | \
828 (addr[2] << 16) | \ 890 (addr[2] << 16) | \
829 (addr[3] << 24)); \ 891 (addr[3] << 24)); \
830 SMC_SET_MAC_CSR(ADDRH, addr[4]|(addr[5] << 8));\ 892 SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
831 } while (0) 893 } while (0)
832 894
833 895
834#define SMC_WRITE_EEPROM_CMD(cmd, addr) \ 896#define SMC_WRITE_EEPROM_CMD(lp, cmd, addr) \
835 do { \ 897 do { \
836 while (SMC_GET_E2P_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 898 while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
837 SMC_SET_MAC_CMD(MAC_CSR_CMD_R_NOT_W_ | a ); \ 899 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a ); \
838 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 900 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
839 } while (0) 901 } while (0)
840 902
841#endif /* _SMC911X_H_ */ 903#endif /* _SMC911X_H_ */
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