1 files changed, 23 insertions, 1 deletions

diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index c0a5eea20007..4d9c4a19bb85 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -28,6 +28,11 @@ enum pci_dev_reg_1 {
         PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
         PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
         PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
+
+        PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit  9.. 8:       GPHY Link Trigger Timer */
+        PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */
+        PCI_ENA_GPHY_LNK = 1<<6, /* Enable PEX L1 on GPHY Link down */
+        PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */
 };
 
 enum pci_dev_reg_2 {
@@ -45,7 +50,11 @@ enum pci_dev_reg_2 {
 
 /*      PCI_OUR_REG_4           32 bit  Our Register 4 (Yukon-ECU only) */
 enum pci_dev_reg_4 {
-                                        /* (Link Training & Status State Machine) */
+                                /* (Link Training & Status State Machine) */
+        P_PEX_LTSSM_STAT_MSK    = 0x7fL<<25,    /* Bit 31..25:  PEX LTSSM Mask */
+#define P_PEX_LTSSM_STAT(x)     ((x << 25) & P_PEX_LTSSM_STAT_MSK)
+        P_PEX_LTSSM_L1_STAT     = 0x34,
+        P_PEX_LTSSM_DET_STAT    = 0x01,
         P_TIMER_VALUE_MSK       = 0xffL<<16,    /* Bit 23..16:  Timer Value Mask */
                                         /* (Active State Power Management) */
         P_FORCE_ASPM_REQUEST    = 1<<15, /* Force ASPM Request (A1 only) */
@@ -432,6 +441,7 @@ enum {
         CHIP_ID_YUKON_FE   = 0xb7, /* YUKON-2 FE */
         CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */
         CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */
+        CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */
 };
 enum yukon_ec_rev {
         CHIP_REV_YU_EC_A1    = 0,  /* Chip Rev. for Yukon-EC A1/A0 */
@@ -454,6 +464,9 @@ enum yukon_ex_rev {
         CHIP_REV_YU_EX_A0    = 1,
         CHIP_REV_YU_EX_B0    = 2,
 };
+enum yukon_supr_rev {
+        CHIP_REV_YU_SU_A0    = 0,
+};
 
 
 /*      B2_Y2_CLK_GATE   8 bit  Clock Gating (Yukon-2 only) */
@@ -1143,6 +1156,12 @@ enum {
         PHY_M_PC_ENA_AUTO       = 3, /* 11 = Enable Automatic Crossover */
 };
 
+/* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
+enum {
+        PHY_M_PC_COP_TX_DIS     = 1<<3, /* Copper Transmitter Disable */
+        PHY_M_PC_POW_D_ENA      = 1<<2, /* Power Down Enable */
+};
+
 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
 enum {
         PHY_M_PC_ENA_DTE_DT     = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
@@ -1411,6 +1430,7 @@ enum {
 /*****  PHY_MARV_PHY_CTRL (page 2)              16 bit r/w      MAC Specific Ctrl *****/
 enum {
         PHY_M_MAC_MD_MSK        = 7<<7, /* Bit  9.. 7: Mode Select Mask */
+        PHY_M_MAC_GMIF_PUP      = 1<<3, /* GMII Power Up (88E1149 only) */
         PHY_M_MAC_MD_AUTO       = 3,/* Auto Copper/1000Base-X */
         PHY_M_MAC_MD_COPPER     = 5,/* Copper only */
         PHY_M_MAC_MD_1000BX     = 7,/* 1000Base-X only */
@@ -2052,7 +2072,9 @@ struct sky2_hw {
 #define SKY2_HW_NEW_LE          0x00000020      /* new LSOv2 format */
 #define SKY2_HW_AUTO_TX_SUM     0x00000040      /* new IP decode for Tx */
 #define SKY2_HW_ADV_POWER_CTL   0x00000080      /* additional PHY power regs */
+#define SKY2_HW_CLK_POWER       0x00000100      /* clock power management */
 
+        int                  pm_cap;
         u8                   chip_id;
         u8                   chip_rev;
         u8                   pmd_type;