1 files changed, 60 insertions, 25 deletions

diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index 6ed1d47dbbd3..3b0189569d52 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -32,6 +32,7 @@ enum pci_dev_reg_1 {
         PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
         PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
         PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
+        PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
 };
 
 enum pci_dev_reg_2 {
@@ -370,12 +371,9 @@ enum {
 
 /*      B2_CHIP_ID               8 bit  Chip Identification Number */
 enum {
-        CHIP_ID_GENESIS    = 0x0a, /* Chip ID for GENESIS */
-        CHIP_ID_YUKON      = 0xb0, /* Chip ID for YUKON */
-        CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
-        CHIP_ID_YUKON_LP   = 0xb2, /* Chip ID for YUKON-LP */
         CHIP_ID_YUKON_XL   = 0xb3, /* Chip ID for YUKON-2 XL */
         CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */
+        CHIP_ID_YUKON_EX   = 0xb5, /* Chip ID for YUKON-2 Extreme */
         CHIP_ID_YUKON_EC   = 0xb6, /* Chip ID for YUKON-2 EC */
         CHIP_ID_YUKON_FE   = 0xb7, /* Chip ID for YUKON-2 FE */
 
@@ -767,6 +765,24 @@ enum {
         POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit     Poll. List Start Addr (high) */
 };
 
+enum {
+        SMB_CFG          = 0x0e40, /* 32 bit    SMBus Config Register */
+        SMB_CSR          = 0x0e44, /* 32 bit    SMBus Control/Status Register */
+};
+
+enum {
+        CPU_WDOG         = 0x0e48, /* 32 bit    Watchdog Register  */
+        CPU_CNTR         = 0x0e4C, /* 32 bit    Counter Register  */
+        CPU_TIM          = 0x0e50,/* 32 bit     Timer Compare Register  */
+        CPU_AHB_ADDR     = 0x0e54, /* 32 bit    CPU AHB Debug  Register  */
+        CPU_AHB_WDATA    = 0x0e58, /* 32 bit    CPU AHB Debug  Register  */
+        CPU_AHB_RDATA    = 0x0e5C, /* 32 bit    CPU AHB Debug  Register  */
+        HCU_MAP_BASE     = 0x0e60, /* 32 bit    Reset Mapping Base */
+        CPU_AHB_CTRL     = 0x0e64, /* 32 bit    CPU AHB Debug  Register  */
+        HCU_CCSR         = 0x0e68, /* 32 bit    CPU Control and Status Register */
+        HCU_HCSR         = 0x0e6C, /* 32 bit    Host Control and Status Register */
+};
+
 /* ASF Subsystem Registers (Yukon-2 only) */
 enum {
         B28_Y2_SMB_CONFIG  = 0x0e40,/* 32 bit   ASF SMBus Config Register */
@@ -837,33 +853,27 @@ enum {
         GMAC_LINK_CTRL  = 0x0f10,/* 16 bit      Link Control Reg */
 
 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
-
-        WOL_REG_OFFS    = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
-
         WOL_CTRL_STAT   = 0x0f20,/* 16 bit      WOL Control/Status Reg */
         WOL_MATCH_CTL   = 0x0f22,/*  8 bit      WOL Match Control Reg */
         WOL_MATCH_RES   = 0x0f23,/*  8 bit      WOL Match Result Reg */
         WOL_MAC_ADDR    = 0x0f24,/* 32 bit      WOL MAC Address */
-        WOL_PATT_PME    = 0x0f2a,/*  8 bit      WOL PME Match Enable (Yukon-2) */
-        WOL_PATT_ASFM   = 0x0f2b,/*  8 bit      WOL ASF Match Enable (Yukon-2) */
         WOL_PATT_RPTR   = 0x0f2c,/*  8 bit      WOL Pattern Read Pointer */
 
 /* WOL Pattern Length Registers (YUKON only) */
-
         WOL_PATT_LEN_LO = 0x0f30,/* 32 bit      WOL Pattern Length 3..0 */
         WOL_PATT_LEN_HI = 0x0f34,/* 24 bit      WOL Pattern Length 6..4 */
 
 /* WOL Pattern Counter Registers (YUKON only) */
-
-
         WOL_PATT_CNT_0  = 0x0f38,/* 32 bit      WOL Pattern Counter 3..0 */
         WOL_PATT_CNT_4  = 0x0f3c,/* 24 bit      WOL Pattern Counter 6..4 */
 };
+#define WOL_REGS(port, x)       (x + (port)*0x80)
 
 enum {
         WOL_PATT_RAM_1  = 0x1000,/*  WOL Pattern RAM Link 1 */
         WOL_PATT_RAM_2  = 0x1400,/*  WOL Pattern RAM Link 2 */
 };
+#define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
 
 enum {
         BASE_GMAC_1     = 0x2800,/* GMAC 1 registers */
@@ -1654,6 +1664,39 @@ enum {
         Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
         Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
 };
+/*      HCU_CCSR        CPU Control and Status Register */
+enum {
+        HCU_CCSR_SMBALERT_MONITOR= 1<<27, /* SMBALERT pin monitor */
+        HCU_CCSR_CPU_SLEEP      = 1<<26, /* CPU sleep status */
+        /* Clock Stretching Timeout */
+        HCU_CCSR_CS_TO          = 1<<25,
+        HCU_CCSR_WDOG           = 1<<24, /* Watchdog Reset */
+
+        HCU_CCSR_CLR_IRQ_HOST   = 1<<17, /* Clear IRQ_HOST */
+        HCU_CCSR_SET_IRQ_HCU    = 1<<16, /* Set IRQ_HCU */
+
+        HCU_CCSR_AHB_RST        = 1<<9, /* Reset AHB bridge */
+        HCU_CCSR_CPU_RST_MODE   = 1<<8, /* CPU Reset Mode */
+
+        HCU_CCSR_SET_SYNC_CPU   = 1<<5,
+        HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3,/* CPU Clock Divide */
+        HCU_CCSR_CPU_CLK_DIVIDE_BASE= 1<<3,
+        HCU_CCSR_OS_PRSNT       = 1<<2, /* ASF OS Present */
+/* Microcontroller State */
+        HCU_CCSR_UC_STATE_MSK   = 3,
+        HCU_CCSR_UC_STATE_BASE  = 1<<0,
+        HCU_CCSR_ASF_RESET      = 0,
+        HCU_CCSR_ASF_HALTED     = 1<<1,
+        HCU_CCSR_ASF_RUNNING    = 1<<0,
+};
+
+/*      HCU_HCSR        Host Control and Status Register */
+enum {
+        HCU_HCSR_SET_IRQ_CPU    = 1<<16, /* Set IRQ_CPU */
+
+        HCU_HCSR_CLR_IRQ_HCU    = 1<<1, /* Clear IRQ_HCU */
+        HCU_HCSR_SET_IRQ_HOST   = 1<<0, /* Set IRQ_HOST */
+};
 
 /*      STAT_CTRL               32 bit  Status BMU control register (Yukon-2 only) */
 enum {
@@ -1715,14 +1758,17 @@ enum {
         GM_IS_RX_COMPL  = 1<<0, /* Frame Reception Complete */
 
 #define GMAC_DEF_MSK     GM_IS_TX_FF_UR
+};
 
 /*      GMAC_LINK_CTRL  16 bit  GMAC Link Control Reg (YUKON only) */
-                                                /* Bits 15.. 2: reserved */
+enum {                                          /* Bits 15.. 2: reserved */
         GMLC_RST_CLR    = 1<<1, /* Clear GMAC Link Reset */
         GMLC_RST_SET    = 1<<0, /* Set   GMAC Link Reset */
+};
 
 
 /*      WOL_CTRL_STAT   16 bit  WOL Control/Status Reg */
+enum {
         WOL_CTL_LINK_CHG_OCC            = 1<<15,
         WOL_CTL_MAGIC_PKT_OCC           = 1<<14,
         WOL_CTL_PATTERN_OCC             = 1<<13,
@@ -1741,17 +1787,6 @@ enum {
         WOL_CTL_DIS_PATTERN_UNIT        = 1<<0,
 };
 
-#define WOL_CTL_DEFAULT                         \
-        (WOL_CTL_DIS_PME_ON_LINK_CHG |  \
-        WOL_CTL_DIS_PME_ON_PATTERN |    \
-        WOL_CTL_DIS_PME_ON_MAGIC_PKT |  \
-        WOL_CTL_DIS_LINK_CHG_UNIT |             \
-        WOL_CTL_DIS_PATTERN_UNIT |              \
-        WOL_CTL_DIS_MAGIC_PKT_UNIT)
-
-/*      WOL_MATCH_CTL    8 bit  WOL Match Control Reg */
-#define WOL_CTL_PATT_ENA(x)     (1 << (x))
-
 
 /* Control flags */
 enum {
@@ -1875,6 +1910,7 @@ struct sky2_port {
         u8                   autoneg;   /* AUTONEG_ENABLE, AUTONEG_DISABLE */
         u8                   duplex;    /* DUPLEX_HALF, DUPLEX_FULL */
         u8                   rx_csum;
+        u8                   wol;
         enum flow_control    flow_mode;
         enum flow_control    flow_status;
 
@@ -1887,7 +1923,6 @@ struct sky2_hw {
         struct pci_dev       *pdev;
         struct net_device    *dev[2];
 
-        int                  pm_cap;
         u8                   chip_id;
         u8                   chip_rev;
         u8                   pmd_type;