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-rw-r--r--drivers/net/sky2.h1935
1 files changed, 1935 insertions, 0 deletions
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
new file mode 100644
index 000000000000..d2a0ac2c53e7
--- /dev/null
+++ b/drivers/net/sky2.h
@@ -0,0 +1,1935 @@
1/*
2 * Definitions for the new Marvell Yukon 2 driver.
3 */
4#ifndef _SKY2_H
5#define _SKY2_H
6
7/* PCI config registers */
8#define PCI_DEV_REG1 0x40
9#define PCI_DEV_REG2 0x44
10#define PCI_DEV_STATUS 0x7c
11#define PCI_OS_PCI_X (1<<26)
12
13#define PEX_LNK_STAT 0xf2
14#define PEX_UNC_ERR_STAT 0x104
15#define PEX_DEV_CTRL 0xe8
16
17/* Yukon-2 */
18enum pci_dev_reg_1 {
19 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
20 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
21 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
22 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
23 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
24 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
25};
26
27enum pci_dev_reg_2 {
28 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
29 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
30 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
31
32 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
33 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
34 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
35 PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
36
37 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
38};
39
40
41#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
42 PCI_STATUS_SIG_SYSTEM_ERROR | \
43 PCI_STATUS_REC_MASTER_ABORT | \
44 PCI_STATUS_REC_TARGET_ABORT | \
45 PCI_STATUS_PARITY)
46
47enum pex_dev_ctrl {
48 PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */
49 PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */
50 PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */
51 PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */
52 PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */
53 PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */
54 PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */
55 PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */
56 PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */
57 PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */
58 PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */
59};
60#define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK)
61
62/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
63enum pex_err {
64 PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */
65
66 PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */
67
68 PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */
69
70 PEX_COMP_TO = 1<<14, /* Completion Timeout */
71 PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */
72 PEX_POIS_TLP = 1<<12, /* Poisoned TLP */
73
74 PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */
75 PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P),
76};
77
78
79enum csr_regs {
80 B0_RAP = 0x0000,
81 B0_CTST = 0x0004,
82 B0_Y2LED = 0x0005,
83 B0_POWER_CTRL = 0x0007,
84 B0_ISRC = 0x0008,
85 B0_IMSK = 0x000c,
86 B0_HWE_ISRC = 0x0010,
87 B0_HWE_IMSK = 0x0014,
88 B0_SP_ISRC = 0x0018,
89 B0_XM1_IMSK = 0x0020,
90 B0_XM1_ISRC = 0x0028,
91 B0_XM1_PHY_ADDR = 0x0030,
92 B0_XM1_PHY_DATA = 0x0034,
93 B0_XM2_IMSK = 0x0040,
94 B0_XM2_ISRC = 0x0048,
95 B0_XM2_PHY_ADDR = 0x0050,
96 B0_XM2_PHY_DATA = 0x0054,
97 B0_R1_CSR = 0x0060,
98 B0_R2_CSR = 0x0064,
99 B0_XS1_CSR = 0x0068,
100 B0_XA1_CSR = 0x006c,
101 B0_XS2_CSR = 0x0070,
102 B0_XA2_CSR = 0x0074,
103
104 /* Special ISR registers (Yukon-2 only) */
105 B0_Y2_SP_ISRC2 = 0x001c,
106 B0_Y2_SP_ISRC3 = 0x0020,
107 B0_Y2_SP_EISR = 0x0024,
108 B0_Y2_SP_LISR = 0x0028,
109 B0_Y2_SP_ICR = 0x002c,
110
111 B2_MAC_1 = 0x0100,
112 B2_MAC_2 = 0x0108,
113 B2_MAC_3 = 0x0110,
114 B2_CONN_TYP = 0x0118,
115 B2_PMD_TYP = 0x0119,
116 B2_MAC_CFG = 0x011a,
117 B2_CHIP_ID = 0x011b,
118 B2_E_0 = 0x011c,
119 B2_E_1 = 0x011d,
120 B2_E_2 = 0x011e,
121 B2_Y2_CLK_GATE = 0x011d,
122 B2_Y2_HW_RES = 0x011e,
123 B2_E_3 = 0x011f,
124 B2_Y2_CLK_CTRL = 0x0120,
125 B2_LD_CTRL = 0x0128,
126 B2_LD_TEST = 0x0129,
127 B2_TI_INI = 0x0130,
128 B2_TI_VAL = 0x0134,
129 B2_TI_CTRL = 0x0138,
130 B2_TI_TEST = 0x0139,
131 B2_IRQM_INI = 0x0140,
132 B2_IRQM_VAL = 0x0144,
133 B2_IRQM_CTRL = 0x0148,
134 B2_IRQM_TEST = 0x0149,
135 B2_IRQM_MSK = 0x014c,
136 B2_IRQM_HWE_MSK = 0x0150,
137 B2_TST_CTRL1 = 0x0158,
138 B2_TST_CTRL2 = 0x0159,
139 B2_GP_IO = 0x015c,
140 B2_I2C_CTRL = 0x0160,
141 B2_I2C_DATA = 0x0164,
142 B2_I2C_IRQ = 0x0168,
143 B2_I2C_SW = 0x016c,
144 B2_BSC_INI = 0x0170,
145 B2_BSC_VAL = 0x0174,
146 B2_BSC_CTRL = 0x0178,
147 B2_BSC_STAT = 0x0179,
148 B2_BSC_TST = 0x017a,
149
150 B3_RAM_ADDR = 0x0180,
151 B3_RAM_DATA_LO = 0x0184,
152 B3_RAM_DATA_HI = 0x0188,
153
154/* RAM Interface Registers */
155/* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
156/*
157 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
158 * not usable in SW. Please notice these are NOT real timeouts, these are
159 * the number of qWords transferred continuously.
160 */
161#define RAM_BUFFER(port, reg) (reg | (port <<6))
162
163 B3_RI_WTO_R1 = 0x0190,
164 B3_RI_WTO_XA1 = 0x0191,
165 B3_RI_WTO_XS1 = 0x0192,
166 B3_RI_RTO_R1 = 0x0193,
167 B3_RI_RTO_XA1 = 0x0194,
168 B3_RI_RTO_XS1 = 0x0195,
169 B3_RI_WTO_R2 = 0x0196,
170 B3_RI_WTO_XA2 = 0x0197,
171 B3_RI_WTO_XS2 = 0x0198,
172 B3_RI_RTO_R2 = 0x0199,
173 B3_RI_RTO_XA2 = 0x019a,
174 B3_RI_RTO_XS2 = 0x019b,
175 B3_RI_TO_VAL = 0x019c,
176 B3_RI_CTRL = 0x01a0,
177 B3_RI_TEST = 0x01a2,
178 B3_MA_TOINI_RX1 = 0x01b0,
179 B3_MA_TOINI_RX2 = 0x01b1,
180 B3_MA_TOINI_TX1 = 0x01b2,
181 B3_MA_TOINI_TX2 = 0x01b3,
182 B3_MA_TOVAL_RX1 = 0x01b4,
183 B3_MA_TOVAL_RX2 = 0x01b5,
184 B3_MA_TOVAL_TX1 = 0x01b6,
185 B3_MA_TOVAL_TX2 = 0x01b7,
186 B3_MA_TO_CTRL = 0x01b8,
187 B3_MA_TO_TEST = 0x01ba,
188 B3_MA_RCINI_RX1 = 0x01c0,
189 B3_MA_RCINI_RX2 = 0x01c1,
190 B3_MA_RCINI_TX1 = 0x01c2,
191 B3_MA_RCINI_TX2 = 0x01c3,
192 B3_MA_RCVAL_RX1 = 0x01c4,
193 B3_MA_RCVAL_RX2 = 0x01c5,
194 B3_MA_RCVAL_TX1 = 0x01c6,
195 B3_MA_RCVAL_TX2 = 0x01c7,
196 B3_MA_RC_CTRL = 0x01c8,
197 B3_MA_RC_TEST = 0x01ca,
198 B3_PA_TOINI_RX1 = 0x01d0,
199 B3_PA_TOINI_RX2 = 0x01d4,
200 B3_PA_TOINI_TX1 = 0x01d8,
201 B3_PA_TOINI_TX2 = 0x01dc,
202 B3_PA_TOVAL_RX1 = 0x01e0,
203 B3_PA_TOVAL_RX2 = 0x01e4,
204 B3_PA_TOVAL_TX1 = 0x01e8,
205 B3_PA_TOVAL_TX2 = 0x01ec,
206 B3_PA_CTRL = 0x01f0,
207 B3_PA_TEST = 0x01f2,
208
209 Y2_CFG_SPC = 0x1c00,
210};
211
212/* Access pci config through board I/O */
213#define PCI_C(x) (Y2_CFG_SPC + (x))
214
215
216/* B0_CTST 16 bit Control/Status register */
217enum {
218 Y2_VMAIN_AVAIL = 1<<17, /* VMAIN available (YUKON-2 only) */
219 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
220 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
221 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
222 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
223 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
224 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
225 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
226
227 CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
228 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
229 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
230 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
231 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
232 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
233 CS_MRST_CLR = 1<<3, /* Clear Master reset */
234 CS_MRST_SET = 1<<2, /* Set Master reset */
235 CS_RST_CLR = 1<<1, /* Clear Software reset */
236 CS_RST_SET = 1, /* Set Software reset */
237
238/* B0_LED 8 Bit LED register */
239/* Bit 7.. 2: reserved */
240 LED_STAT_ON = 1<<1, /* Status LED on */
241 LED_STAT_OFF = 1, /* Status LED off */
242
243/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
244 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
245 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
246 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
247 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
248 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
249 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
250 PC_VCC_ON = 1<<1, /* Switch VCC On */
251 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
252};
253
254/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
255
256/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
257/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
258/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
259/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
260enum {
261 Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */
262 Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */
263 Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */
264
265 Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */
266 Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
267 Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */
268 Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */
269
270 Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */
271 Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
272 Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
273 Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
274 Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
275
276 Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
277 Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
278 Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
279 Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
280 Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
281
282 Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU |
283 Y2_IS_POLL_CHK | Y2_IS_TWSI_RDY |
284 Y2_IS_IRQ_SW | Y2_IS_TIMINT,
285 Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 |
286 Y2_IS_CHK_RX1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXS1,
287 Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 |
288 Y2_IS_CHK_RX2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_TXS2,
289};
290
291/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
292enum {
293 IS_ERR_MSK = 0x00003fff,/* All Error bits */
294
295 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
296 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
297 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
298 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
299 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
300 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
301 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
302 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
303 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
304 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
305 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
306 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
307 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
308 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
309};
310
311/* Hardware error interrupt mask for Yukon 2 */
312enum {
313 Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */
314 Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */
315 Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */
316 Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */
317 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
318 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
319 /* Link 2 */
320 Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */
321 Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */
322 Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
323 Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
324 Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
325 Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
326 /* Link 1 */
327 Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */
328 Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */
329 Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */
330 Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
331 Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
332 Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
333
334 Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
335 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
336 Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
337 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
338
339 Y2_HWE_ALL_MASK = Y2_IS_SENSOR | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
340 Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP |
341 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
342};
343
344/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
345enum {
346 DPT_START = 1<<1,
347 DPT_STOP = 1<<0,
348};
349
350/* B2_TST_CTRL1 8 bit Test Control Register 1 */
351enum {
352 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
353 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
354 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
355 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
356 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
357 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
358 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
359 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
360};
361
362/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
363enum {
364 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
365 /* Bit 3.. 2: reserved */
366 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
367 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
368};
369
370/* B2_CHIP_ID 8 bit Chip Identification Number */
371enum {
372 CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
373 CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
374 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
375 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
376 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
377 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
378 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
379
380 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
381 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
382 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
383};
384
385/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
386enum {
387 Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactiv (0 = activ) */
388 Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
389 Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
390 Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
391 Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactiv (0 = activ) */
392 Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
393 Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
394 Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
395};
396
397/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
398enum {
399 CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
400 CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */
401 CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */
402};
403#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
404#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
405
406
407/* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
408enum {
409 Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
410#define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
411 Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
412 Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
413#define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
414#define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
415 Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
416 Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
417};
418
419/* B2_TI_CTRL 8 bit Timer control */
420/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
421enum {
422 TIM_START = 1<<2, /* Start Timer */
423 TIM_STOP = 1<<1, /* Stop Timer */
424 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
425};
426
427/* B2_TI_TEST 8 Bit Timer Test */
428/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
429/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
430enum {
431 TIM_T_ON = 1<<2, /* Test mode on */
432 TIM_T_OFF = 1<<1, /* Test mode off */
433 TIM_T_STEP = 1<<0, /* Test step */
434};
435
436/* B3_RAM_ADDR 32 bit RAM Address, to read or write */
437 /* Bit 31..19: reserved */
438#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
439/* RAM Interface Registers */
440
441/* B3_RI_CTRL 16 bit RAM Iface Control Register */
442enum {
443 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
444 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
445
446 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
447 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
448};
449
450#define SK_RI_TO_53 36 /* RAM interface timeout */
451
452
453/* Port related registers FIFO, and Arbiter */
454#define SK_REG(port,reg) (((port)<<7)+(reg))
455
456/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
457/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
458/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
459/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
460/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
461
462#define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
463
464/* TXA_CTRL 8 bit Tx Arbiter Control Register */
465enum {
466 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
467 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
468 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
469 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
470 TXA_START_RC = 1<<3, /* Start sync Rate Control */
471 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
472 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
473 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
474};
475
476/*
477 * Bank 4 - 5
478 */
479/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
480enum {
481 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
482 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
483 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
484 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
485 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
486 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
487 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
488};
489
490
491enum {
492 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
493 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
494 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
495 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
496 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
497 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
498 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
499 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
500 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
501};
502
503/* Queue Register Offsets, use Q_ADDR() to access */
504enum {
505 B8_Q_REGS = 0x0400, /* base of Queue registers */
506 Q_D = 0x00, /* 8*32 bit Current Descriptor */
507 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
508 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
509 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
510 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
511 Q_BC = 0x30, /* 32 bit Current Byte Counter */
512 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
513 Q_F = 0x38, /* 32 bit Flag Register */
514 Q_T1 = 0x3c, /* 32 bit Test Register 1 */
515 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
516 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
517 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
518 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
519 Q_T2 = 0x40, /* 32 bit Test Register 2 */
520 Q_T3 = 0x44, /* 32 bit Test Register 3 */
521
522/* Yukon-2 */
523 Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
524 Q_WM = 0x40, /* 16 bit FIFO Watermark */
525 Q_AL = 0x42, /* 8 bit FIFO Alignment */
526 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
527 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
528 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
529 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
530 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
531 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
532 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
533 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
534};
535#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
536
537
538/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
539enum {
540 Y2_B8_PREF_REGS = 0x0450,
541
542 PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
543 PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
544 PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
545 PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
546 PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
547 PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
548 PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
549 PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
550 PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
551 PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
552
553 PREF_UNIT_MASK_IDX = 0x0fff,
554};
555#define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
556
557/* RAM Buffer Register Offsets */
558enum {
559
560 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
561 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
562 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
563 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
564 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
565 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
566 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
567 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
568 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
569 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
570 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
571 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
572 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
573 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
574};
575
576/* Receive and Transmit Queues */
577enum {
578 Q_R1 = 0x0000, /* Receive Queue 1 */
579 Q_R2 = 0x0080, /* Receive Queue 2 */
580 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
581 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
582 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
583 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
584};
585
586/* Different PHY Types */
587enum {
588 PHY_ADDR_MARV = 0,
589};
590
591#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
592
593
594enum {
595 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
596 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
597 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
598 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
599
600 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
601
602/* Receive GMAC FIFO (YUKON and Yukon-2) */
603
604 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
605 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
606 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
607 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
608 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
609 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
610
611 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
612 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
613
614 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
615
616 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
617
618 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
619};
620
621
622/* Q_BC 32 bit Current Byte Counter */
623
624/* BMU Control Status Registers */
625/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
626/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
627/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
628/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
629/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
630/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
631/* Q_CSR 32 bit BMU Control/Status Register */
632
633/* Rx BMU Control / Status Registers (Yukon-2) */
634enum {
635 BMU_IDLE = 1<<31, /* BMU Idle State */
636 BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
637 BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
638
639 BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
640 BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
641 BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
642 BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
643 BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
644 BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segmen. error (Tx) */
645 BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
646 BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
647 BMU_START = 1<<8, /* Start Rx/Tx Queue */
648 BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */
649 BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
650 BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
651 BMU_FIFO_RST = 1<<4, /* Reset FIFO */
652 BMU_OP_ON = 1<<3, /* BMU Operational On */
653 BMU_OP_OFF = 1<<2, /* BMU Operational Off */
654 BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
655 BMU_RST_SET = 1<<0, /* Set BMU Reset */
656
657 BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
658 BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
659 BMU_FIFO_ENA | BMU_OP_ON,
660};
661
662/* Tx BMU Control / Status Registers (Yukon-2) */
663 /* Bit 31: same as for Rx */
664enum {
665 BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
666 BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
667 BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segm. length mism. */
668};
669
670/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
671/* PREF_UNIT_CTRL 32 bit Prefetch Control register */
672enum {
673 PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */
674 PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */
675 PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */
676 PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */
677};
678
679/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
680/* RB_START 32 bit RAM Buffer Start Address */
681/* RB_END 32 bit RAM Buffer End Address */
682/* RB_WP 32 bit RAM Buffer Write Pointer */
683/* RB_RP 32 bit RAM Buffer Read Pointer */
684/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
685/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
686/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
687/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
688/* RB_PC 32 bit RAM Buffer Packet Counter */
689/* RB_LEV 32 bit RAM Buffer Level Register */
690
691#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
692/* RB_TST2 8 bit RAM Buffer Test Register 2 */
693/* RB_TST1 8 bit RAM Buffer Test Register 1 */
694
695/* RB_CTRL 8 bit RAM Buffer Control Register */
696enum {
697 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
698 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
699 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
700 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
701 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
702 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
703};
704
705
706/* Transmit GMAC FIFO (YUKON only) */
707enum {
708 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
709 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
710 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
711
712 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
713 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
714 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
715
716 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
717 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
718 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
719};
720
721/* Descriptor Poll Timer Registers */
722enum {
723 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
724 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
725 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
726
727 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
728};
729
730/* Time Stamp Timer Registers (YUKON only) */
731enum {
732 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
733 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
734 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
735};
736
737/* Polling Unit Registers (Yukon-2 only) */
738enum {
739 POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
740 POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
741
742 POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
743 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
744};
745
746/* ASF Subsystem Registers (Yukon-2 only) */
747enum {
748 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
749 B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
750 B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
751
752 B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
753 B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
754 B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
755 B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
756 B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
757 B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
758};
759
760/* Status BMU Registers (Yukon-2 only)*/
761enum {
762 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
763 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
764
765 STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
766 STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
767 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
768 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
769 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
770 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
771 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
772 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
773
774/* FIFO Control/Status Registers (Yukon-2 only)*/
775 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
776 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
777 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
778 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
779 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
780 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
781 STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
782
783/* Level and ISR Timer Registers (Yukon-2 only)*/
784 STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
785 STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
786 STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
787 STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
788 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
789 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
790 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
791 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
792 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
793 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
794 STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
795 STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
796
797 ST_LAST_IDX_MASK = 0x007f,/* Last Index Mask */
798 ST_TXRP_IDX_MASK = 0x0fff,/* Tx Report Index Mask */
799 ST_TXTH_IDX_MASK = 0x0fff,/* Tx Threshold Index Mask */
800 ST_WM_IDX_MASK = 0x3f,/* FIFO Watermark Index Mask */
801};
802
803enum {
804 LINKLED_OFF = 0x01,
805 LINKLED_ON = 0x02,
806 LINKLED_LINKSYNC_OFF = 0x04,
807 LINKLED_LINKSYNC_ON = 0x08,
808 LINKLED_BLINK_OFF = 0x10,
809 LINKLED_BLINK_ON = 0x20,
810};
811
812/* GMAC and GPHY Control Registers (YUKON only) */
813enum {
814 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
815 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
816 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
817 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
818 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
819
820/* Wake-up Frame Pattern Match Control Registers (YUKON only) */
821
822 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
823
824 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
825 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
826 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
827 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
828 WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
829 WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
830 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
831
832/* WOL Pattern Length Registers (YUKON only) */
833
834 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
835 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
836
837/* WOL Pattern Counter Registers (YUKON only) */
838
839 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
840 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
841};
842
843enum {
844 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
845 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
846};
847
848enum {
849 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
850 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
851};
852
853/*
854 * Marvel-PHY Registers, indirect addressed over GMAC
855 */
856enum {
857 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
858 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
859 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
860 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
861 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
862 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
863 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
864 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
865 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
866 /* Marvel-specific registers */
867 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
868 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
869 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
870 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
871 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
872 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
873 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
874 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
875 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
876 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
877 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
878 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
879 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
880 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
881 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
882 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
883 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
884 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
885
886/* for 10/100 Fast Ethernet PHY (88E3082 only) */
887 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
888 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
889 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
890 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
891 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
892};
893
894enum {
895 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
896 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
897 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
898 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
899 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
900 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
901 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
902 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
903 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
904 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
905};
906
907enum {
908 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
909 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
910 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
911};
912
913enum {
914 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
915
916 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
917 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
918 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
919 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
920 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
921 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
922 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
923};
924
925enum {
926 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
927 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
928 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
929};
930
931/* different Marvell PHY Ids */
932enum {
933 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
934
935 PHY_BCOM_ID1_A1 = 0x6041,
936 PHY_BCOM_ID1_B2 = 0x6043,
937 PHY_BCOM_ID1_C0 = 0x6044,
938 PHY_BCOM_ID1_C5 = 0x6047,
939
940 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
941 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
942 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
943 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
944};
945
946/* Advertisement register bits */
947enum {
948 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
949 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
950 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
951
952 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
953 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
954 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
955 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
956 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
957 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
958 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
959 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
960 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
961 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
962 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
963 PHY_AN_100HALF | PHY_AN_100FULL,
964};
965
966/***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
967/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
968enum {
969 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
970 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
971 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
972 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
973 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
974 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
975 /* Bit 9..8: reserved */
976 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
977};
978
979/** Marvell-Specific */
980enum {
981 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
982 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
983 PHY_M_AN_RF = 1<<13, /* Remote Fault */
984
985 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
986 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
987 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
988 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
989 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
990 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
991 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
992 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
993};
994
995/* special defines for FIBER (88E1011S only) */
996enum {
997 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
998 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
999 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1000 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1001};
1002
1003/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1004enum {
1005 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1006 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1007 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1008 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1009};
1010
1011/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1012enum {
1013 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1014 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1015 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1016 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1017 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1018 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1019};
1020
1021/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1022enum {
1023 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1024 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1025 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1026 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1027 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1028 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1029 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1030 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1031 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1032 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1033 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1034 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1035};
1036
1037enum {
1038 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1039 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1040};
1041
1042#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
1043
1044enum {
1045 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1046 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1047 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1048};
1049
1050/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1051enum {
1052 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1053 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1054 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1055 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1056 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1057
1058 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1059 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1060
1061 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1062 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1063};
1064
1065/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1066enum {
1067 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1068 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1069 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1070 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1071 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1072 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1073 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1074 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1075 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1076 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1077 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1078 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1079 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1080 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1081 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1082 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1083};
1084
1085#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1086
1087/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1088enum {
1089 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1090 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1091};
1092
1093enum {
1094 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1095 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1096 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1097 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1098 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1099 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1100 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1101 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1102 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1103 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1104 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1105 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1106
1107 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1108 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1109 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1110
1111 PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
1112 | PHY_M_IS_FIFO_ERROR,
1113 PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1114};
1115
1116
1117/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1118enum {
1119 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1120 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1121
1122 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1123 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1124 /* (88E1011 only) */
1125 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
1126 /* (88E1011 only) */
1127 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1128 /* (88E1111 only) */
1129 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1130 /* !!! Errata in spec. (1 = disable) */
1131 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1132 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
1133 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1134 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1135 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1136 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1137
1138#define PHY_M_EC_M_DSC(x) ((x)<<10 & PHY_M_EC_M_DSC_MSK)
1139 /* 00=1x; 01=2x; 10=3x; 11=4x */
1140#define PHY_M_EC_S_DSC(x) ((x)<<8 & PHY_M_EC_S_DSC_MSK)
1141 /* 00=dis; 01=1x; 10=2x; 11=3x */
1142#define PHY_M_EC_DSC_2(x) ((x)<<9 & PHY_M_EC_M_DSC_MSK2)
1143 /* 000=1x; 001=2x; 010=3x; 011=4x */
1144#define PHY_M_EC_MAC_S(x) ((x)<<4 & PHY_M_EC_MAC_S_MSK)
1145 /* 01X=0; 110=2.5; 111=25 (MHz) */
1146
1147/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1148enum {
1149 PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */
1150 PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */
1151 PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
1152};
1153/* !!! Errata in spec. (1 = disable) */
1154
1155#define PHY_M_PC_DSC(x) (((x)<<12) & PHY_M_PC_DSC_MSK)
1156 /* 100=5x; 101=6x; 110=7x; 111=8x */
1157enum {
1158 MAC_TX_CLK_0_MHZ = 2,
1159 MAC_TX_CLK_2_5_MHZ = 6,
1160 MAC_TX_CLK_25_MHZ = 7,
1161};
1162
1163/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1164enum {
1165 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1166 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1167 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1168 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1169 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1170 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1171 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1172 /* (88E1111 only) */
1173};
1174
1175enum {
1176 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
1177 /* (88E1011 only) */
1178 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1179 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1180 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1181 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1182 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1183};
1184
1185#define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK)
1186
1187/***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
1188enum {
1189 PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
1190 PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1191 PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1192 PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1193 PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1194 PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1195};
1196
1197#define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK)
1198#define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK)
1199#define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK)
1200#define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK)
1201#define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK)
1202#define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK)
1203
1204enum {
1205 PULS_NO_STR = 0,/* no pulse stretching */
1206 PULS_21MS = 1,/* 21 ms to 42 ms */
1207 PULS_42MS = 2,/* 42 ms to 84 ms */
1208 PULS_84MS = 3,/* 84 ms to 170 ms */
1209 PULS_170MS = 4,/* 170 ms to 340 ms */
1210 PULS_340MS = 5,/* 340 ms to 670 ms */
1211 PULS_670MS = 6,/* 670 ms to 1.3 s */
1212 PULS_1300MS = 7,/* 1.3 s to 2.7 s */
1213};
1214
1215#define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
1216
1217enum {
1218 BLINK_42MS = 0,/* 42 ms */
1219 BLINK_84MS = 1,/* 84 ms */
1220 BLINK_170MS = 2,/* 170 ms */
1221 BLINK_340MS = 3,/* 340 ms */
1222 BLINK_670MS = 4,/* 670 ms */
1223};
1224
1225/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1226#define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1227 /* Bit 13..12: reserved */
1228#define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1229#define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1230#define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1231#define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1232#define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1233#define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1234
1235enum {
1236 MO_LED_NORM = 0,
1237 MO_LED_BLINK = 1,
1238 MO_LED_OFF = 2,
1239 MO_LED_ON = 3,
1240};
1241
1242/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1243enum {
1244 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1245 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1246 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1247 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1248 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
1249};
1250
1251/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1252enum {
1253 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1254 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1255 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1256 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1257 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1258 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1259 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1260 /* (88E1111 only) */
1261
1262 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1263 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1264 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1265};
1266
1267/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1268/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1269 /* Bit 15..12: reserved (used internally) */
1270enum {
1271 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1272 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1273 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1274};
1275
1276#define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
1277#define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
1278#define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
1279
1280enum {
1281 LED_PAR_CTRL_COLX = 0x00,
1282 LED_PAR_CTRL_ERROR = 0x01,
1283 LED_PAR_CTRL_DUPLEX = 0x02,
1284 LED_PAR_CTRL_DP_COL = 0x03,
1285 LED_PAR_CTRL_SPEED = 0x04,
1286 LED_PAR_CTRL_LINK = 0x05,
1287 LED_PAR_CTRL_TX = 0x06,
1288 LED_PAR_CTRL_RX = 0x07,
1289 LED_PAR_CTRL_ACT = 0x08,
1290 LED_PAR_CTRL_LNK_RX = 0x09,
1291 LED_PAR_CTRL_LNK_AC = 0x0a,
1292 LED_PAR_CTRL_ACT_BL = 0x0b,
1293 LED_PAR_CTRL_TX_BL = 0x0c,
1294 LED_PAR_CTRL_RX_BL = 0x0d,
1295 LED_PAR_CTRL_COL_BL = 0x0e,
1296 LED_PAR_CTRL_INACT = 0x0f
1297};
1298
1299/*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1300enum {
1301 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1302 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1303 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1304};
1305
1306/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1307/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1308enum {
1309 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1310 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1311 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1312 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1313};
1314#define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
1315
1316/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1317enum {
1318 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1319 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1320 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1321 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1322};
1323
1324#define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1325#define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1326#define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1327#define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1328
1329/* GMAC registers */
1330/* Port Registers */
1331enum {
1332 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1333 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1334 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1335 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1336 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1337 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1338 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1339/* Source Address Registers */
1340 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1341 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1342 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1343 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1344 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1345 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1346
1347/* Multicast Address Hash Registers */
1348 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1349 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1350 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1351 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1352
1353/* Interrupt Source Registers */
1354 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1355 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1356 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1357
1358/* Interrupt Mask Registers */
1359 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1360 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1361 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1362
1363/* Serial Management Interface (SMI) Registers */
1364 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1365 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1366 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1367};
1368
1369/* MIB Counters */
1370#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
1371#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
1372
1373/*
1374 * MIB Counters base address definitions (low word) -
1375 * use offset 4 for access to high word (32 bit r/o)
1376 */
1377enum {
1378 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1379 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1380 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1381 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1382 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1383 /* GM_MIB_CNT_BASE + 40: reserved */
1384 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1385 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1386 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1387 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1388 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1389 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1390 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1391 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
1392 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
1393 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
1394 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
1395 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
1396 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
1397 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
1398 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
1399 /* GM_MIB_CNT_BASE + 168: reserved */
1400 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
1401 /* GM_MIB_CNT_BASE + 184: reserved */
1402 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
1403 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
1404 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
1405 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
1406 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
1407 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
1408 GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
1409 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
1410 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
1411 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
1412 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
1413 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
1414 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
1415
1416 GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
1417 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
1418 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
1419 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
1420 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
1421 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
1422};
1423
1424/* GMAC Bit Definitions */
1425/* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1426enum {
1427 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1428 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1429 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1430 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1431 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1432 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1433 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
1434 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
1435
1436 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1437 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1438 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1439 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1440 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1441};
1442
1443/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1444enum {
1445 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1446 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1447 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1448 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1449 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1450 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1451 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1452 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1453 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1454 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1455 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1456 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1457 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1458 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1459 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1460};
1461
1462#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1463#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1464
1465/* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1466enum {
1467 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1468 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1469 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1470 GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */
1471};
1472
1473#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1474#define TX_COL_DEF 0x04
1475
1476/* GM_RX_CTRL 16 bit r/w Receive Control Register */
1477enum {
1478 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1479 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1480 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1481 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1482};
1483
1484/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1485enum {
1486 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1487 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1488 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1489 GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
1490
1491 TX_JAM_LEN_DEF = 0x03,
1492 TX_JAM_IPG_DEF = 0x0b,
1493 TX_IPG_JAM_DEF = 0x1c,
1494 TX_BOF_LIM_DEF = 0x04,
1495};
1496
1497#define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1498#define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1499#define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1500#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
1501
1502
1503/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1504enum {
1505 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1506 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1507 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1508 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1509 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1510};
1511
1512#define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1513#define DATA_BLIND_DEF 0x04
1514
1515#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1516#define IPG_DATA_DEF 0x1e
1517
1518/* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1519enum {
1520 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
1521 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
1522 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1523 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1524 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1525};
1526
1527#define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
1528#define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
1529
1530/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1531enum {
1532 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1533 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1534};
1535
1536/* Receive Frame Status Encoding */
1537enum {
1538 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
1539 GMR_FS_VLAN = 1<<13, /* Bit 13: VLAN Packet */
1540 GMR_FS_JABBER = 1<<12, /* Bit 12: Jabber Packet */
1541 GMR_FS_UN_SIZE = 1<<11, /* Bit 11: Undersize Packet */
1542 GMR_FS_MC = 1<<10, /* Bit 10: Multicast Packet */
1543 GMR_FS_BC = 1<<9, /* Bit 9: Broadcast Packet */
1544 GMR_FS_RX_OK = 1<<8, /* Bit 8: Receive OK (Good Packet) */
1545 GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
1546 GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
1547 GMR_FS_MII_ERR = 1<<5, /* Bit 5: MII Error */
1548 GMR_FS_LONG_ERR = 1<<4, /* Bit 4: Too Long Packet */
1549 GMR_FS_FRAGMENT = 1<<3, /* Bit 3: Fragment */
1550
1551 GMR_FS_CRC_ERR = 1<<1, /* Bit 1: CRC Error */
1552 GMR_FS_RX_FF_OV = 1<<0, /* Bit 0: Rx FIFO Overflow */
1553
1554/*
1555 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
1556 */
1557 GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
1558 GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
1559 GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
1560 GMR_FS_UN_SIZE | GMR_FS_JABBER,
1561/* Rx GMAC FIFO Flush Mask (default) */
1562 RX_FF_FL_DEF_MSK = GMR_FS_ANY_ERR,
1563};
1564
1565/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1566enum {
1567 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1568 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
1569 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
1570
1571 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1572 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
1573 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
1574 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1575 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1576 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1577 GMF_CLI_RX_FC = 1<<4, /* Clear IRQ Rx Frame Complete */
1578 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1579 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1580 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1581 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1582
1583 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
1584};
1585
1586
1587/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1588enum {
1589 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
1590 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
1591 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
1592
1593 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1594 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1595 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1596};
1597
1598/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1599enum {
1600 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1601 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1602 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1603};
1604
1605/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
1606enum {
1607 Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */
1608 Y2_ASF_RESET = 1<<3, /* ASF system in reset state */
1609 Y2_ASF_RUNNING = 1<<2, /* ASF system operational */
1610 Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */
1611 Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */
1612
1613 Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */
1614 Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */
1615};
1616
1617/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
1618enum {
1619 Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
1620 Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
1621};
1622
1623/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
1624enum {
1625 SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */
1626 SC_STAT_OP_ON = 1<<3, /* Operational Mode On */
1627 SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */
1628 SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
1629 SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */
1630};
1631
1632/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1633enum {
1634 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1635 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1636 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1637 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1638 GMC_PAUSE_ON = 1<<3, /* Pause On */
1639 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
1640 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1641 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1642};
1643
1644/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1645enum {
1646 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1647 GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
1648 GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
1649 GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
1650 GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
1651 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
1652 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
1653 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
1654 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
1655 GPC_ANEG_0 = 1<<19, /* ANEG[0] */
1656 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
1657 GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
1658 GPC_ANEG_3 = 1<<16, /* ANEG[3] */
1659 GPC_ANEG_2 = 1<<15, /* ANEG[2] */
1660 GPC_ANEG_1 = 1<<14, /* ANEG[1] */
1661 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
1662 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
1663 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
1664 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
1665 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
1666 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
1667 /* Bits 7..2: reserved */
1668 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1669 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1670};
1671
1672/* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1673/* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1674enum {
1675 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
1676 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
1677 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
1678 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
1679 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
1680 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
1681
1682#define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV |\
1683 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR)
1684
1685/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1686 /* Bits 15.. 2: reserved */
1687 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
1688 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
1689
1690
1691/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1692 WOL_CTL_LINK_CHG_OCC = 1<<15,
1693 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
1694 WOL_CTL_PATTERN_OCC = 1<<13,
1695 WOL_CTL_CLEAR_RESULT = 1<<12,
1696 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
1697 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
1698 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
1699 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
1700 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
1701 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
1702 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
1703 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
1704 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
1705 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
1706 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
1707 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
1708};
1709
1710#define WOL_CTL_DEFAULT \
1711 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
1712 WOL_CTL_DIS_PME_ON_PATTERN | \
1713 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
1714 WOL_CTL_DIS_LINK_CHG_UNIT | \
1715 WOL_CTL_DIS_PATTERN_UNIT | \
1716 WOL_CTL_DIS_MAGIC_PKT_UNIT)
1717
1718/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
1719#define WOL_CTL_PATT_ENA(x) (1 << (x))
1720
1721
1722/* Control flags */
1723enum {
1724 UDPTCP = 1<<0,
1725 CALSUM = 1<<1,
1726 WR_SUM = 1<<2,
1727 INIT_SUM= 1<<3,
1728 LOCK_SUM= 1<<4,
1729 INS_VLAN= 1<<5,
1730 FRC_STAT= 1<<6,
1731 EOP = 1<<7,
1732};
1733
1734enum {
1735 HW_OWNER = 1<<7,
1736 OP_TCPWRITE = 0x11,
1737 OP_TCPSTART = 0x12,
1738 OP_TCPINIT = 0x14,
1739 OP_TCPLCK = 0x18,
1740 OP_TCPCHKSUM = OP_TCPSTART,
1741 OP_TCPIS = OP_TCPINIT | OP_TCPSTART,
1742 OP_TCPLW = OP_TCPLCK | OP_TCPWRITE,
1743 OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
1744 OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
1745
1746 OP_ADDR64 = 0x21,
1747 OP_VLAN = 0x22,
1748 OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN,
1749 OP_LRGLEN = 0x24,
1750 OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN,
1751 OP_BUFFER = 0x40,
1752 OP_PACKET = 0x41,
1753 OP_LARGESEND = 0x43,
1754
1755/* YUKON-2 STATUS opcodes defines */
1756 OP_RXSTAT = 0x60,
1757 OP_RXTIMESTAMP = 0x61,
1758 OP_RXVLAN = 0x62,
1759 OP_RXCHKS = 0x64,
1760 OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN,
1761 OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
1762 OP_RSS_HASH = 0x65,
1763 OP_TXINDEXLE = 0x68,
1764
1765/* YUKON-2 SPECIAL opcodes defines */
1766 OP_PUTIDX = 0x70,
1767};
1768
1769/* Yukon 2 hardware interface
1770 * Not tested on big endian
1771 */
1772struct sky2_tx_le {
1773 union {
1774 u32 addr;
1775 struct {
1776 u16 offset;
1777 u16 start;
1778 } csum;
1779 struct {
1780 u16 size;
1781 u16 rsvd;
1782 } tso;
1783 } tx;
1784 u16 length; /* also vlan tag or checksum start */
1785 u8 ctrl;
1786 u8 opcode;
1787};
1788
1789struct sky2_rx_le {
1790 union {
1791 u32 addr;
1792 struct {
1793 u16 start1;
1794 u16 start2;
1795 } csum;
1796 } rx;
1797 u16 length;
1798 u8 ctrl;
1799 u8 opcode;
1800};
1801
1802struct sky2_status_le {
1803 u32 status; /* also checksum */
1804 u16 length; /* also vlan tag */
1805 u8 link;
1806 u8 opcode;
1807};
1808
1809
1810struct ring_info {
1811 struct sk_buff *skb;
1812 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1813 DECLARE_PCI_UNMAP_LEN(maplen);
1814};
1815
1816struct sky2_port {
1817 struct sky2_hw *hw ____cacheline_aligned;
1818 struct net_device *netdev;
1819 unsigned port;
1820 u32 msg_enable;
1821
1822 struct ring_info *tx_ring ____cacheline_aligned;
1823 struct sky2_tx_le *tx_le;
1824 spinlock_t tx_lock;
1825 u16 tx_cons; /* next le to check */
1826 u16 tx_prod; /* next le to use */
1827 u16 tx_last_put;
1828
1829 struct ring_info *rx_ring ____cacheline_aligned;
1830 struct sky2_rx_le *rx_le;
1831 u16 rx_ring_size;
1832 u16 rx_next; /* next re to check */
1833 u16 rx_put; /* next le index to use */
1834 u16 rx_last_put;
1835
1836 dma_addr_t rx_le_map;
1837 dma_addr_t tx_le_map;
1838 u32 advertising; /* ADVERTISED_ bits */
1839 u16 speed; /* SPEED_1000, SPEED_100, ... */
1840 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
1841 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
1842 u8 rx_pause;
1843 u8 tx_pause;
1844 u8 rx_csum;
1845 u8 wol;
1846
1847 struct tasklet_struct phy_task;
1848 struct net_device_stats net_stats;
1849};
1850
1851struct sky2_hw {
1852 void __iomem *regs;
1853 struct pci_dev *pdev;
1854 u32 intr_mask;
1855 struct net_device *dev[2];
1856
1857 u8 chip_id;
1858 u8 chip_rev;
1859 u8 copper;
1860 u8 ports;
1861
1862 struct sky2_status_le *st_le;
1863 u32 st_idx;
1864 dma_addr_t st_dma;
1865
1866 spinlock_t phy_lock;
1867};
1868
1869/* Register accessor for memory mapped device */
1870static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
1871{
1872 return readl(hw->regs + reg);
1873}
1874
1875static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
1876{
1877 return readw(hw->regs + reg);
1878}
1879
1880static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
1881{
1882 return readb(hw->regs + reg);
1883}
1884
1885static inline int is_pciex(const struct sky2_hw *hw)
1886{
1887 return (sky2_read32(hw, PCI_C(PCI_DEV_STATUS)) & PCI_OS_PCI_X) == 0;
1888}
1889
1890
1891static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
1892{
1893 writel(val, hw->regs + reg);
1894}
1895
1896static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
1897{
1898 writew(val, hw->regs + reg);
1899}
1900
1901static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
1902{
1903 writeb(val, hw->regs + reg);
1904}
1905
1906/* Yukon PHY related registers */
1907#define SK_GMAC_REG(port,reg) \
1908 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
1909#define GM_PHY_RETRIES 100
1910
1911static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
1912{
1913 return sky2_read16(hw, SK_GMAC_REG(port,reg));
1914}
1915
1916static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
1917{
1918 unsigned base = SK_GMAC_REG(port, reg);
1919 return (u32) sky2_read16(hw, base)
1920 | (u32) sky2_read16(hw, base+4) << 16;
1921}
1922
1923static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
1924{
1925 sky2_write16(hw, SK_GMAC_REG(port,r), v);
1926}
1927
1928static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
1929 const u8 *addr)
1930{
1931 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
1932 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
1933 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
1934}
1935#endif
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