diff options
Diffstat (limited to 'drivers/net/sky2.h')
-rw-r--r-- | drivers/net/sky2.h | 29 |
1 files changed, 11 insertions, 18 deletions
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h index 3caeddf893ef..00907f58019e 100644 --- a/drivers/net/sky2.h +++ b/drivers/net/sky2.h | |||
@@ -592,23 +592,15 @@ enum { | |||
592 | enum { | 592 | enum { |
593 | B8_Q_REGS = 0x0400, /* base of Queue registers */ | 593 | B8_Q_REGS = 0x0400, /* base of Queue registers */ |
594 | Q_D = 0x00, /* 8*32 bit Current Descriptor */ | 594 | Q_D = 0x00, /* 8*32 bit Current Descriptor */ |
595 | Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */ | 595 | Q_VLAN = 0x20, /* 16 bit Current VLAN Tag */ |
596 | Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */ | 596 | Q_DONE = 0x24, /* 16 bit Done Index */ |
597 | Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */ | 597 | Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */ |
598 | Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */ | 598 | Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */ |
599 | Q_BC = 0x30, /* 32 bit Current Byte Counter */ | 599 | Q_BC = 0x30, /* 32 bit Current Byte Counter */ |
600 | Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */ | 600 | Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */ |
601 | Q_F = 0x38, /* 32 bit Flag Register */ | 601 | Q_TEST = 0x38, /* 32 bit Test/Control Register */ |
602 | Q_T1 = 0x3c, /* 32 bit Test Register 1 */ | ||
603 | Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */ | ||
604 | Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */ | ||
605 | Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */ | ||
606 | Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */ | ||
607 | Q_T2 = 0x40, /* 32 bit Test Register 2 */ | ||
608 | Q_T3 = 0x44, /* 32 bit Test Register 3 */ | ||
609 | 602 | ||
610 | /* Yukon-2 */ | 603 | /* Yukon-2 */ |
611 | Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */ | ||
612 | Q_WM = 0x40, /* 16 bit FIFO Watermark */ | 604 | Q_WM = 0x40, /* 16 bit FIFO Watermark */ |
613 | Q_AL = 0x42, /* 8 bit FIFO Alignment */ | 605 | Q_AL = 0x42, /* 8 bit FIFO Alignment */ |
614 | Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */ | 606 | Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */ |
@@ -622,15 +614,16 @@ enum { | |||
622 | }; | 614 | }; |
623 | #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) | 615 | #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) |
624 | 616 | ||
625 | /* Q_F 32 bit Flag Register */ | 617 | /* Q_TEST 32 bit Test Register */ |
626 | enum { | 618 | enum { |
627 | F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */ | 619 | /* Transmit */ |
628 | F_EMPTY = 1<<27, /* Tx FIFO: empty flag */ | 620 | F_TX_CHK_AUTO_OFF = 1<<31, /* Tx checksum auto calc off (Yukon EX) */ |
629 | F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */ | 621 | F_TX_CHK_AUTO_ON = 1<<30, /* Tx checksum auto calc off (Yukon EX) */ |
630 | F_WM_REACHED = 1<<25, /* Watermark reached */ | 622 | |
623 | /* Receive */ | ||
631 | F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */ | 624 | F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */ |
632 | F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */ | 625 | |
633 | F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */ | 626 | /* Hardware testbits not used */ |
634 | }; | 627 | }; |
635 | 628 | ||
636 | /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ | 629 | /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ |