1 files changed, 171 insertions, 31 deletions

diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 4b0f03358777..c83406f4f2a7 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -284,6 +284,86 @@ static void sky2_power_aux(struct sky2_hw *hw)
                              PC_VAUX_ON | PC_VCC_OFF));
 }
 
+static void sky2_power_state(struct sky2_hw *hw, pci_power_t state)
+{
+        u16 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
+        int pex = pci_find_capability(hw->pdev, PCI_CAP_ID_EXP);
+        u32 reg;
+
+        sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
+
+        switch (state) {
+        case PCI_D0:
+                break;
+
+        case PCI_D1:
+                power_control |= 1;
+                break;
+
+        case PCI_D2:
+                power_control |= 2;
+                break;
+
+        case PCI_D3hot:
+        case PCI_D3cold:
+                power_control |= 3;
+                if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
+                        /* additional power saving measurements */
+                        reg = sky2_pci_read32(hw, PCI_DEV_REG4);
+
+                        /* set gating core clock for LTSSM in L1 state */
+                        reg |= P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
+                                /* auto clock gated scheme controlled by CLKREQ */
+                                P_ASPM_A1_MODE_SELECT |
+                                /* enable Gate Root Core Clock */
+                                P_CLK_GATE_ROOT_COR_ENA;
+
+                        if (pex && (hw->flags & SKY2_HW_CLK_POWER)) {
+                                /* enable Clock Power Management (CLKREQ) */
+                                u16 ctrl = sky2_pci_read16(hw, pex + PCI_EXP_DEVCTL);
+
+                                ctrl |= PCI_EXP_DEVCTL_AUX_PME;
+                                sky2_pci_write16(hw, pex + PCI_EXP_DEVCTL, ctrl);
+                        } else
+                                /* force CLKREQ Enable in Our4 (A1b only) */
+                                reg |= P_ASPM_FORCE_CLKREQ_ENA;
+
+                        /* set Mask Register for Release/Gate Clock */
+                        sky2_pci_write32(hw, PCI_DEV_REG5,
+                                         P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
+                                         P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
+                                         P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN);
+                } else
+                        sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_CLK_HALT);
+
+                /* put CPU into reset state */
+                sky2_write8(hw,  B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_RESET);
+                if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev == CHIP_REV_YU_SU_A0)
+                        /* put CPU into halt state */
+                        sky2_write8(hw, B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_HALTED);
+
+                if (pex && !(hw->flags & SKY2_HW_RAM_BUFFER)) {
+                        reg = sky2_pci_read32(hw, PCI_DEV_REG1);
+                        /* force to PCIe L1 */
+                        reg |= PCI_FORCE_PEX_L1;
+                        sky2_pci_write32(hw, PCI_DEV_REG1, reg);
+                }
+                break;
+
+        default:
+                dev_warn(&hw->pdev->dev, PFX "Invalid power state (%d) ",
+                       state);
+                return;
+        }
+
+        power_control |= PCI_PM_CTRL_PME_ENABLE;
+        /* Finally, set the new power state. */
+        sky2_pci_write32(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
+
+        sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
+        sky2_pci_read32(hw, B0_CTST);
+}
+
 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
 {
         u16 reg;
@@ -619,28 +699,71 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
                 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
 }
 
-static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
+static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
+static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
+
+static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
 {
         u32 reg1;
-        static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
-        static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
 
         sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
         reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
-        /* Turn on/off phy power saving */
-        if (onoff)
-                reg1 &= ~phy_power[port];
-        else
-                reg1 |= phy_power[port];
+        reg1 &= ~phy_power[port];
 
-        if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
+        if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
                 reg1 |= coma_mode[port];
 
         sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
         sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
         sky2_pci_read32(hw, PCI_DEV_REG1);
+}
+
+static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
+{
+        u32 reg1;
+        u16 ctrl;
+
+        /* release GPHY Control reset */
+        sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
+
+        /* release GMAC reset */
+        sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
 
-        udelay(100);
+        if (hw->flags & SKY2_HW_NEWER_PHY) {
+                /* select page 2 to access MAC control register */
+                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
+
+                ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
+                /* allow GMII Power Down */
+                ctrl &= ~PHY_M_MAC_GMIF_PUP;
+                gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
+
+                /* set page register back to 0 */
+                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
+        }
+
+        /* setup General Purpose Control Register */
+        gma_write16(hw, port, GM_GP_CTRL,
+                    GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
+
+        if (hw->chip_id != CHIP_ID_YUKON_EC) {
+                if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
+                        ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
+
+                        /* enable Power Down */
+                        ctrl |= PHY_M_PC_POW_D_ENA;
+                        gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
+                }
+
+                /* set IEEE compatible Power Down Mode (dev. #4.99) */
+                gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
+        }
+
+        sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
+        reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
+        reg1 |= phy_power[port];                /* set PHY to PowerDown/COMA Mode */
+        sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
+        sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
 }
 
 /* Force a renegotiation */
@@ -675,8 +798,11 @@ static void sky2_wol_init(struct sky2_port *sky2)
 
         sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
         sky2->flow_mode = FC_NONE;
-        sky2_phy_power(hw, port, 1);
-        sky2_phy_reinit(sky2);
+
+        spin_lock_bh(&sky2->phy_lock);
+        sky2_phy_power_up(hw, port);
+        sky2_phy_init(hw, port);
+        spin_unlock_bh(&sky2->phy_lock);
 
         sky2->flow_mode = save_mode;
         sky2->advertising = ctrl;
@@ -781,6 +907,7 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
         sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
 
         spin_lock_bh(&sky2->phy_lock);
+        sky2_phy_power_up(hw, port);
         sky2_phy_init(hw, port);
         spin_unlock_bh(&sky2->phy_lock);
 
@@ -1159,17 +1286,9 @@ static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 }
 
 #ifdef SKY2_VLAN_TAG_USED
-static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
+static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
 {
-        struct sky2_port *sky2 = netdev_priv(dev);
-        struct sky2_hw *hw = sky2->hw;
-        u16 port = sky2->port;
-
-        netif_tx_lock_bh(dev);
-        napi_disable(&hw->napi);
-
-        sky2->vlgrp = grp;
-        if (grp) {
+        if (onoff) {
                 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
                              RX_VLAN_STRIP_ON);
                 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
@@ -1180,6 +1299,19 @@ static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp
                 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
                              TX_VLAN_TAG_OFF);
         }
+}
+
+static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
+{
+        struct sky2_port *sky2 = netdev_priv(dev);
+        struct sky2_hw *hw = sky2->hw;
+        u16 port = sky2->port;
+
+        netif_tx_lock_bh(dev);
+        napi_disable(&hw->napi);
+
+        sky2->vlgrp = grp;
+        sky2_set_vlan_mode(hw, port, grp != NULL);
 
         sky2_read32(hw, B0_Y2_SP_LISR);
         napi_enable(&hw->napi);
@@ -1380,8 +1512,6 @@ static int sky2_up(struct net_device *dev)
         if (!sky2->rx_ring)
                 goto err_out;
 
-        sky2_phy_power(hw, port, 1);
-
         sky2_mac_init(hw, port);
 
         /* Register is number of 4K blocks on internal RAM buffer. */
@@ -1418,6 +1548,10 @@ static int sky2_up(struct net_device *dev)
         sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
                            TX_RING_SIZE - 1);
 
+#ifdef SKY2_VLAN_TAG_USED
+        sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
+#endif
+
         err = sky2_rx_start(sky2);
         if (err)
                 goto err_out;
@@ -1758,7 +1892,7 @@ static int sky2_down(struct net_device *dev)
         sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
         sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
 
-        sky2_phy_power(hw, port, 0);
+        sky2_phy_power_down(hw, port);
 
         netif_carrier_off(dev);
 
@@ -2732,6 +2866,10 @@ static int __devinit sky2_init(struct sky2_hw *hw)
                 hw->flags = SKY2_HW_GIGABIT
                         | SKY2_HW_NEWER_PHY
                         | SKY2_HW_ADV_POWER_CTL;
+
+                /* check for Rev. A1 dev 4200 */
+                if (sky2_read16(hw, Q_ADDR(Q_XA1, Q_WM)) == 0)
+                        hw->flags |= SKY2_HW_CLK_POWER;
                 break;
 
         case CHIP_ID_YUKON_EX:
@@ -2782,6 +2920,11 @@ static int __devinit sky2_init(struct sky2_hw *hw)
         if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
                 hw->flags |= SKY2_HW_FIBRE_PHY;
 
+        hw->pm_cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PM);
+        if (hw->pm_cap == 0) {
+                dev_err(&hw->pdev->dev, "cannot find PowerManagement capability\n");
+                return -EIO;
+        }
 
         hw->ports = 1;
         t8 = sky2_read8(hw, B2_Y2_HW_RES);
@@ -4353,7 +4496,7 @@ static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
 
         pci_save_state(pdev);
         pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
-        pci_set_power_state(pdev, pci_choose_state(pdev, state));
+        sky2_power_state(hw, pci_choose_state(pdev, state));
 
         return 0;
 }
@@ -4366,9 +4509,7 @@ static int sky2_resume(struct pci_dev *pdev)
         if (!hw)
                 return 0;
 
-        err = pci_set_power_state(pdev, PCI_D0);
-        if (err)
-                goto out;
+        sky2_power_state(hw, PCI_D0);
 
         err = pci_restore_state(pdev);
         if (err)
@@ -4436,8 +4577,7 @@ static void sky2_shutdown(struct pci_dev *pdev)
         pci_enable_wake(pdev, PCI_D3cold, wol);
 
         pci_disable_device(pdev);
-        pci_set_power_state(pdev, PCI_D3hot);
-
+        sky2_power_state(hw, PCI_D3hot);
 }
 
 static struct pci_driver sky2_driver = {