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path: root/drivers/net/sky2.c
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-rw-r--r--drivers/net/sky2.c283
1 files changed, 152 insertions, 131 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index c10e7f5faa5f..842abd9396c6 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -10,8 +10,7 @@
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by 12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or 13 * the Free Software Foundation; either version 2 of the License.
14 * (at your option) any later version.
15 * 14 *
16 * This program is distributed in the hope that it will be useful, 15 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -50,7 +49,7 @@
50#include "sky2.h" 49#include "sky2.h"
51 50
52#define DRV_NAME "sky2" 51#define DRV_NAME "sky2"
53#define DRV_VERSION "1.9" 52#define DRV_VERSION "1.10"
54#define PFX DRV_NAME " " 53#define PFX DRV_NAME " "
55 54
56/* 55/*
@@ -96,15 +95,16 @@ static int disable_msi = 0;
96module_param(disable_msi, int, 0); 95module_param(disable_msi, int, 0);
97MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98 97
99static int idle_timeout = 100; 98static int idle_timeout = 0;
100module_param(idle_timeout, int, 0); 99module_param(idle_timeout, int, 0);
101MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)"); 100MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
102 101
103static const struct pci_device_id sky2_id_table[] = { 102static const struct pci_device_id sky2_id_table[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
@@ -284,6 +284,31 @@ static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
284 gma_write16(hw, port, GM_RX_CTRL, reg); 284 gma_write16(hw, port, GM_RX_CTRL, reg);
285} 285}
286 286
287/* flow control to advertise bits */
288static const u16 copper_fc_adv[] = {
289 [FC_NONE] = 0,
290 [FC_TX] = PHY_M_AN_ASP,
291 [FC_RX] = PHY_M_AN_PC,
292 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
293};
294
295/* flow control to advertise bits when using 1000BaseX */
296static const u16 fiber_fc_adv[] = {
297 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
298 [FC_TX] = PHY_M_P_ASYM_MD_X,
299 [FC_RX] = PHY_M_P_SYM_MD_X,
300 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
301};
302
303/* flow control to GMA disable bits */
304static const u16 gm_fc_disable[] = {
305 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
306 [FC_TX] = GM_GPCR_FC_RX_DIS,
307 [FC_RX] = GM_GPCR_FC_TX_DIS,
308 [FC_BOTH] = 0,
309};
310
311
287static void sky2_phy_init(struct sky2_hw *hw, unsigned port) 312static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
288{ 313{
289 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 314 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
@@ -356,16 +381,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
356 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 381 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
357 } 382 }
358 383
359 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); 384 ctrl = PHY_CT_RESET;
360 if (sky2->autoneg == AUTONEG_DISABLE)
361 ctrl &= ~PHY_CT_ANE;
362 else
363 ctrl |= PHY_CT_ANE;
364
365 ctrl |= PHY_CT_RESET;
366 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
367
368 ctrl = 0;
369 ct1000 = 0; 385 ct1000 = 0;
370 adv = PHY_AN_CSMA; 386 adv = PHY_AN_CSMA;
371 reg = 0; 387 reg = 0;
@@ -384,20 +400,16 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
384 adv |= PHY_M_AN_10_FD; 400 adv |= PHY_M_AN_10_FD;
385 if (sky2->advertising & ADVERTISED_10baseT_Half) 401 if (sky2->advertising & ADVERTISED_10baseT_Half)
386 adv |= PHY_M_AN_10_HD; 402 adv |= PHY_M_AN_10_HD;
403
404 adv |= copper_fc_adv[sky2->flow_mode];
387 } else { /* special defines for FIBER (88E1040S only) */ 405 } else { /* special defines for FIBER (88E1040S only) */
388 if (sky2->advertising & ADVERTISED_1000baseT_Full) 406 if (sky2->advertising & ADVERTISED_1000baseT_Full)
389 adv |= PHY_M_AN_1000X_AFD; 407 adv |= PHY_M_AN_1000X_AFD;
390 if (sky2->advertising & ADVERTISED_1000baseT_Half) 408 if (sky2->advertising & ADVERTISED_1000baseT_Half)
391 adv |= PHY_M_AN_1000X_AHD; 409 adv |= PHY_M_AN_1000X_AHD;
392 }
393 410
394 /* Set Flow-control capabilities */ 411 adv |= fiber_fc_adv[sky2->flow_mode];
395 if (sky2->tx_pause && sky2->rx_pause) 412 }
396 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
397 else if (sky2->rx_pause && !sky2->tx_pause)
398 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
399 else if (!sky2->rx_pause && sky2->tx_pause)
400 adv |= PHY_AN_PAUSE_ASYM; /* local */
401 413
402 /* Restart Auto-negotiation */ 414 /* Restart Auto-negotiation */
403 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 415 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
@@ -422,25 +434,17 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
422 if (sky2->duplex == DUPLEX_FULL) { 434 if (sky2->duplex == DUPLEX_FULL) {
423 reg |= GM_GPCR_DUP_FULL; 435 reg |= GM_GPCR_DUP_FULL;
424 ctrl |= PHY_CT_DUP_MD; 436 ctrl |= PHY_CT_DUP_MD;
425 } else if (sky2->speed != SPEED_1000 && hw->chip_id != CHIP_ID_YUKON_EC_U) { 437 } else if (sky2->speed < SPEED_1000)
426 /* Turn off flow control for 10/100mbps */ 438 sky2->flow_mode = FC_NONE;
427 sky2->rx_pause = 0;
428 sky2->tx_pause = 0;
429 }
430 439
431 if (!sky2->rx_pause)
432 reg |= GM_GPCR_FC_RX_DIS;
433 440
434 if (!sky2->tx_pause) 441 reg |= gm_fc_disable[sky2->flow_mode];
435 reg |= GM_GPCR_FC_TX_DIS;
436 442
437 /* Forward pause packets to GMAC? */ 443 /* Forward pause packets to GMAC? */
438 if (sky2->tx_pause || sky2->rx_pause) 444 if (sky2->flow_mode & FC_RX)
439 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 445 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
440 else 446 else
441 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 447 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
442
443 ctrl |= PHY_CT_RESET;
444 } 448 }
445 449
446 gma_write16(hw, port, GM_GP_CTRL, reg); 450 gma_write16(hw, port, GM_GP_CTRL, reg);
@@ -673,17 +677,15 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
673 /* Flush Rx MAC FIFO on any flow control or error */ 677 /* Flush Rx MAC FIFO on any flow control or error */
674 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); 678 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
675 679
676 /* Set threshold to 0xa (64 bytes) 680 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
677 * ASF disabled so no need to do WA dev #4.30 681 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
678 */
679 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
680 682
681 /* Configure Tx MAC FIFO */ 683 /* Configure Tx MAC FIFO */
682 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 684 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
683 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 685 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
684 686
685 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 687 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
686 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 512/8); 688 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
687 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); 689 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
688 if (hw->dev[port]->mtu > ETH_DATA_LEN) { 690 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
689 /* set Tx GMAC FIFO Almost Empty Threshold */ 691 /* set Tx GMAC FIFO Almost Empty Threshold */
@@ -695,16 +697,10 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
695 697
696} 698}
697 699
698/* Assign Ram Buffer allocation. 700/* Assign Ram Buffer allocation in units of 64bit (8 bytes) */
699 * start and end are in units of 4k bytes 701static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 end)
700 * ram registers are in units of 64bit words
701 */
702static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
703{ 702{
704 u32 start, end; 703 pr_debug(PFX "q %d %#x %#x\n", q, start, end);
705
706 start = startk * 4096/8;
707 end = (endk * 4096/8) - 1;
708 704
709 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 705 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
710 sky2_write32(hw, RB_ADDR(q, RB_START), start); 706 sky2_write32(hw, RB_ADDR(q, RB_START), start);
@@ -713,7 +709,7 @@ static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
713 sky2_write32(hw, RB_ADDR(q, RB_RP), start); 709 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
714 710
715 if (q == Q_R1 || q == Q_R2) { 711 if (q == Q_R1 || q == Q_R2) {
716 u32 space = (endk - startk) * 4096/8; 712 u32 space = end - start + 1;
717 u32 tp = space - space/4; 713 u32 tp = space - space/4;
718 714
719 /* On receive queue's set the thresholds 715 /* On receive queue's set the thresholds
@@ -1063,7 +1059,8 @@ static int sky2_rx_start(struct sky2_port *sky2)
1063 sky2->rx_put = sky2->rx_next = 0; 1059 sky2->rx_put = sky2->rx_next = 0;
1064 sky2_qset(hw, rxq); 1060 sky2_qset(hw, rxq);
1065 1061
1066 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) { 1062 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1063 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) {
1067 /* MAC Rx RAM Read is controlled by hardware */ 1064 /* MAC Rx RAM Read is controlled by hardware */
1068 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); 1065 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1069 } 1066 }
@@ -1195,19 +1192,16 @@ static int sky2_up(struct net_device *dev)
1195 1192
1196 sky2_mac_init(hw, port); 1193 sky2_mac_init(hw, port);
1197 1194
1198 /* Determine available ram buffer space (in 4K blocks). 1195 /* Determine available ram buffer space in qwords. */
1199 * Note: not sure about the FE setting below yet 1196 ramsize = sky2_read8(hw, B2_E_0) * 4096/8;
1200 */
1201 if (hw->chip_id == CHIP_ID_YUKON_FE)
1202 ramsize = 4;
1203 else
1204 ramsize = sky2_read8(hw, B2_E_0);
1205 1197
1206 /* Give transmitter one third (rounded up) */ 1198 if (ramsize > 6*1024/8)
1207 rxspace = ramsize - (ramsize + 2) / 3; 1199 rxspace = ramsize - (ramsize + 2) / 3;
1200 else
1201 rxspace = ramsize / 2;
1208 1202
1209 sky2_ramset(hw, rxqaddr[port], 0, rxspace); 1203 sky2_ramset(hw, rxqaddr[port], 0, rxspace-1);
1210 sky2_ramset(hw, txqaddr[port], rxspace, ramsize); 1204 sky2_ramset(hw, txqaddr[port], rxspace, ramsize-1);
1211 1205
1212 /* Make sure SyncQ is disabled */ 1206 /* Make sure SyncQ is disabled */
1213 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), 1207 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
@@ -1356,7 +1350,7 @@ static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1356 u32 tcpsum; 1350 u32 tcpsum;
1357 1351
1358 tcpsum = offset << 16; /* sum start */ 1352 tcpsum = offset << 16; /* sum start */
1359 tcpsum |= offset + skb->csum; /* sum write */ 1353 tcpsum |= offset + skb->csum_offset; /* sum write */
1360 1354
1361 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 1355 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1362 if (skb->nh.iph->protocol == IPPROTO_UDP) 1356 if (skb->nh.iph->protocol == IPPROTO_UDP)
@@ -1459,7 +1453,7 @@ static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1459 if (unlikely(netif_msg_tx_done(sky2))) 1453 if (unlikely(netif_msg_tx_done(sky2)))
1460 printk(KERN_DEBUG "%s: tx done %u\n", 1454 printk(KERN_DEBUG "%s: tx done %u\n",
1461 dev->name, idx); 1455 dev->name, idx);
1462 dev_kfree_skb(re->skb); 1456 dev_kfree_skb_any(re->skb);
1463 } 1457 }
1464 1458
1465 le->opcode = 0; /* paranoia */ 1459 le->opcode = 0; /* paranoia */
@@ -1499,6 +1493,11 @@ static int sky2_down(struct net_device *dev)
1499 /* Stop more packets from being queued */ 1493 /* Stop more packets from being queued */
1500 netif_stop_queue(dev); 1494 netif_stop_queue(dev);
1501 1495
1496 /* Disable port IRQ */
1497 imask = sky2_read32(hw, B0_IMSK);
1498 imask &= ~portirq_msk[port];
1499 sky2_write32(hw, B0_IMSK, imask);
1500
1502 sky2_gmac_reset(hw, port); 1501 sky2_gmac_reset(hw, port);
1503 1502
1504 /* Stop transmitter */ 1503 /* Stop transmitter */
@@ -1510,7 +1509,7 @@ static int sky2_down(struct net_device *dev)
1510 1509
1511 /* WA for dev. #4.209 */ 1510 /* WA for dev. #4.209 */
1512 if (hw->chip_id == CHIP_ID_YUKON_EC_U 1511 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1513 && hw->chip_rev == CHIP_REV_YU_EC_U_A1) 1512 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1514 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1513 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1515 sky2->speed != SPEED_1000 ? 1514 sky2->speed != SPEED_1000 ?
1516 TX_STFW_ENA : TX_STFW_DIS); 1515 TX_STFW_ENA : TX_STFW_DIS);
@@ -1549,11 +1548,6 @@ static int sky2_down(struct net_device *dev)
1549 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 1548 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1550 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 1549 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1551 1550
1552 /* Disable port IRQ */
1553 imask = sky2_read32(hw, B0_IMSK);
1554 imask &= ~portirq_msk[port];
1555 sky2_write32(hw, B0_IMSK, imask);
1556
1557 sky2_phy_power(hw, port, 0); 1551 sky2_phy_power(hw, port, 0);
1558 1552
1559 /* turn off LED's */ 1553 /* turn off LED's */
@@ -1605,6 +1599,12 @@ static void sky2_link_up(struct sky2_port *sky2)
1605 struct sky2_hw *hw = sky2->hw; 1599 struct sky2_hw *hw = sky2->hw;
1606 unsigned port = sky2->port; 1600 unsigned port = sky2->port;
1607 u16 reg; 1601 u16 reg;
1602 static const char *fc_name[] = {
1603 [FC_NONE] = "none",
1604 [FC_TX] = "tx",
1605 [FC_RX] = "rx",
1606 [FC_BOTH] = "both",
1607 };
1608 1608
1609 /* enable Rx/Tx */ 1609 /* enable Rx/Tx */
1610 reg = gma_read16(hw, port, GM_GP_CTRL); 1610 reg = gma_read16(hw, port, GM_GP_CTRL);
@@ -1648,8 +1648,7 @@ static void sky2_link_up(struct sky2_port *sky2)
1648 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", 1648 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1649 sky2->netdev->name, sky2->speed, 1649 sky2->netdev->name, sky2->speed,
1650 sky2->duplex == DUPLEX_FULL ? "full" : "half", 1650 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1651 (sky2->tx_pause && sky2->rx_pause) ? "both" : 1651 fc_name[sky2->flow_status]);
1652 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1653} 1652}
1654 1653
1655static void sky2_link_down(struct sky2_port *sky2) 1654static void sky2_link_down(struct sky2_port *sky2)
@@ -1664,7 +1663,7 @@ static void sky2_link_down(struct sky2_port *sky2)
1664 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 1663 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1665 gma_write16(hw, port, GM_GP_CTRL, reg); 1664 gma_write16(hw, port, GM_GP_CTRL, reg);
1666 1665
1667 if (sky2->rx_pause && !sky2->tx_pause) { 1666 if (sky2->flow_status == FC_RX) {
1668 /* restore Asymmetric Pause bit */ 1667 /* restore Asymmetric Pause bit */
1669 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, 1668 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1670 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV) 1669 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
@@ -1683,6 +1682,14 @@ static void sky2_link_down(struct sky2_port *sky2)
1683 sky2_phy_init(hw, port); 1682 sky2_phy_init(hw, port);
1684} 1683}
1685 1684
1685static enum flow_control sky2_flow(int rx, int tx)
1686{
1687 if (rx)
1688 return tx ? FC_BOTH : FC_RX;
1689 else
1690 return tx ? FC_TX : FC_NONE;
1691}
1692
1686static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) 1693static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1687{ 1694{
1688 struct sky2_hw *hw = sky2->hw; 1695 struct sky2_hw *hw = sky2->hw;
@@ -1703,39 +1710,20 @@ static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1703 } 1710 }
1704 1711
1705 sky2->speed = sky2_phy_speed(hw, aux); 1712 sky2->speed = sky2_phy_speed(hw, aux);
1706 if (sky2->speed == SPEED_1000) { 1713 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1707 u16 ctl2 = gm_phy_read(hw, port, PHY_MARV_1000T_CTRL);
1708 u16 lpa2 = gm_phy_read(hw, port, PHY_MARV_1000T_STAT);
1709 if (lpa2 & PHY_B_1000S_MSF) {
1710 printk(KERN_ERR PFX "%s: master/slave fault",
1711 sky2->netdev->name);
1712 return -1;
1713 }
1714
1715 if ((ctl2 & PHY_M_1000C_AFD) && (lpa2 & PHY_B_1000S_LP_FD))
1716 sky2->duplex = DUPLEX_FULL;
1717 else
1718 sky2->duplex = DUPLEX_HALF;
1719 } else {
1720 u16 adv = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1721 if ((aux & adv) & PHY_AN_FULL)
1722 sky2->duplex = DUPLEX_FULL;
1723 else
1724 sky2->duplex = DUPLEX_HALF;
1725 }
1726 1714
1727 /* Pause bits are offset (9..8) */ 1715 /* Pause bits are offset (9..8) */
1728 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) 1716 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
1729 aux >>= 6; 1717 aux >>= 6;
1730 1718
1731 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0; 1719 sky2->flow_status = sky2_flow(aux & PHY_M_PS_RX_P_EN,
1732 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0; 1720 aux & PHY_M_PS_TX_P_EN);
1733 1721
1734 if (sky2->duplex == DUPLEX_HALF && sky2->speed != SPEED_1000 1722 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1735 && hw->chip_id != CHIP_ID_YUKON_EC_U) 1723 && hw->chip_id != CHIP_ID_YUKON_EC_U)
1736 sky2->rx_pause = sky2->tx_pause = 0; 1724 sky2->flow_status = FC_NONE;
1737 1725
1738 if (sky2->rx_pause || sky2->tx_pause) 1726 if (aux & PHY_M_PS_RX_P_EN)
1739 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 1727 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1740 else 1728 else
1741 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 1729 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
@@ -1750,13 +1738,13 @@ static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1750 struct sky2_port *sky2 = netdev_priv(dev); 1738 struct sky2_port *sky2 = netdev_priv(dev);
1751 u16 istatus, phystat; 1739 u16 istatus, phystat;
1752 1740
1741 if (!netif_running(dev))
1742 return;
1743
1753 spin_lock(&sky2->phy_lock); 1744 spin_lock(&sky2->phy_lock);
1754 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); 1745 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1755 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 1746 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1756 1747
1757 if (!netif_running(dev))
1758 goto out;
1759
1760 if (netif_msg_intr(sky2)) 1748 if (netif_msg_intr(sky2))
1761 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", 1749 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1762 sky2->netdev->name, istatus, phystat); 1750 sky2->netdev->name, istatus, phystat);
@@ -2016,6 +2004,10 @@ oversize:
2016 2004
2017error: 2005error:
2018 ++sky2->net_stats.rx_errors; 2006 ++sky2->net_stats.rx_errors;
2007 if (status & GMR_FS_RX_FF_OV) {
2008 sky2->net_stats.rx_fifo_errors++;
2009 goto resubmit;
2010 }
2019 2011
2020 if (netif_msg_rx_err(sky2) && net_ratelimit()) 2012 if (netif_msg_rx_err(sky2) && net_ratelimit())
2021 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", 2013 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
@@ -2027,8 +2019,6 @@ error:
2027 sky2->net_stats.rx_frame_errors++; 2019 sky2->net_stats.rx_frame_errors++;
2028 if (status & GMR_FS_CRC_ERR) 2020 if (status & GMR_FS_CRC_ERR)
2029 sky2->net_stats.rx_crc_errors++; 2021 sky2->net_stats.rx_crc_errors++;
2030 if (status & GMR_FS_RX_FF_OV)
2031 sky2->net_stats.rx_fifo_errors++;
2032 2022
2033 goto resubmit; 2023 goto resubmit;
2034} 2024}
@@ -2075,7 +2065,7 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2075 case OP_RXSTAT: 2065 case OP_RXSTAT:
2076 skb = sky2_receive(dev, length, status); 2066 skb = sky2_receive(dev, length, status);
2077 if (!skb) 2067 if (!skb)
2078 break; 2068 goto force_update;
2079 2069
2080 skb->protocol = eth_type_trans(skb, dev); 2070 skb->protocol = eth_type_trans(skb, dev);
2081 dev->last_rx = jiffies; 2071 dev->last_rx = jiffies;
@@ -2091,8 +2081,8 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2091 2081
2092 /* Update receiver after 16 frames */ 2082 /* Update receiver after 16 frames */
2093 if (++buf_write[le->link] == RX_BUF_WRITE) { 2083 if (++buf_write[le->link] == RX_BUF_WRITE) {
2094 sky2_put_idx(hw, rxqaddr[le->link], 2084force_update:
2095 sky2->rx_put); 2085 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
2096 buf_write[le->link] = 0; 2086 buf_write[le->link] = 0;
2097 } 2087 }
2098 2088
@@ -2748,7 +2738,7 @@ static int sky2_nway_reset(struct net_device *dev)
2748{ 2738{
2749 struct sky2_port *sky2 = netdev_priv(dev); 2739 struct sky2_port *sky2 = netdev_priv(dev);
2750 2740
2751 if (sky2->autoneg != AUTONEG_ENABLE) 2741 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
2752 return -EINVAL; 2742 return -EINVAL;
2753 2743
2754 sky2_phy_reinit(sky2); 2744 sky2_phy_reinit(sky2);
@@ -2850,6 +2840,14 @@ static int sky2_set_mac_address(struct net_device *dev, void *p)
2850 return 0; 2840 return 0;
2851} 2841}
2852 2842
2843static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
2844{
2845 u32 bit;
2846
2847 bit = ether_crc(ETH_ALEN, addr) & 63;
2848 filter[bit >> 3] |= 1 << (bit & 7);
2849}
2850
2853static void sky2_set_multicast(struct net_device *dev) 2851static void sky2_set_multicast(struct net_device *dev)
2854{ 2852{
2855 struct sky2_port *sky2 = netdev_priv(dev); 2853 struct sky2_port *sky2 = netdev_priv(dev);
@@ -2858,7 +2856,10 @@ static void sky2_set_multicast(struct net_device *dev)
2858 struct dev_mc_list *list = dev->mc_list; 2856 struct dev_mc_list *list = dev->mc_list;
2859 u16 reg; 2857 u16 reg;
2860 u8 filter[8]; 2858 u8 filter[8];
2859 int rx_pause;
2860 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2861 2861
2862 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
2862 memset(filter, 0, sizeof(filter)); 2863 memset(filter, 0, sizeof(filter));
2863 2864
2864 reg = gma_read16(hw, port, GM_RX_CTRL); 2865 reg = gma_read16(hw, port, GM_RX_CTRL);
@@ -2866,18 +2867,19 @@ static void sky2_set_multicast(struct net_device *dev)
2866 2867
2867 if (dev->flags & IFF_PROMISC) /* promiscuous */ 2868 if (dev->flags & IFF_PROMISC) /* promiscuous */
2868 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 2869 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2869 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */ 2870 else if (dev->flags & IFF_ALLMULTI)
2870 memset(filter, 0xff, sizeof(filter)); 2871 memset(filter, 0xff, sizeof(filter));
2871 else if (dev->mc_count == 0) /* no multicast */ 2872 else if (dev->mc_count == 0 && !rx_pause)
2872 reg &= ~GM_RXCR_MCF_ENA; 2873 reg &= ~GM_RXCR_MCF_ENA;
2873 else { 2874 else {
2874 int i; 2875 int i;
2875 reg |= GM_RXCR_MCF_ENA; 2876 reg |= GM_RXCR_MCF_ENA;
2876 2877
2877 for (i = 0; list && i < dev->mc_count; i++, list = list->next) { 2878 if (rx_pause)
2878 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; 2879 sky2_add_filter(filter, pause_mc_addr);
2879 filter[bit / 8] |= 1 << (bit % 8); 2880
2880 } 2881 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2882 sky2_add_filter(filter, list->dmi_addr);
2881 } 2883 }
2882 2884
2883 gma_write16(hw, port, GM_MC_ADDR_H1, 2885 gma_write16(hw, port, GM_MC_ADDR_H1,
@@ -2990,8 +2992,20 @@ static void sky2_get_pauseparam(struct net_device *dev,
2990{ 2992{
2991 struct sky2_port *sky2 = netdev_priv(dev); 2993 struct sky2_port *sky2 = netdev_priv(dev);
2992 2994
2993 ecmd->tx_pause = sky2->tx_pause; 2995 switch (sky2->flow_mode) {
2994 ecmd->rx_pause = sky2->rx_pause; 2996 case FC_NONE:
2997 ecmd->tx_pause = ecmd->rx_pause = 0;
2998 break;
2999 case FC_TX:
3000 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3001 break;
3002 case FC_RX:
3003 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3004 break;
3005 case FC_BOTH:
3006 ecmd->tx_pause = ecmd->rx_pause = 1;
3007 }
3008
2995 ecmd->autoneg = sky2->autoneg; 3009 ecmd->autoneg = sky2->autoneg;
2996} 3010}
2997 3011
@@ -3001,10 +3015,10 @@ static int sky2_set_pauseparam(struct net_device *dev,
3001 struct sky2_port *sky2 = netdev_priv(dev); 3015 struct sky2_port *sky2 = netdev_priv(dev);
3002 3016
3003 sky2->autoneg = ecmd->autoneg; 3017 sky2->autoneg = ecmd->autoneg;
3004 sky2->tx_pause = ecmd->tx_pause != 0; 3018 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3005 sky2->rx_pause = ecmd->rx_pause != 0;
3006 3019
3007 sky2_phy_reinit(sky2); 3020 if (netif_running(dev))
3021 sky2_phy_reinit(sky2);
3008 3022
3009 return 0; 3023 return 0;
3010} 3024}
@@ -3224,7 +3238,11 @@ static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3224 dev->poll = sky2_poll; 3238 dev->poll = sky2_poll;
3225 dev->weight = NAPI_WEIGHT; 3239 dev->weight = NAPI_WEIGHT;
3226#ifdef CONFIG_NET_POLL_CONTROLLER 3240#ifdef CONFIG_NET_POLL_CONTROLLER
3227 dev->poll_controller = sky2_netpoll; 3241 /* Network console (only works on port 0)
3242 * because netpoll makes assumptions about NAPI
3243 */
3244 if (port == 0)
3245 dev->poll_controller = sky2_netpoll;
3228#endif 3246#endif
3229 3247
3230 sky2 = netdev_priv(dev); 3248 sky2 = netdev_priv(dev);
@@ -3234,8 +3252,8 @@ static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3234 3252
3235 /* Auto speed and flow control */ 3253 /* Auto speed and flow control */
3236 sky2->autoneg = AUTONEG_ENABLE; 3254 sky2->autoneg = AUTONEG_ENABLE;
3237 sky2->tx_pause = 1; 3255 sky2->flow_mode = FC_BOTH;
3238 sky2->rx_pause = 1; 3256
3239 sky2->duplex = -1; 3257 sky2->duplex = -1;
3240 sky2->speed = -1; 3258 sky2->speed = -1;
3241 sky2->advertising = sky2_supported_modes(hw); 3259 sky2->advertising = sky2_supported_modes(hw);
@@ -3293,7 +3311,7 @@ static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3293 return IRQ_NONE; 3311 return IRQ_NONE;
3294 3312
3295 if (status & Y2_IS_IRQ_SW) { 3313 if (status & Y2_IS_IRQ_SW) {
3296 hw->msi_detected = 1; 3314 hw->msi = 1;
3297 wake_up(&hw->msi_wait); 3315 wake_up(&hw->msi_wait);
3298 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 3316 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3299 } 3317 }
@@ -3312,7 +3330,7 @@ static int __devinit sky2_test_msi(struct sky2_hw *hw)
3312 3330
3313 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); 3331 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3314 3332
3315 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw); 3333 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3316 if (err) { 3334 if (err) {
3317 printk(KERN_ERR PFX "%s: cannot assign irq %d\n", 3335 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3318 pci_name(pdev), pdev->irq); 3336 pci_name(pdev), pdev->irq);
@@ -3322,13 +3340,12 @@ static int __devinit sky2_test_msi(struct sky2_hw *hw)
3322 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); 3340 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3323 sky2_read8(hw, B0_CTST); 3341 sky2_read8(hw, B0_CTST);
3324 3342
3325 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10); 3343 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
3326 3344
3327 if (!hw->msi_detected) { 3345 if (!hw->msi) {
3328 /* MSI test failed, go back to INTx mode */ 3346 /* MSI test failed, go back to INTx mode */
3329 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, " 3347 printk(KERN_INFO PFX "%s: No interrupt generated using MSI, "
3330 "switching to INTx mode. Please report this failure to " 3348 "switching to INTx mode.\n",
3331 "the PCI maintainer and include system chipset information.\n",
3332 pci_name(pdev)); 3349 pci_name(pdev));
3333 3350
3334 err = -EOPNOTSUPP; 3351 err = -EOPNOTSUPP;
@@ -3336,6 +3353,7 @@ static int __devinit sky2_test_msi(struct sky2_hw *hw)
3336 } 3353 }
3337 3354
3338 sky2_write32(hw, B0_IMSK, 0); 3355 sky2_write32(hw, B0_IMSK, 0);
3356 sky2_read32(hw, B0_IMSK);
3339 3357
3340 free_irq(pdev->irq, hw); 3358 free_irq(pdev->irq, hw);
3341 3359
@@ -3457,7 +3475,8 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
3457 goto err_out_free_netdev; 3475 goto err_out_free_netdev;
3458 } 3476 }
3459 3477
3460 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, dev->name, hw); 3478 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3479 dev->name, hw);
3461 if (err) { 3480 if (err) {
3462 printk(KERN_ERR PFX "%s: cannot assign irq %d\n", 3481 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3463 pci_name(pdev), pdev->irq); 3482 pci_name(pdev), pdev->irq);
@@ -3487,7 +3506,8 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
3487 return 0; 3506 return 0;
3488 3507
3489err_out_unregister: 3508err_out_unregister:
3490 pci_disable_msi(pdev); 3509 if (hw->msi)
3510 pci_disable_msi(pdev);
3491 unregister_netdev(dev); 3511 unregister_netdev(dev);
3492err_out_free_netdev: 3512err_out_free_netdev:
3493 free_netdev(dev); 3513 free_netdev(dev);
@@ -3530,7 +3550,8 @@ static void __devexit sky2_remove(struct pci_dev *pdev)
3530 sky2_read8(hw, B0_CTST); 3550 sky2_read8(hw, B0_CTST);
3531 3551
3532 free_irq(pdev->irq, hw); 3552 free_irq(pdev->irq, hw);
3533 pci_disable_msi(pdev); 3553 if (hw->msi)
3554 pci_disable_msi(pdev);
3534 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); 3555 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3535 pci_release_regions(pdev); 3556 pci_release_regions(pdev);
3536 pci_disable_device(pdev); 3557 pci_disable_device(pdev);