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-rw-r--r--drivers/net/sky2.c3038
1 files changed, 3038 insertions, 0 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
new file mode 100644
index 000000000000..e08695a2ca5a
--- /dev/null
+++ b/drivers/net/sky2.c
@@ -0,0 +1,3038 @@
1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
27 * TODO
28 * - coalescing setting?
29 *
30 * TOTEST
31 * - speed setting
32 * - suspend/resume
33 */
34
35#include <linux/config.h>
36#include <linux/crc32.h>
37#include <linux/kernel.h>
38#include <linux/version.h>
39#include <linux/module.h>
40#include <linux/netdevice.h>
41#include <linux/etherdevice.h>
42#include <linux/ethtool.h>
43#include <linux/pci.h>
44#include <linux/ip.h>
45#include <linux/tcp.h>
46#include <linux/in.h>
47#include <linux/delay.h>
48#include <linux/if_vlan.h>
49
50#include <asm/irq.h>
51
52#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
53#define SKY2_VLAN_TAG_USED 1
54#endif
55
56#include "sky2.h"
57
58#define DRV_NAME "sky2"
59#define DRV_VERSION "0.7"
60#define PFX DRV_NAME " "
61
62/*
63 * The Yukon II chipset takes 64 bit command blocks (called list elements)
64 * that are organized into three (receive, transmit, status) different rings
65 * similar to Tigon3. A transmit can require several elements;
66 * a receive requires one (or two if using 64 bit dma).
67 */
68
69#ifdef CONFIG_SKY2_EC_A1
70#define is_ec_a1(hw) \
71 ((hw)->chip_id == CHIP_ID_YUKON_EC && \
72 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
73#else
74#define is_ec_a1(hw) 0
75#endif
76
77#define RX_LE_SIZE 256
78#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
79#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
80#define RX_DEF_PENDING 128
81#define RX_COPY_THRESHOLD 256
82
83#define TX_RING_SIZE 512
84#define TX_DEF_PENDING (TX_RING_SIZE - 1)
85#define TX_MIN_PENDING 64
86#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
87
88#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
89#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
90#define ETH_JUMBO_MTU 9000
91#define TX_WATCHDOG (5 * HZ)
92#define NAPI_WEIGHT 64
93#define PHY_RETRIES 1000
94
95static const u32 default_msg =
96 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
97 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
98 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
99
100static int debug = -1; /* defaults above */
101module_param(debug, int, 0);
102MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
103
104static const struct pci_device_id sky2_id_table[] = {
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
122 { 0 }
123};
124
125MODULE_DEVICE_TABLE(pci, sky2_id_table);
126
127/* Avoid conditionals by using array */
128static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
129static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
130
131static const char *yukon_name[] = {
132 [CHIP_ID_YUKON_LITE - CHIP_ID_YUKON] = "Lite", /* 0xb0 */
133 [CHIP_ID_YUKON_LP - CHIP_ID_YUKON] = "LP", /* 0xb2 */
134 [CHIP_ID_YUKON_XL - CHIP_ID_YUKON] = "XL", /* 0xb3 */
135
136 [CHIP_ID_YUKON_EC - CHIP_ID_YUKON] = "EC", /* 0xb6 */
137 [CHIP_ID_YUKON_FE - CHIP_ID_YUKON] = "FE", /* 0xb7 */
138};
139
140
141/* Access to external PHY */
142static void gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
143{
144 int i;
145
146 gma_write16(hw, port, GM_SMI_DATA, val);
147 gma_write16(hw, port, GM_SMI_CTRL,
148 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
149
150 for (i = 0; i < PHY_RETRIES; i++) {
151 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
152 return;
153 udelay(1);
154 }
155 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
156}
157
158static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
159{
160 int i;
161
162 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
163 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
164
165 for (i = 0; i < PHY_RETRIES; i++) {
166 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
167 goto ready;
168 udelay(1);
169 }
170
171 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
172ready:
173 return gma_read16(hw, port, GM_SMI_DATA);
174}
175
176static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
177{
178 u16 power_control;
179 u32 reg1;
180 int vaux;
181 int ret = 0;
182
183 pr_debug("sky2_set_power_state %d\n", state);
184 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
185
186 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
187 vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
188 (power_control & PCI_PM_CAP_PME_D3cold);
189
190 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
191
192 power_control |= PCI_PM_CTRL_PME_STATUS;
193 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
194
195 switch (state) {
196 case PCI_D0:
197 /* switch power to VCC (WA for VAUX problem) */
198 sky2_write8(hw, B0_POWER_CTRL,
199 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
200
201 /* disable Core Clock Division, */
202 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
203
204 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
205 /* enable bits are inverted */
206 sky2_write8(hw, B2_Y2_CLK_GATE,
207 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
208 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
209 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
210 else
211 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
212
213 /* Turn off phy power saving */
214 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
215 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
216
217 /* looks like this XL is back asswards .. */
218 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
219 reg1 |= PCI_Y2_PHY1_COMA;
220 if (hw->ports > 1)
221 reg1 |= PCI_Y2_PHY2_COMA;
222 }
223 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
224 break;
225
226 case PCI_D3hot:
227 case PCI_D3cold:
228 /* Turn on phy power saving */
229 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
230 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
231 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
232 else
233 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
234 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
235
236 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
237 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
238 else
239 /* enable bits are inverted */
240 sky2_write8(hw, B2_Y2_CLK_GATE,
241 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
242 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
243 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
244
245 /* switch power to VAUX */
246 if (vaux && state != PCI_D3cold)
247 sky2_write8(hw, B0_POWER_CTRL,
248 (PC_VAUX_ENA | PC_VCC_ENA |
249 PC_VAUX_ON | PC_VCC_OFF));
250 break;
251 default:
252 printk(KERN_ERR PFX "Unknown power state %d\n", state);
253 ret = -1;
254 }
255
256 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
257 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
258 return ret;
259}
260
261static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
262{
263 u16 reg;
264
265 /* disable all GMAC IRQ's */
266 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
267 /* disable PHY IRQs */
268 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
269
270 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
271 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
272 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
273 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
274
275 reg = gma_read16(hw, port, GM_RX_CTRL);
276 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
277 gma_write16(hw, port, GM_RX_CTRL, reg);
278}
279
280static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
281{
282 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
283 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
284
285 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
286 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
287
288 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
289 PHY_M_EC_MAC_S_MSK);
290 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
291
292 if (hw->chip_id == CHIP_ID_YUKON_EC)
293 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
294 else
295 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
296
297 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
298 }
299
300 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
301 if (hw->copper) {
302 if (hw->chip_id == CHIP_ID_YUKON_FE) {
303 /* enable automatic crossover */
304 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
305 } else {
306 /* disable energy detect */
307 ctrl &= ~PHY_M_PC_EN_DET_MSK;
308
309 /* enable automatic crossover */
310 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
311
312 if (sky2->autoneg == AUTONEG_ENABLE &&
313 hw->chip_id == CHIP_ID_YUKON_XL) {
314 ctrl &= ~PHY_M_PC_DSC_MSK;
315 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
316 }
317 }
318 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
319 } else {
320 /* workaround for deviation #4.88 (CRC errors) */
321 /* disable Automatic Crossover */
322
323 ctrl &= ~PHY_M_PC_MDIX_MSK;
324 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
325
326 if (hw->chip_id == CHIP_ID_YUKON_XL) {
327 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
328 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
329 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
330 ctrl &= ~PHY_M_MAC_MD_MSK;
331 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
332 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
333
334 /* select page 1 to access Fiber registers */
335 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
336 }
337 }
338
339 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
340 if (sky2->autoneg == AUTONEG_DISABLE)
341 ctrl &= ~PHY_CT_ANE;
342 else
343 ctrl |= PHY_CT_ANE;
344
345 ctrl |= PHY_CT_RESET;
346 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
347
348 ctrl = 0;
349 ct1000 = 0;
350 adv = PHY_AN_CSMA;
351
352 if (sky2->autoneg == AUTONEG_ENABLE) {
353 if (hw->copper) {
354 if (sky2->advertising & ADVERTISED_1000baseT_Full)
355 ct1000 |= PHY_M_1000C_AFD;
356 if (sky2->advertising & ADVERTISED_1000baseT_Half)
357 ct1000 |= PHY_M_1000C_AHD;
358 if (sky2->advertising & ADVERTISED_100baseT_Full)
359 adv |= PHY_M_AN_100_FD;
360 if (sky2->advertising & ADVERTISED_100baseT_Half)
361 adv |= PHY_M_AN_100_HD;
362 if (sky2->advertising & ADVERTISED_10baseT_Full)
363 adv |= PHY_M_AN_10_FD;
364 if (sky2->advertising & ADVERTISED_10baseT_Half)
365 adv |= PHY_M_AN_10_HD;
366 } else /* special defines for FIBER (88E1011S only) */
367 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
368
369 /* Set Flow-control capabilities */
370 if (sky2->tx_pause && sky2->rx_pause)
371 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
372 else if (sky2->rx_pause && !sky2->tx_pause)
373 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
374 else if (!sky2->rx_pause && sky2->tx_pause)
375 adv |= PHY_AN_PAUSE_ASYM; /* local */
376
377 /* Restart Auto-negotiation */
378 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
379 } else {
380 /* forced speed/duplex settings */
381 ct1000 = PHY_M_1000C_MSE;
382
383 if (sky2->duplex == DUPLEX_FULL)
384 ctrl |= PHY_CT_DUP_MD;
385
386 switch (sky2->speed) {
387 case SPEED_1000:
388 ctrl |= PHY_CT_SP1000;
389 break;
390 case SPEED_100:
391 ctrl |= PHY_CT_SP100;
392 break;
393 }
394
395 ctrl |= PHY_CT_RESET;
396 }
397
398 if (hw->chip_id != CHIP_ID_YUKON_FE)
399 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
400
401 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
402 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
403
404 /* Setup Phy LED's */
405 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
406 ledover = 0;
407
408 switch (hw->chip_id) {
409 case CHIP_ID_YUKON_FE:
410 /* on 88E3082 these bits are at 11..9 (shifted left) */
411 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
412
413 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
414
415 /* delete ACT LED control bits */
416 ctrl &= ~PHY_M_FELP_LED1_MSK;
417 /* change ACT LED control to blink mode */
418 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
419 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
420 break;
421
422 case CHIP_ID_YUKON_XL:
423 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
424
425 /* select page 3 to access LED control register */
426 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
427
428 /* set LED Function Control register */
429 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
430 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
431 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
432 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
433
434 /* set Polarity Control register */
435 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
436 (PHY_M_POLC_LS1_P_MIX(4) |
437 PHY_M_POLC_IS0_P_MIX(4) |
438 PHY_M_POLC_LOS_CTRL(2) |
439 PHY_M_POLC_INIT_CTRL(2) |
440 PHY_M_POLC_STA1_CTRL(2) |
441 PHY_M_POLC_STA0_CTRL(2)));
442
443 /* restore page register */
444 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
445 break;
446
447 default:
448 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
449 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
450 /* turn off the Rx LED (LED_RX) */
451 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
452 }
453
454 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
455
456 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
457 /* turn on 100 Mbps LED (LED_LINK100) */
458 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
459 }
460
461 if (ledover)
462 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
463
464 /* Enable phy interrupt on auto-negotiation complete (or link up) */
465 if (sky2->autoneg == AUTONEG_ENABLE)
466 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
467 else
468 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
469}
470
471static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
472{
473 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
474 u16 reg;
475 int i;
476 const u8 *addr = hw->dev[port]->dev_addr;
477
478 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
479 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
480
481 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
482
483 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
484 /* WA DEV_472 -- looks like crossed wires on port 2 */
485 /* clear GMAC 1 Control reset */
486 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
487 do {
488 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
489 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
490 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
491 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
492 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
493 }
494
495 if (sky2->autoneg == AUTONEG_DISABLE) {
496 reg = gma_read16(hw, port, GM_GP_CTRL);
497 reg |= GM_GPCR_AU_ALL_DIS;
498 gma_write16(hw, port, GM_GP_CTRL, reg);
499 gma_read16(hw, port, GM_GP_CTRL);
500
501 switch (sky2->speed) {
502 case SPEED_1000:
503 reg |= GM_GPCR_SPEED_1000;
504 /* fallthru */
505 case SPEED_100:
506 reg |= GM_GPCR_SPEED_100;
507 }
508
509 if (sky2->duplex == DUPLEX_FULL)
510 reg |= GM_GPCR_DUP_FULL;
511 } else
512 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
513
514 if (!sky2->tx_pause && !sky2->rx_pause) {
515 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
516 reg |=
517 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
518 } else if (sky2->tx_pause && !sky2->rx_pause) {
519 /* disable Rx flow-control */
520 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
521 }
522
523 gma_write16(hw, port, GM_GP_CTRL, reg);
524
525 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
526
527 spin_lock_bh(&hw->phy_lock);
528 sky2_phy_init(hw, port);
529 spin_unlock_bh(&hw->phy_lock);
530
531 /* MIB clear */
532 reg = gma_read16(hw, port, GM_PHY_ADDR);
533 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
534
535 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
536 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
537 gma_write16(hw, port, GM_PHY_ADDR, reg);
538
539 /* transmit control */
540 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
541
542 /* receive control reg: unicast + multicast + no FCS */
543 gma_write16(hw, port, GM_RX_CTRL,
544 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
545
546 /* transmit flow control */
547 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
548
549 /* transmit parameter */
550 gma_write16(hw, port, GM_TX_PARAM,
551 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
552 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
553 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
554 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
555
556 /* serial mode register */
557 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
558 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
559
560 if (hw->dev[port]->mtu > ETH_DATA_LEN)
561 reg |= GM_SMOD_JUMBO_ENA;
562
563 gma_write16(hw, port, GM_SERIAL_MODE, reg);
564
565 /* virtual address for data */
566 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
567
568 /* physical address: used for pause frames */
569 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
570
571 /* ignore counter overflows */
572 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
573 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
574 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
575
576 /* Configure Rx MAC FIFO */
577 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
578 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
579 GMF_RX_CTRL_DEF);
580
581 /* Flush Rx MAC FIFO on any flow control or error */
582 reg = GMR_FS_ANY_ERR;
583 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1)
584 reg = 0; /* WA dev #4.115 */
585
586 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg);
587 /* Set threshold to 0xa (64 bytes)
588 * ASF disabled so no need to do WA dev #4.30
589 */
590 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
591
592 /* Configure Tx MAC FIFO */
593 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
594 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
595}
596
597static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
598{
599 u32 end;
600
601 start /= 8;
602 len /= 8;
603 end = start + len - 1;
604
605 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
606 sky2_write32(hw, RB_ADDR(q, RB_START), start);
607 sky2_write32(hw, RB_ADDR(q, RB_END), end);
608 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
609 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
610
611 if (q == Q_R1 || q == Q_R2) {
612 u32 rxup, rxlo;
613
614 rxlo = len/2;
615 rxup = rxlo + len/4;
616
617 /* Set thresholds on receive queue's */
618 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
619 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
620 } else {
621 /* Enable store & forward on Tx queue's because
622 * Tx FIFO is only 1K on Yukon
623 */
624 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
625 }
626
627 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
628 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
629}
630
631/* Setup Bus Memory Interface */
632static void sky2_qset(struct sky2_hw *hw, u16 q, u32 wm)
633{
634 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
635 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
636 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
637 sky2_write32(hw, Q_ADDR(q, Q_WM), wm);
638}
639
640/* Setup prefetch unit registers. This is the interface between
641 * hardware and driver list elements
642 */
643static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
644 u64 addr, u32 last)
645{
646 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
647 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
648 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
649 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
650 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
651 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
652
653 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
654}
655
656static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
657{
658 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
659
660 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
661 return le;
662}
663
664/*
665 * This is a workaround code taken from SysKonnect sk98lin driver
666 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
667 */
668static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
669 u16 idx, u16 *last, u16 size)
670{
671 if (is_ec_a1(hw) && idx < *last) {
672 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
673
674 if (hwget == 0) {
675 /* Start prefetching again */
676 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
677 goto setnew;
678 }
679
680 if (hwget == size - 1) {
681 /* set watermark to one list element */
682 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
683
684 /* set put index to first list element */
685 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
686 } else /* have hardware go to end of list */
687 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
688 size - 1);
689 } else {
690setnew:
691 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
692 }
693 *last = idx;
694}
695
696
697static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
698{
699 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
700 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
701 return le;
702}
703
704/* Build description to hardware about buffer */
705static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re)
706{
707 struct sky2_rx_le *le;
708 u32 hi = (re->mapaddr >> 16) >> 16;
709
710 re->idx = sky2->rx_put;
711 if (sky2->rx_addr64 != hi) {
712 le = sky2_next_rx(sky2);
713 le->addr = cpu_to_le32(hi);
714 le->ctrl = 0;
715 le->opcode = OP_ADDR64 | HW_OWNER;
716 sky2->rx_addr64 = hi;
717 }
718
719 le = sky2_next_rx(sky2);
720 le->addr = cpu_to_le32((u32) re->mapaddr);
721 le->length = cpu_to_le16(re->maplen);
722 le->ctrl = 0;
723 le->opcode = OP_PACKET | HW_OWNER;
724}
725
726
727/* Tell chip where to start receive checksum.
728 * Actually has two checksums, but set both same to avoid possible byte
729 * order problems.
730 */
731static void rx_set_checksum(struct sky2_port *sky2)
732{
733 struct sky2_rx_le *le;
734
735 le = sky2_next_rx(sky2);
736 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
737 le->ctrl = 0;
738 le->opcode = OP_TCPSTART | HW_OWNER;
739
740 sky2_write32(sky2->hw,
741 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
742 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
743
744}
745
746/*
747 * The RX Stop command will not work for Yukon-2 if the BMU does not
748 * reach the end of packet and since we can't make sure that we have
749 * incoming data, we must reset the BMU while it is not doing a DMA
750 * transfer. Since it is possible that the RX path is still active,
751 * the RX RAM buffer will be stopped first, so any possible incoming
752 * data will not trigger a DMA. After the RAM buffer is stopped, the
753 * BMU is polled until any DMA in progress is ended and only then it
754 * will be reset.
755 */
756static void sky2_rx_stop(struct sky2_port *sky2)
757{
758 struct sky2_hw *hw = sky2->hw;
759 unsigned rxq = rxqaddr[sky2->port];
760 int i;
761
762 /* disable the RAM Buffer receive queue */
763 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
764
765 for (i = 0; i < 0xffff; i++)
766 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
767 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
768 goto stopped;
769
770 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
771 sky2->netdev->name);
772stopped:
773 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
774
775 /* reset the Rx prefetch unit */
776 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
777}
778
779/* Clean out receive buffer area, assumes receiver hardware stopped */
780static void sky2_rx_clean(struct sky2_port *sky2)
781{
782 unsigned i;
783
784 memset(sky2->rx_le, 0, RX_LE_BYTES);
785 for (i = 0; i < sky2->rx_pending; i++) {
786 struct ring_info *re = sky2->rx_ring + i;
787
788 if (re->skb) {
789 pci_unmap_single(sky2->hw->pdev,
790 re->mapaddr, re->maplen,
791 PCI_DMA_FROMDEVICE);
792 kfree_skb(re->skb);
793 re->skb = NULL;
794 }
795 }
796}
797
798#ifdef SKY2_VLAN_TAG_USED
799static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
800{
801 struct sky2_port *sky2 = netdev_priv(dev);
802 struct sky2_hw *hw = sky2->hw;
803 u16 port = sky2->port;
804 unsigned long flags;
805
806 spin_lock_irqsave(&sky2->tx_lock, flags);
807
808 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
809 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
810 sky2->vlgrp = grp;
811
812 spin_unlock_irqrestore(&sky2->tx_lock, flags);
813}
814
815static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
816{
817 struct sky2_port *sky2 = netdev_priv(dev);
818 struct sky2_hw *hw = sky2->hw;
819 u16 port = sky2->port;
820 unsigned long flags;
821
822 spin_lock_irqsave(&sky2->tx_lock, flags);
823
824 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
825 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
826 if (sky2->vlgrp)
827 sky2->vlgrp->vlan_devices[vid] = NULL;
828
829 spin_unlock_irqrestore(&sky2->tx_lock, flags);
830}
831#endif
832
833#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
834static inline unsigned rx_size(const struct sky2_port *sky2)
835{
836 return roundup(sky2->netdev->mtu + ETH_HLEN + 4, 8);
837}
838
839/*
840 * Allocate and setup receiver buffer pool.
841 * In case of 64 bit dma, there are 2X as many list elements
842 * available as ring entries
843 * and need to reserve one list element so we don't wrap around.
844 *
845 * It appears the hardware has a bug in the FIFO logic that
846 * cause it to hang if the FIFO gets overrun and the receive buffer
847 * is not aligned. This means we can't use skb_reserve to align
848 * the IP header.
849 */
850static int sky2_rx_start(struct sky2_port *sky2)
851{
852 struct sky2_hw *hw = sky2->hw;
853 unsigned size = rx_size(sky2);
854 unsigned rxq = rxqaddr[sky2->port];
855 int i;
856
857 sky2->rx_put = sky2->rx_next = 0;
858 sky2_qset(hw, rxq, is_pciex(hw) ? 0x80 : 0x600);
859 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
860
861 rx_set_checksum(sky2);
862 for (i = 0; i < sky2->rx_pending; i++) {
863 struct ring_info *re = sky2->rx_ring + i;
864
865 re->skb = dev_alloc_skb(size);
866 if (!re->skb)
867 goto nomem;
868
869 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
870 size, PCI_DMA_FROMDEVICE);
871 re->maplen = size;
872 sky2_rx_add(sky2, re);
873 }
874
875 /* Tell chip about available buffers */
876 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
877 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
878 return 0;
879nomem:
880 sky2_rx_clean(sky2);
881 return -ENOMEM;
882}
883
884/* Bring up network interface. */
885static int sky2_up(struct net_device *dev)
886{
887 struct sky2_port *sky2 = netdev_priv(dev);
888 struct sky2_hw *hw = sky2->hw;
889 unsigned port = sky2->port;
890 u32 ramsize, rxspace;
891 int err = -ENOMEM;
892
893 if (netif_msg_ifup(sky2))
894 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
895
896 /* must be power of 2 */
897 sky2->tx_le = pci_alloc_consistent(hw->pdev,
898 TX_RING_SIZE *
899 sizeof(struct sky2_tx_le),
900 &sky2->tx_le_map);
901 if (!sky2->tx_le)
902 goto err_out;
903
904 sky2->tx_ring = kzalloc(TX_RING_SIZE * sizeof(struct ring_info),
905 GFP_KERNEL);
906 if (!sky2->tx_ring)
907 goto err_out;
908 sky2->tx_prod = sky2->tx_cons = 0;
909
910 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
911 &sky2->rx_le_map);
912 if (!sky2->rx_le)
913 goto err_out;
914 memset(sky2->rx_le, 0, RX_LE_BYTES);
915
916 sky2->rx_ring = kzalloc(sky2->rx_pending * sizeof(struct ring_info),
917 GFP_KERNEL);
918 if (!sky2->rx_ring)
919 goto err_out;
920
921 sky2_mac_init(hw, port);
922
923 /* Configure RAM buffers */
924 if (hw->chip_id == CHIP_ID_YUKON_FE ||
925 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
926 ramsize = 4096;
927 else {
928 u8 e0 = sky2_read8(hw, B2_E_0);
929 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
930 }
931
932 /* 2/3 for Rx */
933 rxspace = (2 * ramsize) / 3;
934 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
935 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
936
937 /* Make sure SyncQ is disabled */
938 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
939 RB_RST_SET);
940
941 sky2_qset(hw, txqaddr[port], 0x600);
942 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
943 TX_RING_SIZE - 1);
944
945 err = sky2_rx_start(sky2);
946 if (err)
947 goto err_out;
948
949 /* Enable interrupts from phy/mac for port */
950 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
951 sky2_write32(hw, B0_IMSK, hw->intr_mask);
952 return 0;
953
954err_out:
955 if (sky2->rx_le)
956 pci_free_consistent(hw->pdev, RX_LE_BYTES,
957 sky2->rx_le, sky2->rx_le_map);
958 if (sky2->tx_le)
959 pci_free_consistent(hw->pdev,
960 TX_RING_SIZE * sizeof(struct sky2_tx_le),
961 sky2->tx_le, sky2->tx_le_map);
962 if (sky2->tx_ring)
963 kfree(sky2->tx_ring);
964 if (sky2->rx_ring)
965 kfree(sky2->rx_ring);
966
967 return err;
968}
969
970/* Modular subtraction in ring */
971static inline int tx_dist(unsigned tail, unsigned head)
972{
973 return (head >= tail ? head : head + TX_RING_SIZE) - tail;
974}
975
976/* Number of list elements available for next tx */
977static inline int tx_avail(const struct sky2_port *sky2)
978{
979 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
980}
981
982/* Estimate of number of transmit list elements required */
983static inline unsigned tx_le_req(const struct sk_buff *skb)
984{
985 unsigned count;
986
987 count = sizeof(dma_addr_t) / sizeof(u32);
988 count += skb_shinfo(skb)->nr_frags * count;
989
990 if (skb_shinfo(skb)->tso_size)
991 ++count;
992
993 if (skb->ip_summed)
994 ++count;
995
996 return count;
997}
998
999/*
1000 * Put one packet in ring for transmit.
1001 * A single packet can generate multiple list elements, and
1002 * the number of ring elements will probably be less than the number
1003 * of list elements used.
1004 */
1005static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1006{
1007 struct sky2_port *sky2 = netdev_priv(dev);
1008 struct sky2_hw *hw = sky2->hw;
1009 struct sky2_tx_le *le = NULL;
1010 struct ring_info *re;
1011 unsigned long flags;
1012 unsigned i, len;
1013 dma_addr_t mapping;
1014 u32 addr64;
1015 u16 mss;
1016 u8 ctrl;
1017
1018 local_irq_save(flags);
1019 if (!spin_trylock(&sky2->tx_lock)) {
1020 local_irq_restore(flags);
1021 return NETDEV_TX_LOCKED;
1022 }
1023
1024 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1025 netif_stop_queue(dev);
1026 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1027
1028 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1029 dev->name);
1030 return NETDEV_TX_BUSY;
1031 }
1032
1033 if (unlikely(netif_msg_tx_queued(sky2)))
1034 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1035 dev->name, sky2->tx_prod, skb->len);
1036
1037 len = skb_headlen(skb);
1038 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1039 addr64 = (mapping >> 16) >> 16;
1040
1041 re = sky2->tx_ring + sky2->tx_prod;
1042
1043 /* Send high bits if changed */
1044 if (addr64 != sky2->tx_addr64) {
1045 le = get_tx_le(sky2);
1046 le->tx.addr = cpu_to_le32(addr64);
1047 le->ctrl = 0;
1048 le->opcode = OP_ADDR64 | HW_OWNER;
1049 sky2->tx_addr64 = addr64;
1050 }
1051
1052 /* Check for TCP Segmentation Offload */
1053 mss = skb_shinfo(skb)->tso_size;
1054 if (mss != 0) {
1055 /* just drop the packet if non-linear expansion fails */
1056 if (skb_header_cloned(skb) &&
1057 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1058 dev_kfree_skb_any(skb);
1059 goto out_unlock;
1060 }
1061
1062 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1063 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1064 mss += ETH_HLEN;
1065 }
1066
1067 if (mss != sky2->tx_last_mss) {
1068 le = get_tx_le(sky2);
1069 le->tx.tso.size = cpu_to_le16(mss);
1070 le->tx.tso.rsvd = 0;
1071 le->opcode = OP_LRGLEN | HW_OWNER;
1072 le->ctrl = 0;
1073 sky2->tx_last_mss = mss;
1074 }
1075
1076 ctrl = 0;
1077#ifdef SKY2_VLAN_TAG_USED
1078 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1079 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1080 if (!le) {
1081 le = get_tx_le(sky2);
1082 le->tx.addr = 0;
1083 le->opcode = OP_VLAN|HW_OWNER;
1084 le->ctrl = 0;
1085 } else
1086 le->opcode |= OP_VLAN;
1087 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1088 ctrl |= INS_VLAN;
1089 }
1090#endif
1091
1092 /* Handle TCP checksum offload */
1093 if (skb->ip_summed == CHECKSUM_HW) {
1094 u16 hdr = skb->h.raw - skb->data;
1095 u16 offset = hdr + skb->csum;
1096
1097 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1098 if (skb->nh.iph->protocol == IPPROTO_UDP)
1099 ctrl |= UDPTCP;
1100
1101 le = get_tx_le(sky2);
1102 le->tx.csum.start = cpu_to_le16(hdr);
1103 le->tx.csum.offset = cpu_to_le16(offset);
1104 le->length = 0; /* initial checksum value */
1105 le->ctrl = 1; /* one packet */
1106 le->opcode = OP_TCPLISW | HW_OWNER;
1107 }
1108
1109 le = get_tx_le(sky2);
1110 le->tx.addr = cpu_to_le32((u32) mapping);
1111 le->length = cpu_to_le16(len);
1112 le->ctrl = ctrl;
1113 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1114
1115 /* Record the transmit mapping info */
1116 re->skb = skb;
1117 re->mapaddr = mapping;
1118 re->maplen = len;
1119
1120 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1121 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1122 struct ring_info *fre;
1123
1124 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1125 frag->size, PCI_DMA_TODEVICE);
1126 addr64 = (mapping >> 16) >> 16;
1127 if (addr64 != sky2->tx_addr64) {
1128 le = get_tx_le(sky2);
1129 le->tx.addr = cpu_to_le32(addr64);
1130 le->ctrl = 0;
1131 le->opcode = OP_ADDR64 | HW_OWNER;
1132 sky2->tx_addr64 = addr64;
1133 }
1134
1135 le = get_tx_le(sky2);
1136 le->tx.addr = cpu_to_le32((u32) mapping);
1137 le->length = cpu_to_le16(frag->size);
1138 le->ctrl = ctrl;
1139 le->opcode = OP_BUFFER | HW_OWNER;
1140
1141 fre = sky2->tx_ring
1142 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1143 fre->skb = NULL;
1144 fre->mapaddr = mapping;
1145 fre->maplen = frag->size;
1146 }
1147 re->idx = sky2->tx_prod;
1148 le->ctrl |= EOP;
1149
1150 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1151 &sky2->tx_last_put, TX_RING_SIZE);
1152
1153 if (tx_avail(sky2) < MAX_SKB_TX_LE + 1)
1154 netif_stop_queue(dev);
1155
1156out_unlock:
1157 mmiowb();
1158 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1159
1160 dev->trans_start = jiffies;
1161 return NETDEV_TX_OK;
1162}
1163
1164/*
1165 * Free ring elements from starting at tx_cons until "done"
1166 *
1167 * NB: the hardware will tell us about partial completion of multi-part
1168 * buffers; these are deferred until completion.
1169 */
1170static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1171{
1172 struct net_device *dev = sky2->netdev;
1173 unsigned i;
1174
1175 if (unlikely(netif_msg_tx_done(sky2)))
1176 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1177 dev->name, done);
1178
1179 spin_lock(&sky2->tx_lock);
1180
1181 while (sky2->tx_cons != done) {
1182 struct ring_info *re = sky2->tx_ring + sky2->tx_cons;
1183 struct sk_buff *skb;
1184
1185 /* Check for partial status */
1186 if (tx_dist(sky2->tx_cons, done)
1187 < tx_dist(sky2->tx_cons, re->idx))
1188 goto out;
1189
1190 skb = re->skb;
1191 pci_unmap_single(sky2->hw->pdev,
1192 re->mapaddr, re->maplen, PCI_DMA_TODEVICE);
1193
1194 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1195 struct ring_info *fre;
1196 fre =
1197 sky2->tx_ring + (sky2->tx_cons + i +
1198 1) % TX_RING_SIZE;
1199 pci_unmap_page(sky2->hw->pdev, fre->mapaddr,
1200 fre->maplen, PCI_DMA_TODEVICE);
1201 }
1202
1203 dev_kfree_skb_any(skb);
1204
1205 sky2->tx_cons = re->idx;
1206 }
1207out:
1208
1209 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1210 netif_wake_queue(dev);
1211 spin_unlock(&sky2->tx_lock);
1212}
1213
1214/* Cleanup all untransmitted buffers, assume transmitter not running */
1215static inline void sky2_tx_clean(struct sky2_port *sky2)
1216{
1217 sky2_tx_complete(sky2, sky2->tx_prod);
1218}
1219
1220/* Network shutdown */
1221static int sky2_down(struct net_device *dev)
1222{
1223 struct sky2_port *sky2 = netdev_priv(dev);
1224 struct sky2_hw *hw = sky2->hw;
1225 unsigned port = sky2->port;
1226 u16 ctrl;
1227
1228 if (netif_msg_ifdown(sky2))
1229 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1230
1231 netif_stop_queue(dev);
1232
1233 sky2_phy_reset(hw, port);
1234
1235 /* Stop transmitter */
1236 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1237 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1238
1239 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1240 RB_RST_SET | RB_DIS_OP_MD);
1241
1242 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1243 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1244 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1245
1246 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1247
1248 /* Workaround shared GMAC reset */
1249 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1250 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1251 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1252
1253 /* Disable Force Sync bit and Enable Alloc bit */
1254 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1255 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1256
1257 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1258 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1259 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1260
1261 /* Reset the PCI FIFO of the async Tx queue */
1262 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1263 BMU_RST_SET | BMU_FIFO_RST);
1264
1265 /* Reset the Tx prefetch units */
1266 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1267 PREF_UNIT_RST_SET);
1268
1269 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1270
1271 sky2_rx_stop(sky2);
1272
1273 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1274 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1275
1276 /* turn off LED's */
1277 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1278
1279 sky2_tx_clean(sky2);
1280 sky2_rx_clean(sky2);
1281
1282 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1283 sky2->rx_le, sky2->rx_le_map);
1284 kfree(sky2->rx_ring);
1285
1286 pci_free_consistent(hw->pdev,
1287 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1288 sky2->tx_le, sky2->tx_le_map);
1289 kfree(sky2->tx_ring);
1290
1291 return 0;
1292}
1293
1294static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1295{
1296 if (!hw->copper)
1297 return SPEED_1000;
1298
1299 if (hw->chip_id == CHIP_ID_YUKON_FE)
1300 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1301
1302 switch (aux & PHY_M_PS_SPEED_MSK) {
1303 case PHY_M_PS_SPEED_1000:
1304 return SPEED_1000;
1305 case PHY_M_PS_SPEED_100:
1306 return SPEED_100;
1307 default:
1308 return SPEED_10;
1309 }
1310}
1311
1312static void sky2_link_up(struct sky2_port *sky2)
1313{
1314 struct sky2_hw *hw = sky2->hw;
1315 unsigned port = sky2->port;
1316 u16 reg;
1317
1318 /* disable Rx GMAC FIFO flush mode */
1319 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RX_F_FL_OFF);
1320
1321 /* Enable Transmit FIFO Underrun */
1322 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1323
1324 reg = gma_read16(hw, port, GM_GP_CTRL);
1325 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1326 reg |= GM_GPCR_DUP_FULL;
1327
1328 /* enable Rx/Tx */
1329 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1330 gma_write16(hw, port, GM_GP_CTRL, reg);
1331 gma_read16(hw, port, GM_GP_CTRL);
1332
1333 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1334
1335 netif_carrier_on(sky2->netdev);
1336 netif_wake_queue(sky2->netdev);
1337
1338 /* Turn on link LED */
1339 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1340 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1341
1342 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1343 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1344
1345 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1347 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1348 SPEED_10 ? 7 : 0) |
1349 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1350 SPEED_100 ? 7 : 0) |
1351 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1352 SPEED_1000 ? 7 : 0));
1353 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1354 }
1355
1356 if (netif_msg_link(sky2))
1357 printk(KERN_INFO PFX
1358 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1359 sky2->netdev->name, sky2->speed,
1360 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1361 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1362 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1363}
1364
1365static void sky2_link_down(struct sky2_port *sky2)
1366{
1367 struct sky2_hw *hw = sky2->hw;
1368 unsigned port = sky2->port;
1369 u16 reg;
1370
1371 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1372
1373 reg = gma_read16(hw, port, GM_GP_CTRL);
1374 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1375 gma_write16(hw, port, GM_GP_CTRL, reg);
1376 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1377
1378 if (sky2->rx_pause && !sky2->tx_pause) {
1379 /* restore Asymmetric Pause bit */
1380 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1381 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1382 | PHY_M_AN_ASP);
1383 }
1384
1385 sky2_phy_reset(hw, port);
1386
1387 netif_carrier_off(sky2->netdev);
1388 netif_stop_queue(sky2->netdev);
1389
1390 /* Turn on link LED */
1391 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1392
1393 if (netif_msg_link(sky2))
1394 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1395 sky2_phy_init(hw, port);
1396}
1397
1398static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1399{
1400 struct sky2_hw *hw = sky2->hw;
1401 unsigned port = sky2->port;
1402 u16 lpa;
1403
1404 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1405
1406 if (lpa & PHY_M_AN_RF) {
1407 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1408 return -1;
1409 }
1410
1411 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1412 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1413 printk(KERN_ERR PFX "%s: master/slave fault",
1414 sky2->netdev->name);
1415 return -1;
1416 }
1417
1418 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1419 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1420 sky2->netdev->name);
1421 return -1;
1422 }
1423
1424 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1425
1426 sky2->speed = sky2_phy_speed(hw, aux);
1427
1428 /* Pause bits are offset (9..8) */
1429 if (hw->chip_id == CHIP_ID_YUKON_XL)
1430 aux >>= 6;
1431
1432 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1433 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1434
1435 if ((sky2->tx_pause || sky2->rx_pause)
1436 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1437 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1438 else
1439 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1440
1441 return 0;
1442}
1443
1444/*
1445 * Interrupt from PHY are handled in tasklet (soft irq)
1446 * because accessing phy registers requires spin wait which might
1447 * cause excess interrupt latency.
1448 */
1449static void sky2_phy_task(unsigned long data)
1450{
1451 struct sky2_port *sky2 = (struct sky2_port *)data;
1452 struct sky2_hw *hw = sky2->hw;
1453 u16 istatus, phystat;
1454
1455 spin_lock(&hw->phy_lock);
1456 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1457 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1458
1459 if (netif_msg_intr(sky2))
1460 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1461 sky2->netdev->name, istatus, phystat);
1462
1463 if (istatus & PHY_M_IS_AN_COMPL) {
1464 if (sky2_autoneg_done(sky2, phystat) == 0)
1465 sky2_link_up(sky2);
1466 goto out;
1467 }
1468
1469 if (istatus & PHY_M_IS_LSP_CHANGE)
1470 sky2->speed = sky2_phy_speed(hw, phystat);
1471
1472 if (istatus & PHY_M_IS_DUP_CHANGE)
1473 sky2->duplex =
1474 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1475
1476 if (istatus & PHY_M_IS_LST_CHANGE) {
1477 if (phystat & PHY_M_PS_LINK_UP)
1478 sky2_link_up(sky2);
1479 else
1480 sky2_link_down(sky2);
1481 }
1482out:
1483 spin_unlock(&hw->phy_lock);
1484
1485 local_irq_disable();
1486 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1487 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1488 local_irq_enable();
1489}
1490
1491static void sky2_tx_timeout(struct net_device *dev)
1492{
1493 struct sky2_port *sky2 = netdev_priv(dev);
1494
1495 if (netif_msg_timer(sky2))
1496 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1497
1498 sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
1499 sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
1500
1501 sky2_tx_clean(sky2);
1502}
1503
1504static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1505{
1506 struct sky2_port *sky2 = netdev_priv(dev);
1507 struct sky2_hw *hw = sky2->hw;
1508 int err;
1509 u16 ctl, mode;
1510
1511 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1512 return -EINVAL;
1513
1514 if (!netif_running(dev)) {
1515 dev->mtu = new_mtu;
1516 return 0;
1517 }
1518
1519 local_irq_disable();
1520 sky2_write32(hw, B0_IMSK, 0);
1521
1522 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1523 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1524 sky2_rx_stop(sky2);
1525 sky2_rx_clean(sky2);
1526
1527 dev->mtu = new_mtu;
1528 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1529 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1530
1531 if (dev->mtu > ETH_DATA_LEN)
1532 mode |= GM_SMOD_JUMBO_ENA;
1533
1534 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1535
1536 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1537
1538 err = sky2_rx_start(sky2);
1539 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1540
1541 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1542 sky2_read32(hw, B0_IMSK);
1543 local_irq_enable();
1544 return err;
1545}
1546
1547/*
1548 * Receive one packet.
1549 * For small packets or errors, just reuse existing skb.
1550 * For larger packets, get new buffer.
1551 */
1552static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1553 u16 length, u32 status)
1554{
1555 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1556 struct sk_buff *skb = NULL;
1557 struct net_device *dev;
1558 const unsigned int bufsize = rx_size(sky2);
1559
1560 if (unlikely(netif_msg_rx_status(sky2)))
1561 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1562 sky2->netdev->name, sky2->rx_next, status, length);
1563
1564 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1565
1566 if (!(status & GMR_FS_RX_OK) || (status & GMR_FS_ANY_ERR))
1567 goto error;
1568
1569 if (length < RX_COPY_THRESHOLD) {
1570 skb = alloc_skb(length + 2, GFP_ATOMIC);
1571 if (!skb)
1572 goto resubmit;
1573
1574 skb_reserve(skb, 2);
1575 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1576 length, PCI_DMA_FROMDEVICE);
1577 memcpy(skb->data, re->skb->data, length);
1578 skb->ip_summed = re->skb->ip_summed;
1579 skb->csum = re->skb->csum;
1580 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1581 length, PCI_DMA_FROMDEVICE);
1582 } else {
1583 struct sk_buff *nskb;
1584
1585 nskb = dev_alloc_skb(bufsize);
1586 if (!nskb)
1587 goto resubmit;
1588
1589 skb = re->skb;
1590 re->skb = nskb;
1591 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1592 re->maplen, PCI_DMA_FROMDEVICE);
1593 prefetch(skb->data);
1594
1595 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1596 bufsize, PCI_DMA_FROMDEVICE);
1597 re->maplen = bufsize;
1598 }
1599
1600 skb_put(skb, length);
1601 dev = sky2->netdev;
1602 skb->dev = dev;
1603 skb->protocol = eth_type_trans(skb, dev);
1604 dev->last_rx = jiffies;
1605
1606resubmit:
1607 re->skb->ip_summed = CHECKSUM_NONE;
1608 sky2_rx_add(sky2, re);
1609
1610 /* Tell receiver about new buffers. */
1611 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1612 &sky2->rx_last_put, RX_LE_SIZE);
1613
1614 return skb;
1615
1616error:
1617 if (status & GMR_FS_GOOD_FC)
1618 goto resubmit;
1619
1620 if (netif_msg_rx_err(sky2))
1621 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1622 sky2->netdev->name, status, length);
1623
1624 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1625 sky2->net_stats.rx_length_errors++;
1626 if (status & GMR_FS_FRAGMENT)
1627 sky2->net_stats.rx_frame_errors++;
1628 if (status & GMR_FS_CRC_ERR)
1629 sky2->net_stats.rx_crc_errors++;
1630 if (status & GMR_FS_RX_FF_OV)
1631 sky2->net_stats.rx_fifo_errors++;
1632
1633 goto resubmit;
1634}
1635
1636/* Transmit ring index in reported status block is encoded as:
1637 *
1638 * | TXS2 | TXA2 | TXS1 | TXA1
1639 */
1640static inline u16 tx_index(u8 port, u32 status, u16 len)
1641{
1642 if (port == 0)
1643 return status & 0xfff;
1644 else
1645 return ((status >> 24) & 0xff) | (len & 0xf) << 8;
1646}
1647
1648/*
1649 * Both ports share the same status interrupt, therefore there is only
1650 * one poll routine.
1651 */
1652static int sky2_poll(struct net_device *dev0, int *budget)
1653{
1654 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1655 unsigned int to_do = min(dev0->quota, *budget);
1656 unsigned int work_done = 0;
1657 u16 hwidx;
1658
1659 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1660 BUG_ON(hwidx >= STATUS_RING_SIZE);
1661 rmb();
1662
1663 do {
1664 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1665 struct sky2_port *sky2;
1666 struct sk_buff *skb;
1667 u32 status;
1668 u16 length;
1669
1670 /* Are we done yet? */
1671 if (hw->st_idx == hwidx) {
1672 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1673 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1674 if (hwidx == hw->st_idx)
1675 break;
1676 }
1677
1678 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1679 prefetch(&hw->st_le[hw->st_idx]);
1680
1681 BUG_ON(le->link >= hw->ports || !hw->dev[le->link]);
1682
1683 sky2 = netdev_priv(hw->dev[le->link]);
1684 status = le32_to_cpu(le->status);
1685 length = le16_to_cpu(le->length);
1686
1687 switch (le->opcode & ~HW_OWNER) {
1688 case OP_RXSTAT:
1689 skb = sky2_receive(sky2, length, status);
1690 if (!skb)
1691 break;
1692#ifdef SKY2_VLAN_TAG_USED
1693 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1694 vlan_hwaccel_receive_skb(skb,
1695 sky2->vlgrp,
1696 be16_to_cpu(sky2->rx_tag));
1697 } else
1698#endif
1699 netif_receive_skb(skb);
1700 ++work_done;
1701 break;
1702
1703#ifdef SKY2_VLAN_TAG_USED
1704 case OP_RXVLAN:
1705 sky2->rx_tag = length;
1706 break;
1707
1708 case OP_RXCHKSVLAN:
1709 sky2->rx_tag = length;
1710 /* fall through */
1711#endif
1712 case OP_RXCHKS:
1713 skb = sky2->rx_ring[sky2->rx_next].skb;
1714 skb->ip_summed = CHECKSUM_HW;
1715 skb->csum = le16_to_cpu(status);
1716 break;
1717
1718 case OP_TXINDEXLE:
1719 sky2_tx_complete(sky2,
1720 tx_index(sky2->port, status, length));
1721 break;
1722
1723 default:
1724 if (net_ratelimit())
1725 printk(KERN_WARNING PFX
1726 "unknown status opcode 0x%x\n",
1727 le->opcode);
1728 break;
1729 }
1730
1731 le->opcode = 0; /* paranoia */
1732 } while (work_done < to_do);
1733
1734 mmiowb();
1735
1736 *budget -= work_done;
1737 dev0->quota -= work_done;
1738 if (work_done < to_do) {
1739 /*
1740 * Another chip workaround, need to restart TX timer if status
1741 * LE was handled. WA_DEV_43_418
1742 */
1743 if (is_ec_a1(hw)) {
1744 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1745 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1746 }
1747
1748 netif_rx_complete(dev0);
1749 hw->intr_mask |= Y2_IS_STAT_BMU;
1750 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1751 sky2_read32(hw, B0_IMSK);
1752 }
1753
1754 return work_done >= to_do;
1755
1756}
1757
1758static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1759{
1760 struct net_device *dev = hw->dev[port];
1761
1762 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1763 dev->name, status);
1764
1765 if (status & Y2_IS_PAR_RD1) {
1766 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1767 dev->name);
1768 /* Clear IRQ */
1769 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1770 }
1771
1772 if (status & Y2_IS_PAR_WR1) {
1773 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1774 dev->name);
1775
1776 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1777 }
1778
1779 if (status & Y2_IS_PAR_MAC1) {
1780 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1781 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1782 }
1783
1784 if (status & Y2_IS_PAR_RX1) {
1785 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1786 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1787 }
1788
1789 if (status & Y2_IS_TCP_TXA1) {
1790 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1791 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1792 }
1793}
1794
1795static void sky2_hw_intr(struct sky2_hw *hw)
1796{
1797 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1798
1799 if (status & Y2_IS_TIST_OV)
1800 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1801
1802 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1803 u16 pci_err;
1804
1805 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1806 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1807 pci_name(hw->pdev), pci_err);
1808
1809 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1810 pci_write_config_word(hw->pdev, PCI_STATUS,
1811 pci_err | PCI_STATUS_ERROR_BITS);
1812 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1813 }
1814
1815 if (status & Y2_IS_PCI_EXP) {
1816 /* PCI-Express uncorrectable Error occurred */
1817 u32 pex_err;
1818
1819 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
1820
1821 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1822 pci_name(hw->pdev), pex_err);
1823
1824 /* clear the interrupt */
1825 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1826 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1827 0xffffffffUL);
1828 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1829
1830 if (pex_err & PEX_FATAL_ERRORS) {
1831 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1832 hwmsk &= ~Y2_IS_PCI_EXP;
1833 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1834 }
1835 }
1836
1837 if (status & Y2_HWE_L1_MASK)
1838 sky2_hw_error(hw, 0, status);
1839 status >>= 8;
1840 if (status & Y2_HWE_L1_MASK)
1841 sky2_hw_error(hw, 1, status);
1842}
1843
1844static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1845{
1846 struct net_device *dev = hw->dev[port];
1847 struct sky2_port *sky2 = netdev_priv(dev);
1848 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1849
1850 if (netif_msg_intr(sky2))
1851 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1852 dev->name, status);
1853
1854 if (status & GM_IS_RX_FF_OR) {
1855 ++sky2->net_stats.rx_fifo_errors;
1856 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1857 }
1858
1859 if (status & GM_IS_TX_FF_UR) {
1860 ++sky2->net_stats.tx_fifo_errors;
1861 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1862 }
1863}
1864
1865static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1866{
1867 struct net_device *dev = hw->dev[port];
1868 struct sky2_port *sky2 = netdev_priv(dev);
1869
1870 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1871 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1872 tasklet_schedule(&sky2->phy_task);
1873}
1874
1875static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1876{
1877 struct sky2_hw *hw = dev_id;
1878 struct net_device *dev0 = hw->dev[0];
1879 u32 status;
1880
1881 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
1882 if (status == 0 || status == ~0)
1883 return IRQ_NONE;
1884
1885 if (status & Y2_IS_HW_ERR)
1886 sky2_hw_intr(hw);
1887
1888 /* Do NAPI for Rx and Tx status */
1889 if (status & Y2_IS_STAT_BMU) {
1890 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1891 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1892 prefetch(&hw->st_le[hw->st_idx]);
1893
1894 if (netif_rx_schedule_test(dev0))
1895 __netif_rx_schedule(dev0);
1896 }
1897
1898 if (status & Y2_IS_IRQ_PHY1)
1899 sky2_phy_intr(hw, 0);
1900
1901 if (status & Y2_IS_IRQ_PHY2)
1902 sky2_phy_intr(hw, 1);
1903
1904 if (status & Y2_IS_IRQ_MAC1)
1905 sky2_mac_intr(hw, 0);
1906
1907 if (status & Y2_IS_IRQ_MAC2)
1908 sky2_mac_intr(hw, 1);
1909
1910 sky2_write32(hw, B0_Y2_SP_ICR, 2);
1911
1912 sky2_read32(hw, B0_IMSK);
1913
1914 return IRQ_HANDLED;
1915}
1916
1917#ifdef CONFIG_NET_POLL_CONTROLLER
1918static void sky2_netpoll(struct net_device *dev)
1919{
1920 struct sky2_port *sky2 = netdev_priv(dev);
1921
1922 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
1923}
1924#endif
1925
1926/* Chip internal frequency for clock calculations */
1927static inline u32 sky2_khz(const struct sky2_hw *hw)
1928{
1929 switch (hw->chip_id) {
1930 case CHIP_ID_YUKON_EC:
1931 return 125000; /* 125 Mhz */
1932 case CHIP_ID_YUKON_FE:
1933 return 100000; /* 100 Mhz */
1934 default: /* YUKON_XL */
1935 return 156000; /* 156 Mhz */
1936 }
1937}
1938
1939static inline u32 sky2_ms2clk(const struct sky2_hw *hw, u32 ms)
1940{
1941 return sky2_khz(hw) * ms;
1942}
1943
1944static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
1945{
1946 return (sky2_khz(hw) * us) / 1000;
1947}
1948
1949static int sky2_reset(struct sky2_hw *hw)
1950{
1951 u32 ctst;
1952 u16 status;
1953 u8 t8, pmd_type;
1954 int i;
1955
1956 ctst = sky2_read32(hw, B0_CTST);
1957
1958 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1959 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
1960 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
1961 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
1962 pci_name(hw->pdev), hw->chip_id);
1963 return -EOPNOTSUPP;
1964 }
1965
1966 /* ring for status responses */
1967 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
1968 &hw->st_dma);
1969 if (!hw->st_le)
1970 return -ENOMEM;
1971
1972 /* disable ASF */
1973 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
1974 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1975 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
1976 }
1977
1978 /* do a SW reset */
1979 sky2_write8(hw, B0_CTST, CS_RST_SET);
1980 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1981
1982 /* clear PCI errors, if any */
1983 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
1984 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1985 pci_write_config_word(hw->pdev, PCI_STATUS,
1986 status | PCI_STATUS_ERROR_BITS);
1987
1988 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
1989
1990 /* clear any PEX errors */
1991 if (is_pciex(hw)) {
1992 u16 lstat;
1993 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1994 0xffffffffUL);
1995 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
1996 }
1997
1998 pmd_type = sky2_read8(hw, B2_PMD_TYP);
1999 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2000
2001 hw->ports = 1;
2002 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2003 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2004 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2005 ++hw->ports;
2006 }
2007 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2008
2009 sky2_set_power_state(hw, PCI_D0);
2010
2011 for (i = 0; i < hw->ports; i++) {
2012 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2013 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2014 }
2015
2016 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2017
2018 /* Clear I2C IRQ noise */
2019 sky2_write32(hw, B2_I2C_IRQ, 1);
2020
2021 /* turn off hardware timer (unused) */
2022 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2023 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2024
2025 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2026
2027 /* Turn on descriptor polling (every 75us) */
2028 sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
2029 sky2_write8(hw, B28_DPT_CTRL, DPT_START);
2030
2031 /* Turn off receive timestamp */
2032 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2033 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2034
2035 /* enable the Tx Arbiters */
2036 for (i = 0; i < hw->ports; i++)
2037 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2038
2039 /* Initialize ram interface */
2040 for (i = 0; i < hw->ports; i++) {
2041 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2042
2043 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2044 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2045 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2046 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2047 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2048 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2049 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2050 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2051 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2052 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2053 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2054 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2055 }
2056
2057 if (is_pciex(hw)) {
2058 u16 pctrl;
2059
2060 /* change Max. Read Request Size to 2048 bytes */
2061 pci_read_config_word(hw->pdev, PEX_DEV_CTRL, &pctrl);
2062 pctrl &= ~PEX_DC_MAX_RRS_MSK;
2063 pctrl |= PEX_DC_MAX_RD_RQ_SIZE(4);
2064
2065
2066 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2067 pci_write_config_word(hw->pdev, PEX_DEV_CTRL, pctrl);
2068 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2069 }
2070
2071 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2072
2073 spin_lock_bh(&hw->phy_lock);
2074 for (i = 0; i < hw->ports; i++)
2075 sky2_phy_reset(hw, i);
2076 spin_unlock_bh(&hw->phy_lock);
2077
2078 memset(hw->st_le, 0, STATUS_LE_BYTES);
2079 hw->st_idx = 0;
2080
2081 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2082 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2083
2084 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2085 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2086
2087 /* Set the list last index */
2088 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2089
2090 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_ms2clk(hw, 10));
2091
2092 /* These status setup values are copied from SysKonnect's driver */
2093 if (is_ec_a1(hw)) {
2094 /* WA for dev. #4.3 */
2095 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2096
2097 /* set Status-FIFO watermark */
2098 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2099
2100 /* set Status-FIFO ISR watermark */
2101 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2102
2103 } else {
2104 sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
2105
2106 /* set Status-FIFO watermark */
2107 sky2_write8(hw, STAT_FIFO_WM, 0x10);
2108
2109 /* set Status-FIFO ISR watermark */
2110 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2111 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
2112
2113 else /* WA dev 4.109 */
2114 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
2115
2116 sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
2117 }
2118
2119 /* enable status unit */
2120 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2121
2122 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2123 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2124 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2125
2126 return 0;
2127}
2128
2129static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2130{
2131 u32 modes;
2132 if (hw->copper) {
2133 modes = SUPPORTED_10baseT_Half
2134 | SUPPORTED_10baseT_Full
2135 | SUPPORTED_100baseT_Half
2136 | SUPPORTED_100baseT_Full
2137 | SUPPORTED_Autoneg | SUPPORTED_TP;
2138
2139 if (hw->chip_id != CHIP_ID_YUKON_FE)
2140 modes |= SUPPORTED_1000baseT_Half
2141 | SUPPORTED_1000baseT_Full;
2142 } else
2143 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2144 | SUPPORTED_Autoneg;
2145 return modes;
2146}
2147
2148static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2149{
2150 struct sky2_port *sky2 = netdev_priv(dev);
2151 struct sky2_hw *hw = sky2->hw;
2152
2153 ecmd->transceiver = XCVR_INTERNAL;
2154 ecmd->supported = sky2_supported_modes(hw);
2155 ecmd->phy_address = PHY_ADDR_MARV;
2156 if (hw->copper) {
2157 ecmd->supported = SUPPORTED_10baseT_Half
2158 | SUPPORTED_10baseT_Full
2159 | SUPPORTED_100baseT_Half
2160 | SUPPORTED_100baseT_Full
2161 | SUPPORTED_1000baseT_Half
2162 | SUPPORTED_1000baseT_Full
2163 | SUPPORTED_Autoneg | SUPPORTED_TP;
2164 ecmd->port = PORT_TP;
2165 } else
2166 ecmd->port = PORT_FIBRE;
2167
2168 ecmd->advertising = sky2->advertising;
2169 ecmd->autoneg = sky2->autoneg;
2170 ecmd->speed = sky2->speed;
2171 ecmd->duplex = sky2->duplex;
2172 return 0;
2173}
2174
2175static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2176{
2177 struct sky2_port *sky2 = netdev_priv(dev);
2178 const struct sky2_hw *hw = sky2->hw;
2179 u32 supported = sky2_supported_modes(hw);
2180
2181 if (ecmd->autoneg == AUTONEG_ENABLE) {
2182 ecmd->advertising = supported;
2183 sky2->duplex = -1;
2184 sky2->speed = -1;
2185 } else {
2186 u32 setting;
2187
2188 switch (ecmd->speed) {
2189 case SPEED_1000:
2190 if (ecmd->duplex == DUPLEX_FULL)
2191 setting = SUPPORTED_1000baseT_Full;
2192 else if (ecmd->duplex == DUPLEX_HALF)
2193 setting = SUPPORTED_1000baseT_Half;
2194 else
2195 return -EINVAL;
2196 break;
2197 case SPEED_100:
2198 if (ecmd->duplex == DUPLEX_FULL)
2199 setting = SUPPORTED_100baseT_Full;
2200 else if (ecmd->duplex == DUPLEX_HALF)
2201 setting = SUPPORTED_100baseT_Half;
2202 else
2203 return -EINVAL;
2204 break;
2205
2206 case SPEED_10:
2207 if (ecmd->duplex == DUPLEX_FULL)
2208 setting = SUPPORTED_10baseT_Full;
2209 else if (ecmd->duplex == DUPLEX_HALF)
2210 setting = SUPPORTED_10baseT_Half;
2211 else
2212 return -EINVAL;
2213 break;
2214 default:
2215 return -EINVAL;
2216 }
2217
2218 if ((setting & supported) == 0)
2219 return -EINVAL;
2220
2221 sky2->speed = ecmd->speed;
2222 sky2->duplex = ecmd->duplex;
2223 }
2224
2225 sky2->autoneg = ecmd->autoneg;
2226 sky2->advertising = ecmd->advertising;
2227
2228 if (netif_running(dev)) {
2229 sky2_down(dev);
2230 sky2_up(dev);
2231 }
2232
2233 return 0;
2234}
2235
2236static void sky2_get_drvinfo(struct net_device *dev,
2237 struct ethtool_drvinfo *info)
2238{
2239 struct sky2_port *sky2 = netdev_priv(dev);
2240
2241 strcpy(info->driver, DRV_NAME);
2242 strcpy(info->version, DRV_VERSION);
2243 strcpy(info->fw_version, "N/A");
2244 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2245}
2246
2247static const struct sky2_stat {
2248 char name[ETH_GSTRING_LEN];
2249 u16 offset;
2250} sky2_stats[] = {
2251 { "tx_bytes", GM_TXO_OK_HI },
2252 { "rx_bytes", GM_RXO_OK_HI },
2253 { "tx_broadcast", GM_TXF_BC_OK },
2254 { "rx_broadcast", GM_RXF_BC_OK },
2255 { "tx_multicast", GM_TXF_MC_OK },
2256 { "rx_multicast", GM_RXF_MC_OK },
2257 { "tx_unicast", GM_TXF_UC_OK },
2258 { "rx_unicast", GM_RXF_UC_OK },
2259 { "tx_mac_pause", GM_TXF_MPAUSE },
2260 { "rx_mac_pause", GM_RXF_MPAUSE },
2261 { "collisions", GM_TXF_SNG_COL },
2262 { "late_collision",GM_TXF_LAT_COL },
2263 { "aborted", GM_TXF_ABO_COL },
2264 { "multi_collisions", GM_TXF_MUL_COL },
2265 { "fifo_underrun", GM_TXE_FIFO_UR },
2266 { "fifo_overflow", GM_RXE_FIFO_OV },
2267 { "rx_toolong", GM_RXF_LNG_ERR },
2268 { "rx_jabber", GM_RXF_JAB_PKT },
2269 { "rx_runt", GM_RXE_FRAG },
2270 { "rx_too_long", GM_RXF_LNG_ERR },
2271 { "rx_fcs_error", GM_RXF_FCS_ERR },
2272};
2273
2274static u32 sky2_get_rx_csum(struct net_device *dev)
2275{
2276 struct sky2_port *sky2 = netdev_priv(dev);
2277
2278 return sky2->rx_csum;
2279}
2280
2281static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2282{
2283 struct sky2_port *sky2 = netdev_priv(dev);
2284
2285 sky2->rx_csum = data;
2286
2287 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2288 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2289
2290 return 0;
2291}
2292
2293static u32 sky2_get_msglevel(struct net_device *netdev)
2294{
2295 struct sky2_port *sky2 = netdev_priv(netdev);
2296 return sky2->msg_enable;
2297}
2298
2299static int sky2_nway_reset(struct net_device *dev)
2300{
2301 struct sky2_port *sky2 = netdev_priv(dev);
2302 struct sky2_hw *hw = sky2->hw;
2303
2304 if (sky2->autoneg != AUTONEG_ENABLE)
2305 return -EINVAL;
2306
2307 netif_stop_queue(dev);
2308
2309 spin_lock_irq(&hw->phy_lock);
2310 sky2_phy_reset(hw, sky2->port);
2311 sky2_phy_init(hw, sky2->port);
2312 spin_unlock_irq(&hw->phy_lock);
2313
2314 return 0;
2315}
2316
2317static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2318{
2319 struct sky2_hw *hw = sky2->hw;
2320 unsigned port = sky2->port;
2321 int i;
2322
2323 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2324 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2325 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2326 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2327
2328 for (i = 2; i < count; i++)
2329 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2330}
2331
2332static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2333{
2334 struct sky2_port *sky2 = netdev_priv(netdev);
2335 sky2->msg_enable = value;
2336}
2337
2338static int sky2_get_stats_count(struct net_device *dev)
2339{
2340 return ARRAY_SIZE(sky2_stats);
2341}
2342
2343static void sky2_get_ethtool_stats(struct net_device *dev,
2344 struct ethtool_stats *stats, u64 * data)
2345{
2346 struct sky2_port *sky2 = netdev_priv(dev);
2347
2348 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2349}
2350
2351static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2352{
2353 int i;
2354
2355 switch (stringset) {
2356 case ETH_SS_STATS:
2357 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2358 memcpy(data + i * ETH_GSTRING_LEN,
2359 sky2_stats[i].name, ETH_GSTRING_LEN);
2360 break;
2361 }
2362}
2363
2364/* Use hardware MIB variables for critical path statistics and
2365 * transmit feedback not reported at interrupt.
2366 * Other errors are accounted for in interrupt handler.
2367 */
2368static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2369{
2370 struct sky2_port *sky2 = netdev_priv(dev);
2371 u64 data[13];
2372
2373 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2374
2375 sky2->net_stats.tx_bytes = data[0];
2376 sky2->net_stats.rx_bytes = data[1];
2377 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2378 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2379 sky2->net_stats.multicast = data[5] + data[7];
2380 sky2->net_stats.collisions = data[10];
2381 sky2->net_stats.tx_aborted_errors = data[12];
2382
2383 return &sky2->net_stats;
2384}
2385
2386static int sky2_set_mac_address(struct net_device *dev, void *p)
2387{
2388 struct sky2_port *sky2 = netdev_priv(dev);
2389 struct sockaddr *addr = p;
2390 int err = 0;
2391
2392 if (!is_valid_ether_addr(addr->sa_data))
2393 return -EADDRNOTAVAIL;
2394
2395 sky2_down(dev);
2396 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2397 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
2398 dev->dev_addr, ETH_ALEN);
2399 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
2400 dev->dev_addr, ETH_ALEN);
2401 if (dev->flags & IFF_UP)
2402 err = sky2_up(dev);
2403 return err;
2404}
2405
2406static void sky2_set_multicast(struct net_device *dev)
2407{
2408 struct sky2_port *sky2 = netdev_priv(dev);
2409 struct sky2_hw *hw = sky2->hw;
2410 unsigned port = sky2->port;
2411 struct dev_mc_list *list = dev->mc_list;
2412 u16 reg;
2413 u8 filter[8];
2414
2415 memset(filter, 0, sizeof(filter));
2416
2417 reg = gma_read16(hw, port, GM_RX_CTRL);
2418 reg |= GM_RXCR_UCF_ENA;
2419
2420 if (dev->flags & IFF_PROMISC) /* promiscuous */
2421 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2422 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2423 memset(filter, 0xff, sizeof(filter));
2424 else if (dev->mc_count == 0) /* no multicast */
2425 reg &= ~GM_RXCR_MCF_ENA;
2426 else {
2427 int i;
2428 reg |= GM_RXCR_MCF_ENA;
2429
2430 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2431 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2432 filter[bit / 8] |= 1 << (bit % 8);
2433 }
2434 }
2435
2436 gma_write16(hw, port, GM_MC_ADDR_H1,
2437 (u16) filter[0] | ((u16) filter[1] << 8));
2438 gma_write16(hw, port, GM_MC_ADDR_H2,
2439 (u16) filter[2] | ((u16) filter[3] << 8));
2440 gma_write16(hw, port, GM_MC_ADDR_H3,
2441 (u16) filter[4] | ((u16) filter[5] << 8));
2442 gma_write16(hw, port, GM_MC_ADDR_H4,
2443 (u16) filter[6] | ((u16) filter[7] << 8));
2444
2445 gma_write16(hw, port, GM_RX_CTRL, reg);
2446}
2447
2448/* Can have one global because blinking is controlled by
2449 * ethtool and that is always under RTNL mutex
2450 */
2451static inline void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2452{
2453 u16 pg;
2454
2455 spin_lock_bh(&hw->phy_lock);
2456 switch (hw->chip_id) {
2457 case CHIP_ID_YUKON_XL:
2458 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2459 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2460 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2461 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2462 PHY_M_LEDC_INIT_CTRL(7) |
2463 PHY_M_LEDC_STA1_CTRL(7) |
2464 PHY_M_LEDC_STA0_CTRL(7))
2465 : 0);
2466
2467 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2468 break;
2469
2470 default:
2471 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2472 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2473 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2474 PHY_M_LED_MO_10(MO_LED_ON) |
2475 PHY_M_LED_MO_100(MO_LED_ON) |
2476 PHY_M_LED_MO_1000(MO_LED_ON) |
2477 PHY_M_LED_MO_RX(MO_LED_ON)
2478 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2479 PHY_M_LED_MO_10(MO_LED_OFF) |
2480 PHY_M_LED_MO_100(MO_LED_OFF) |
2481 PHY_M_LED_MO_1000(MO_LED_OFF) |
2482 PHY_M_LED_MO_RX(MO_LED_OFF));
2483
2484 }
2485 spin_unlock_bh(&hw->phy_lock);
2486}
2487
2488/* blink LED's for finding board */
2489static int sky2_phys_id(struct net_device *dev, u32 data)
2490{
2491 struct sky2_port *sky2 = netdev_priv(dev);
2492 struct sky2_hw *hw = sky2->hw;
2493 unsigned port = sky2->port;
2494 u16 ledctrl, ledover = 0;
2495 long ms;
2496 int onoff = 1;
2497
2498 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2499 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2500 else
2501 ms = data * 1000;
2502
2503 /* save initial values */
2504 spin_lock_bh(&hw->phy_lock);
2505 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2506 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2507 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2508 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2509 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2510 } else {
2511 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2512 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2513 }
2514 spin_unlock_bh(&hw->phy_lock);
2515
2516 while (ms > 0) {
2517 sky2_led(hw, port, onoff);
2518 onoff = !onoff;
2519
2520 if (msleep_interruptible(250))
2521 break; /* interrupted */
2522 ms -= 250;
2523 }
2524
2525 /* resume regularly scheduled programming */
2526 spin_lock_bh(&hw->phy_lock);
2527 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2528 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2529 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2530 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2532 } else {
2533 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2534 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2535 }
2536 spin_unlock_bh(&hw->phy_lock);
2537
2538 return 0;
2539}
2540
2541static void sky2_get_pauseparam(struct net_device *dev,
2542 struct ethtool_pauseparam *ecmd)
2543{
2544 struct sky2_port *sky2 = netdev_priv(dev);
2545
2546 ecmd->tx_pause = sky2->tx_pause;
2547 ecmd->rx_pause = sky2->rx_pause;
2548 ecmd->autoneg = sky2->autoneg;
2549}
2550
2551static int sky2_set_pauseparam(struct net_device *dev,
2552 struct ethtool_pauseparam *ecmd)
2553{
2554 struct sky2_port *sky2 = netdev_priv(dev);
2555 int err = 0;
2556
2557 sky2->autoneg = ecmd->autoneg;
2558 sky2->tx_pause = ecmd->tx_pause != 0;
2559 sky2->rx_pause = ecmd->rx_pause != 0;
2560
2561 if (netif_running(dev)) {
2562 sky2_down(dev);
2563 err = sky2_up(dev);
2564 }
2565
2566 return err;
2567}
2568
2569#ifdef CONFIG_PM
2570static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2571{
2572 struct sky2_port *sky2 = netdev_priv(dev);
2573
2574 wol->supported = WAKE_MAGIC;
2575 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2576}
2577
2578static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2579{
2580 struct sky2_port *sky2 = netdev_priv(dev);
2581 struct sky2_hw *hw = sky2->hw;
2582
2583 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2584 return -EOPNOTSUPP;
2585
2586 sky2->wol = wol->wolopts == WAKE_MAGIC;
2587
2588 if (sky2->wol) {
2589 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2590
2591 sky2_write16(hw, WOL_CTRL_STAT,
2592 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2593 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2594 } else
2595 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2596
2597 return 0;
2598}
2599#endif
2600
2601static void sky2_get_ringparam(struct net_device *dev,
2602 struct ethtool_ringparam *ering)
2603{
2604 struct sky2_port *sky2 = netdev_priv(dev);
2605
2606 ering->rx_max_pending = RX_MAX_PENDING;
2607 ering->rx_mini_max_pending = 0;
2608 ering->rx_jumbo_max_pending = 0;
2609 ering->tx_max_pending = TX_RING_SIZE - 1;
2610
2611 ering->rx_pending = sky2->rx_pending;
2612 ering->rx_mini_pending = 0;
2613 ering->rx_jumbo_pending = 0;
2614 ering->tx_pending = sky2->tx_pending;
2615}
2616
2617static int sky2_set_ringparam(struct net_device *dev,
2618 struct ethtool_ringparam *ering)
2619{
2620 struct sky2_port *sky2 = netdev_priv(dev);
2621 int err = 0;
2622
2623 if (ering->rx_pending > RX_MAX_PENDING ||
2624 ering->rx_pending < 8 ||
2625 ering->tx_pending < MAX_SKB_TX_LE ||
2626 ering->tx_pending > TX_RING_SIZE - 1)
2627 return -EINVAL;
2628
2629 if (netif_running(dev))
2630 sky2_down(dev);
2631
2632 sky2->rx_pending = ering->rx_pending;
2633 sky2->tx_pending = ering->tx_pending;
2634
2635 if (netif_running(dev))
2636 err = sky2_up(dev);
2637
2638 return err;
2639}
2640
2641static int sky2_get_regs_len(struct net_device *dev)
2642{
2643 return 0x4000;
2644}
2645
2646/*
2647 * Returns copy of control register region
2648 * Note: access to the RAM address register set will cause timeouts.
2649 */
2650static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2651 void *p)
2652{
2653 const struct sky2_port *sky2 = netdev_priv(dev);
2654 const void __iomem *io = sky2->hw->regs;
2655
2656 BUG_ON(regs->len < B3_RI_WTO_R1);
2657 regs->version = 1;
2658 memset(p, 0, regs->len);
2659
2660 memcpy_fromio(p, io, B3_RAM_ADDR);
2661
2662 memcpy_fromio(p + B3_RI_WTO_R1,
2663 io + B3_RI_WTO_R1,
2664 regs->len - B3_RI_WTO_R1);
2665}
2666
2667static struct ethtool_ops sky2_ethtool_ops = {
2668 .get_settings = sky2_get_settings,
2669 .set_settings = sky2_set_settings,
2670 .get_drvinfo = sky2_get_drvinfo,
2671 .get_msglevel = sky2_get_msglevel,
2672 .set_msglevel = sky2_set_msglevel,
2673 .nway_reset = sky2_nway_reset,
2674 .get_regs_len = sky2_get_regs_len,
2675 .get_regs = sky2_get_regs,
2676 .get_link = ethtool_op_get_link,
2677 .get_sg = ethtool_op_get_sg,
2678 .set_sg = ethtool_op_set_sg,
2679 .get_tx_csum = ethtool_op_get_tx_csum,
2680 .set_tx_csum = ethtool_op_set_tx_csum,
2681 .get_tso = ethtool_op_get_tso,
2682 .set_tso = ethtool_op_set_tso,
2683 .get_rx_csum = sky2_get_rx_csum,
2684 .set_rx_csum = sky2_set_rx_csum,
2685 .get_strings = sky2_get_strings,
2686 .get_ringparam = sky2_get_ringparam,
2687 .set_ringparam = sky2_set_ringparam,
2688 .get_pauseparam = sky2_get_pauseparam,
2689 .set_pauseparam = sky2_set_pauseparam,
2690#ifdef CONFIG_PM
2691 .get_wol = sky2_get_wol,
2692 .set_wol = sky2_set_wol,
2693#endif
2694 .phys_id = sky2_phys_id,
2695 .get_stats_count = sky2_get_stats_count,
2696 .get_ethtool_stats = sky2_get_ethtool_stats,
2697 .get_perm_addr = ethtool_op_get_perm_addr,
2698};
2699
2700/* Initialize network device */
2701static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2702 unsigned port, int highmem)
2703{
2704 struct sky2_port *sky2;
2705 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2706
2707 if (!dev) {
2708 printk(KERN_ERR "sky2 etherdev alloc failed");
2709 return NULL;
2710 }
2711
2712 SET_MODULE_OWNER(dev);
2713 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2714 dev->open = sky2_up;
2715 dev->stop = sky2_down;
2716 dev->hard_start_xmit = sky2_xmit_frame;
2717 dev->get_stats = sky2_get_stats;
2718 dev->set_multicast_list = sky2_set_multicast;
2719 dev->set_mac_address = sky2_set_mac_address;
2720 dev->change_mtu = sky2_change_mtu;
2721 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2722 dev->tx_timeout = sky2_tx_timeout;
2723 dev->watchdog_timeo = TX_WATCHDOG;
2724 if (port == 0)
2725 dev->poll = sky2_poll;
2726 dev->weight = NAPI_WEIGHT;
2727#ifdef CONFIG_NET_POLL_CONTROLLER
2728 dev->poll_controller = sky2_netpoll;
2729#endif
2730
2731 sky2 = netdev_priv(dev);
2732 sky2->netdev = dev;
2733 sky2->hw = hw;
2734 sky2->msg_enable = netif_msg_init(debug, default_msg);
2735
2736 spin_lock_init(&sky2->tx_lock);
2737 /* Auto speed and flow control */
2738 sky2->autoneg = AUTONEG_ENABLE;
2739 sky2->tx_pause = 0;
2740 sky2->rx_pause = 1;
2741 sky2->duplex = -1;
2742 sky2->speed = -1;
2743 sky2->advertising = sky2_supported_modes(hw);
2744 sky2->rx_csum = 1;
2745 tasklet_init(&sky2->phy_task, sky2_phy_task, (unsigned long)sky2);
2746 sky2->tx_pending = TX_DEF_PENDING;
2747 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
2748
2749 hw->dev[port] = dev;
2750
2751 sky2->port = port;
2752
2753 dev->features |= NETIF_F_LLTX | NETIF_F_TSO;
2754 if (highmem)
2755 dev->features |= NETIF_F_HIGHDMA;
2756 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2757
2758#ifdef SKY2_VLAN_TAG_USED
2759 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2760 dev->vlan_rx_register = sky2_vlan_rx_register;
2761 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
2762#endif
2763
2764 /* read the mac address */
2765 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2766 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2767
2768 /* device is off until link detection */
2769 netif_carrier_off(dev);
2770 netif_stop_queue(dev);
2771
2772 return dev;
2773}
2774
2775static inline void sky2_show_addr(struct net_device *dev)
2776{
2777 const struct sky2_port *sky2 = netdev_priv(dev);
2778
2779 if (netif_msg_probe(sky2))
2780 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2781 dev->name,
2782 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2783 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2784}
2785
2786static int __devinit sky2_probe(struct pci_dev *pdev,
2787 const struct pci_device_id *ent)
2788{
2789 struct net_device *dev, *dev1 = NULL;
2790 struct sky2_hw *hw;
2791 int err, pm_cap, using_dac = 0;
2792
2793 err = pci_enable_device(pdev);
2794 if (err) {
2795 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2796 pci_name(pdev));
2797 goto err_out;
2798 }
2799
2800 err = pci_request_regions(pdev, DRV_NAME);
2801 if (err) {
2802 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2803 pci_name(pdev));
2804 goto err_out;
2805 }
2806
2807 pci_set_master(pdev);
2808
2809 /* Find power-management capability. */
2810 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2811 if (pm_cap == 0) {
2812 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
2813 "aborting.\n");
2814 err = -EIO;
2815 goto err_out_free_regions;
2816 }
2817
2818 if (sizeof(dma_addr_t) > sizeof(u32)) {
2819 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2820 if (!err)
2821 using_dac = 1;
2822 }
2823
2824 if (!using_dac) {
2825 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2826 if (err) {
2827 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
2828 pci_name(pdev));
2829 goto err_out_free_regions;
2830 }
2831 }
2832#ifdef __BIG_ENDIAN
2833 /* byte swap descriptors in hardware */
2834 {
2835 u32 reg;
2836
2837 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
2838 reg |= PCI_REV_DESC;
2839 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
2840 }
2841#endif
2842
2843 err = -ENOMEM;
2844 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
2845 if (!hw) {
2846 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
2847 pci_name(pdev));
2848 goto err_out_free_regions;
2849 }
2850
2851 memset(hw, 0, sizeof(*hw));
2852 hw->pdev = pdev;
2853 spin_lock_init(&hw->phy_lock);
2854
2855 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
2856 if (!hw->regs) {
2857 printk(KERN_ERR PFX "%s: cannot map device registers\n",
2858 pci_name(pdev));
2859 goto err_out_free_hw;
2860 }
2861 hw->pm_cap = pm_cap;
2862
2863 err = sky2_reset(hw);
2864 if (err)
2865 goto err_out_iounmap;
2866
2867 printk(KERN_INFO PFX "addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
2868 pci_resource_start(pdev, 0), pdev->irq,
2869 yukon_name[hw->chip_id - CHIP_ID_YUKON],
2870 hw->chip_id, hw->chip_rev);
2871
2872 dev = sky2_init_netdev(hw, 0, using_dac);
2873 if (!dev)
2874 goto err_out_free_pci;
2875
2876 err = register_netdev(dev);
2877 if (err) {
2878 printk(KERN_ERR PFX "%s: cannot register net device\n",
2879 pci_name(pdev));
2880 goto err_out_free_netdev;
2881 }
2882
2883 sky2_show_addr(dev);
2884
2885 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
2886 if (register_netdev(dev1) == 0)
2887 sky2_show_addr(dev1);
2888 else {
2889 /* Failure to register second port need not be fatal */
2890 printk(KERN_WARNING PFX
2891 "register of second port failed\n");
2892 hw->dev[1] = NULL;
2893 free_netdev(dev1);
2894 }
2895 }
2896
2897 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
2898 if (err) {
2899 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
2900 pci_name(pdev), pdev->irq);
2901 goto err_out_unregister;
2902 }
2903
2904 hw->intr_mask = Y2_IS_BASE;
2905 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2906
2907 pci_set_drvdata(pdev, hw);
2908
2909 return 0;
2910
2911err_out_unregister:
2912 if (dev1) {
2913 unregister_netdev(dev1);
2914 free_netdev(dev1);
2915 }
2916 unregister_netdev(dev);
2917err_out_free_netdev:
2918 free_netdev(dev);
2919err_out_free_pci:
2920 sky2_write8(hw, B0_CTST, CS_RST_SET);
2921 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2922err_out_iounmap:
2923 iounmap(hw->regs);
2924err_out_free_hw:
2925 kfree(hw);
2926err_out_free_regions:
2927 pci_release_regions(pdev);
2928 pci_disable_device(pdev);
2929err_out:
2930 return err;
2931}
2932
2933static void __devexit sky2_remove(struct pci_dev *pdev)
2934{
2935 struct sky2_hw *hw = pci_get_drvdata(pdev);
2936 struct net_device *dev0, *dev1;
2937
2938 if (!hw)
2939 return;
2940
2941 dev0 = hw->dev[0];
2942 dev1 = hw->dev[1];
2943 if (dev1)
2944 unregister_netdev(dev1);
2945 unregister_netdev(dev0);
2946
2947 sky2_write32(hw, B0_IMSK, 0);
2948 sky2_set_power_state(hw, PCI_D3hot);
2949 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
2950 sky2_write8(hw, B0_CTST, CS_RST_SET);
2951 sky2_read8(hw, B0_CTST);
2952
2953 free_irq(pdev->irq, hw);
2954 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2955 pci_release_regions(pdev);
2956 pci_disable_device(pdev);
2957
2958 if (dev1)
2959 free_netdev(dev1);
2960 free_netdev(dev0);
2961 iounmap(hw->regs);
2962 kfree(hw);
2963
2964 pci_set_drvdata(pdev, NULL);
2965}
2966
2967#ifdef CONFIG_PM
2968static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
2969{
2970 struct sky2_hw *hw = pci_get_drvdata(pdev);
2971 int i;
2972
2973 for (i = 0; i < 2; i++) {
2974 struct net_device *dev = hw->dev[i];
2975
2976 if (dev) {
2977 if (!netif_running(dev))
2978 continue;
2979
2980 sky2_down(dev);
2981 netif_device_detach(dev);
2982 }
2983 }
2984
2985 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
2986}
2987
2988static int sky2_resume(struct pci_dev *pdev)
2989{
2990 struct sky2_hw *hw = pci_get_drvdata(pdev);
2991 int i;
2992
2993 pci_restore_state(pdev);
2994 pci_enable_wake(pdev, PCI_D0, 0);
2995 sky2_set_power_state(hw, PCI_D0);
2996
2997 sky2_reset(hw);
2998
2999 for (i = 0; i < 2; i++) {
3000 struct net_device *dev = hw->dev[i];
3001 if (dev) {
3002 if (netif_running(dev)) {
3003 netif_device_attach(dev);
3004 sky2_up(dev);
3005 }
3006 }
3007 }
3008 return 0;
3009}
3010#endif
3011
3012static struct pci_driver sky2_driver = {
3013 .name = DRV_NAME,
3014 .id_table = sky2_id_table,
3015 .probe = sky2_probe,
3016 .remove = __devexit_p(sky2_remove),
3017#ifdef CONFIG_PM
3018 .suspend = sky2_suspend,
3019 .resume = sky2_resume,
3020#endif
3021};
3022
3023static int __init sky2_init_module(void)
3024{
3025 return pci_module_init(&sky2_driver);
3026}
3027
3028static void __exit sky2_cleanup_module(void)
3029{
3030 pci_unregister_driver(&sky2_driver);
3031}
3032
3033module_init(sky2_init_module);
3034module_exit(sky2_cleanup_module);
3035
3036MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3037MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3038MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-12 03:30:34 -0500