diff options
Diffstat (limited to 'drivers/net/sky2.c')
-rw-r--r-- | drivers/net/sky2.c | 127 |
1 files changed, 51 insertions, 76 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c index a2070db725c9..6197afb3ed83 100644 --- a/drivers/net/sky2.c +++ b/drivers/net/sky2.c | |||
@@ -31,7 +31,6 @@ | |||
31 | #include <linux/etherdevice.h> | 31 | #include <linux/etherdevice.h> |
32 | #include <linux/ethtool.h> | 32 | #include <linux/ethtool.h> |
33 | #include <linux/pci.h> | 33 | #include <linux/pci.h> |
34 | #include <linux/aer.h> | ||
35 | #include <linux/ip.h> | 34 | #include <linux/ip.h> |
36 | #include <net/ip.h> | 35 | #include <net/ip.h> |
37 | #include <linux/tcp.h> | 36 | #include <linux/tcp.h> |
@@ -240,22 +239,21 @@ static void sky2_power_on(struct sky2_hw *hw) | |||
240 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | 239 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); |
241 | 240 | ||
242 | if (hw->flags & SKY2_HW_ADV_POWER_CTL) { | 241 | if (hw->flags & SKY2_HW_ADV_POWER_CTL) { |
243 | struct pci_dev *pdev = hw->pdev; | ||
244 | u32 reg; | 242 | u32 reg; |
245 | 243 | ||
246 | pci_write_config_dword(pdev, PCI_DEV_REG3, 0); | 244 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
247 | 245 | ||
248 | pci_read_config_dword(pdev, PCI_DEV_REG4, ®); | 246 | reg = sky2_pci_read32(hw, PCI_DEV_REG4); |
249 | /* set all bits to 0 except bits 15..12 and 8 */ | 247 | /* set all bits to 0 except bits 15..12 and 8 */ |
250 | reg &= P_ASPM_CONTROL_MSK; | 248 | reg &= P_ASPM_CONTROL_MSK; |
251 | pci_write_config_dword(pdev, PCI_DEV_REG4, reg); | 249 | sky2_pci_write32(hw, PCI_DEV_REG4, reg); |
252 | 250 | ||
253 | pci_read_config_dword(pdev, PCI_DEV_REG5, ®); | 251 | reg = sky2_pci_read32(hw, PCI_DEV_REG5); |
254 | /* set all bits to 0 except bits 28 & 27 */ | 252 | /* set all bits to 0 except bits 28 & 27 */ |
255 | reg &= P_CTL_TIM_VMAIN_AV_MSK; | 253 | reg &= P_CTL_TIM_VMAIN_AV_MSK; |
256 | pci_write_config_dword(pdev, PCI_DEV_REG5, reg); | 254 | sky2_pci_write32(hw, PCI_DEV_REG5, reg); |
257 | 255 | ||
258 | pci_write_config_dword(pdev, PCI_CFG_REG_1, 0); | 256 | sky2_pci_write32(hw, PCI_CFG_REG_1, 0); |
259 | 257 | ||
260 | /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ | 258 | /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ |
261 | reg = sky2_read32(hw, B2_GP_IO); | 259 | reg = sky2_read32(hw, B2_GP_IO); |
@@ -619,12 +617,11 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |||
619 | 617 | ||
620 | static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff) | 618 | static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff) |
621 | { | 619 | { |
622 | struct pci_dev *pdev = hw->pdev; | ||
623 | u32 reg1; | 620 | u32 reg1; |
624 | static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; | 621 | static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; |
625 | static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; | 622 | static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; |
626 | 623 | ||
627 | pci_read_config_dword(pdev, PCI_DEV_REG1, ®1); | 624 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
628 | /* Turn on/off phy power saving */ | 625 | /* Turn on/off phy power saving */ |
629 | if (onoff) | 626 | if (onoff) |
630 | reg1 &= ~phy_power[port]; | 627 | reg1 &= ~phy_power[port]; |
@@ -634,8 +631,8 @@ static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff) | |||
634 | if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | 631 | if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) |
635 | reg1 |= coma_mode[port]; | 632 | reg1 |= coma_mode[port]; |
636 | 633 | ||
637 | pci_write_config_dword(pdev, PCI_DEV_REG1, reg1); | 634 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
638 | pci_read_config_dword(pdev, PCI_DEV_REG1, ®1); | 635 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
639 | 636 | ||
640 | udelay(100); | 637 | udelay(100); |
641 | } | 638 | } |
@@ -704,9 +701,9 @@ static void sky2_wol_init(struct sky2_port *sky2) | |||
704 | sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); | 701 | sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); |
705 | 702 | ||
706 | /* Turn on legacy PCI-Express PME mode */ | 703 | /* Turn on legacy PCI-Express PME mode */ |
707 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1); | 704 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
708 | reg1 |= PCI_Y2_PME_LEGACY; | 705 | reg1 |= PCI_Y2_PME_LEGACY; |
709 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1); | 706 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
710 | 707 | ||
711 | /* block receiver */ | 708 | /* block receiver */ |
712 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | 709 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); |
@@ -848,6 +845,13 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port) | |||
848 | sky2_set_tx_stfwd(hw, port); | 845 | sky2_set_tx_stfwd(hw, port); |
849 | } | 846 | } |
850 | 847 | ||
848 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && | ||
849 | hw->chip_rev == CHIP_REV_YU_FE2_A0) { | ||
850 | /* disable dynamic watermark */ | ||
851 | reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA)); | ||
852 | reg &= ~TX_DYN_WM_ENA; | ||
853 | sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg); | ||
854 | } | ||
851 | } | 855 | } |
852 | 856 | ||
853 | /* Assign Ram Buffer allocation to queue */ | 857 | /* Assign Ram Buffer allocation to queue */ |
@@ -1320,15 +1324,12 @@ static int sky2_up(struct net_device *dev) | |||
1320 | */ | 1324 | */ |
1321 | if (otherdev && netif_running(otherdev) && | 1325 | if (otherdev && netif_running(otherdev) && |
1322 | (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { | 1326 | (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { |
1323 | struct sky2_port *osky2 = netdev_priv(otherdev); | ||
1324 | u16 cmd; | 1327 | u16 cmd; |
1325 | 1328 | ||
1326 | pci_read_config_word(hw->pdev, cap + PCI_X_CMD, &cmd); | 1329 | cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); |
1327 | cmd &= ~PCI_X_CMD_MAX_SPLIT; | 1330 | cmd &= ~PCI_X_CMD_MAX_SPLIT; |
1328 | pci_write_config_word(hw->pdev, cap + PCI_X_CMD, cmd); | 1331 | sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); |
1329 | 1332 | ||
1330 | sky2->rx_csum = 0; | ||
1331 | osky2->rx_csum = 0; | ||
1332 | } | 1333 | } |
1333 | 1334 | ||
1334 | if (netif_msg_ifup(sky2)) | 1335 | if (netif_msg_ifup(sky2)) |
@@ -2426,37 +2427,26 @@ static void sky2_hw_intr(struct sky2_hw *hw) | |||
2426 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { | 2427 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { |
2427 | u16 pci_err; | 2428 | u16 pci_err; |
2428 | 2429 | ||
2429 | pci_read_config_word(pdev, PCI_STATUS, &pci_err); | 2430 | pci_err = sky2_pci_read16(hw, PCI_STATUS); |
2430 | if (net_ratelimit()) | 2431 | if (net_ratelimit()) |
2431 | dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", | 2432 | dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", |
2432 | pci_err); | 2433 | pci_err); |
2433 | 2434 | ||
2434 | pci_write_config_word(pdev, PCI_STATUS, | 2435 | sky2_pci_write16(hw, PCI_STATUS, |
2435 | pci_err | PCI_STATUS_ERROR_BITS); | 2436 | pci_err | PCI_STATUS_ERROR_BITS); |
2436 | } | 2437 | } |
2437 | 2438 | ||
2438 | if (status & Y2_IS_PCI_EXP) { | 2439 | if (status & Y2_IS_PCI_EXP) { |
2439 | /* PCI-Express uncorrectable Error occurred */ | 2440 | /* PCI-Express uncorrectable Error occurred */ |
2440 | int aer = pci_find_aer_capability(hw->pdev); | ||
2441 | u32 err; | 2441 | u32 err; |
2442 | 2442 | ||
2443 | if (aer) { | 2443 | err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); |
2444 | pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, | 2444 | sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, |
2445 | &err); | 2445 | 0xfffffffful); |
2446 | pci_cleanup_aer_uncorrect_error_status(pdev); | ||
2447 | } else { | ||
2448 | /* Either AER not configured, or not working | ||
2449 | * because of bad MMCONFIG, so just do recover | ||
2450 | * manually. | ||
2451 | */ | ||
2452 | err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); | ||
2453 | sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, | ||
2454 | 0xfffffffful); | ||
2455 | } | ||
2456 | |||
2457 | if (net_ratelimit()) | 2446 | if (net_ratelimit()) |
2458 | dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err); | 2447 | dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err); |
2459 | 2448 | ||
2449 | sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); | ||
2460 | } | 2450 | } |
2461 | 2451 | ||
2462 | if (status & Y2_HWE_L1_MASK) | 2452 | if (status & Y2_HWE_L1_MASK) |
@@ -2703,13 +2693,10 @@ static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) | |||
2703 | 2693 | ||
2704 | static int __devinit sky2_init(struct sky2_hw *hw) | 2694 | static int __devinit sky2_init(struct sky2_hw *hw) |
2705 | { | 2695 | { |
2706 | int rc; | ||
2707 | u8 t8; | 2696 | u8 t8; |
2708 | 2697 | ||
2709 | /* Enable all clocks and check for bad PCI access */ | 2698 | /* Enable all clocks and check for bad PCI access */ |
2710 | rc = pci_write_config_dword(hw->pdev, PCI_DEV_REG3, 0); | 2699 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
2711 | if (rc) | ||
2712 | return rc; | ||
2713 | 2700 | ||
2714 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | 2701 | sky2_write8(hw, B0_CTST, CS_RST_CLR); |
2715 | 2702 | ||
@@ -2806,32 +2793,21 @@ static void sky2_reset(struct sky2_hw *hw) | |||
2806 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | 2793 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
2807 | 2794 | ||
2808 | /* clear PCI errors, if any */ | 2795 | /* clear PCI errors, if any */ |
2809 | pci_read_config_word(pdev, PCI_STATUS, &status); | 2796 | status = sky2_pci_read16(hw, PCI_STATUS); |
2810 | status |= PCI_STATUS_ERROR_BITS; | 2797 | status |= PCI_STATUS_ERROR_BITS; |
2811 | pci_write_config_word(pdev, PCI_STATUS, status); | 2798 | sky2_pci_write16(hw, PCI_STATUS, status); |
2812 | 2799 | ||
2813 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); | 2800 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); |
2814 | 2801 | ||
2815 | cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); | 2802 | cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
2816 | if (cap) { | 2803 | if (cap) { |
2817 | if (pci_find_aer_capability(pdev)) { | 2804 | sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, |
2818 | /* Check for advanced error reporting */ | 2805 | 0xfffffffful); |
2819 | pci_cleanup_aer_uncorrect_error_status(pdev); | ||
2820 | pci_cleanup_aer_correct_error_status(pdev); | ||
2821 | } else { | ||
2822 | dev_warn(&pdev->dev, | ||
2823 | "PCI Express Advanced Error Reporting" | ||
2824 | " not configured or MMCONFIG problem?\n"); | ||
2825 | |||
2826 | sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, | ||
2827 | 0xfffffffful); | ||
2828 | } | ||
2829 | 2806 | ||
2830 | /* If error bit is stuck on ignore it */ | 2807 | /* If error bit is stuck on ignore it */ |
2831 | if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP) | 2808 | if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP) |
2832 | dev_info(&pdev->dev, "ignoring stuck error report bit\n"); | 2809 | dev_info(&pdev->dev, "ignoring stuck error report bit\n"); |
2833 | 2810 | else | |
2834 | else if (pci_enable_pcie_error_reporting(pdev)) | ||
2835 | hwe_mask |= Y2_IS_PCI_EXP; | 2811 | hwe_mask |= Y2_IS_PCI_EXP; |
2836 | } | 2812 | } |
2837 | 2813 | ||
@@ -2930,16 +2906,14 @@ static void sky2_restart(struct work_struct *work) | |||
2930 | int i, err; | 2906 | int i, err; |
2931 | 2907 | ||
2932 | rtnl_lock(); | 2908 | rtnl_lock(); |
2933 | sky2_write32(hw, B0_IMSK, 0); | ||
2934 | sky2_read32(hw, B0_IMSK); | ||
2935 | napi_disable(&hw->napi); | ||
2936 | |||
2937 | for (i = 0; i < hw->ports; i++) { | 2909 | for (i = 0; i < hw->ports; i++) { |
2938 | dev = hw->dev[i]; | 2910 | dev = hw->dev[i]; |
2939 | if (netif_running(dev)) | 2911 | if (netif_running(dev)) |
2940 | sky2_down(dev); | 2912 | sky2_down(dev); |
2941 | } | 2913 | } |
2942 | 2914 | ||
2915 | napi_disable(&hw->napi); | ||
2916 | sky2_write32(hw, B0_IMSK, 0); | ||
2943 | sky2_reset(hw); | 2917 | sky2_reset(hw); |
2944 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); | 2918 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); |
2945 | napi_enable(&hw->napi); | 2919 | napi_enable(&hw->napi); |
@@ -3672,32 +3646,33 @@ static int sky2_set_tso(struct net_device *dev, u32 data) | |||
3672 | static int sky2_get_eeprom_len(struct net_device *dev) | 3646 | static int sky2_get_eeprom_len(struct net_device *dev) |
3673 | { | 3647 | { |
3674 | struct sky2_port *sky2 = netdev_priv(dev); | 3648 | struct sky2_port *sky2 = netdev_priv(dev); |
3649 | struct sky2_hw *hw = sky2->hw; | ||
3675 | u16 reg2; | 3650 | u16 reg2; |
3676 | 3651 | ||
3677 | pci_read_config_word(sky2->hw->pdev, PCI_DEV_REG2, ®2); | 3652 | reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); |
3678 | return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); | 3653 | return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); |
3679 | } | 3654 | } |
3680 | 3655 | ||
3681 | static u32 sky2_vpd_read(struct pci_dev *pdev, int cap, u16 offset) | 3656 | static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset) |
3682 | { | 3657 | { |
3683 | u32 val; | 3658 | u32 val; |
3684 | 3659 | ||
3685 | pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset); | 3660 | sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset); |
3686 | 3661 | ||
3687 | do { | 3662 | do { |
3688 | pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset); | 3663 | offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR); |
3689 | } while (!(offset & PCI_VPD_ADDR_F)); | 3664 | } while (!(offset & PCI_VPD_ADDR_F)); |
3690 | 3665 | ||
3691 | pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val); | 3666 | val = sky2_pci_read32(hw, cap + PCI_VPD_DATA); |
3692 | return val; | 3667 | return val; |
3693 | } | 3668 | } |
3694 | 3669 | ||
3695 | static void sky2_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val) | 3670 | static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val) |
3696 | { | 3671 | { |
3697 | pci_write_config_word(pdev, cap + PCI_VPD_DATA, val); | 3672 | sky2_pci_write16(hw, cap + PCI_VPD_DATA, val); |
3698 | pci_write_config_dword(pdev, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F); | 3673 | sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F); |
3699 | do { | 3674 | do { |
3700 | pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset); | 3675 | offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR); |
3701 | } while (offset & PCI_VPD_ADDR_F); | 3676 | } while (offset & PCI_VPD_ADDR_F); |
3702 | } | 3677 | } |
3703 | 3678 | ||
@@ -3715,7 +3690,7 @@ static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom | |||
3715 | eeprom->magic = SKY2_EEPROM_MAGIC; | 3690 | eeprom->magic = SKY2_EEPROM_MAGIC; |
3716 | 3691 | ||
3717 | while (length > 0) { | 3692 | while (length > 0) { |
3718 | u32 val = sky2_vpd_read(sky2->hw->pdev, cap, offset); | 3693 | u32 val = sky2_vpd_read(sky2->hw, cap, offset); |
3719 | int n = min_t(int, length, sizeof(val)); | 3694 | int n = min_t(int, length, sizeof(val)); |
3720 | 3695 | ||
3721 | memcpy(data, &val, n); | 3696 | memcpy(data, &val, n); |
@@ -3745,10 +3720,10 @@ static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom | |||
3745 | int n = min_t(int, length, sizeof(val)); | 3720 | int n = min_t(int, length, sizeof(val)); |
3746 | 3721 | ||
3747 | if (n < sizeof(val)) | 3722 | if (n < sizeof(val)) |
3748 | val = sky2_vpd_read(sky2->hw->pdev, cap, offset); | 3723 | val = sky2_vpd_read(sky2->hw, cap, offset); |
3749 | memcpy(&val, data, n); | 3724 | memcpy(&val, data, n); |
3750 | 3725 | ||
3751 | sky2_vpd_write(sky2->hw->pdev, cap, offset, val); | 3726 | sky2_vpd_write(sky2->hw, cap, offset, val); |
3752 | 3727 | ||
3753 | length -= n; | 3728 | length -= n; |
3754 | data += n; | 3729 | data += n; |
@@ -4013,7 +3988,7 @@ static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, | |||
4013 | sky2->duplex = -1; | 3988 | sky2->duplex = -1; |
4014 | sky2->speed = -1; | 3989 | sky2->speed = -1; |
4015 | sky2->advertising = sky2_supported_modes(hw); | 3990 | sky2->advertising = sky2_supported_modes(hw); |
4016 | sky2->rx_csum = 1; | 3991 | sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL); |
4017 | sky2->wol = wol; | 3992 | sky2->wol = wol; |
4018 | 3993 | ||
4019 | spin_lock_init(&sky2->phy_lock); | 3994 | spin_lock_init(&sky2->phy_lock); |
@@ -4184,9 +4159,9 @@ static int __devinit sky2_probe(struct pci_dev *pdev, | |||
4184 | */ | 4159 | */ |
4185 | { | 4160 | { |
4186 | u32 reg; | 4161 | u32 reg; |
4187 | pci_read_config_dword(pdev,PCI_DEV_REG2, ®); | 4162 | reg = sky2_pci_read32(hw, PCI_DEV_REG2); |
4188 | reg &= ~PCI_REV_DESC; | 4163 | reg &= ~PCI_REV_DESC; |
4189 | pci_write_config_dword(pdev, PCI_DEV_REG2, reg); | 4164 | sky2_pci_write32(hw, PCI_DEV_REG2, reg); |
4190 | } | 4165 | } |
4191 | #endif | 4166 | #endif |
4192 | 4167 | ||
@@ -4377,7 +4352,7 @@ static int sky2_resume(struct pci_dev *pdev) | |||
4377 | if (hw->chip_id == CHIP_ID_YUKON_EX || | 4352 | if (hw->chip_id == CHIP_ID_YUKON_EX || |
4378 | hw->chip_id == CHIP_ID_YUKON_EC_U || | 4353 | hw->chip_id == CHIP_ID_YUKON_EC_U || |
4379 | hw->chip_id == CHIP_ID_YUKON_FE_P) | 4354 | hw->chip_id == CHIP_ID_YUKON_FE_P) |
4380 | pci_write_config_dword(pdev, PCI_DEV_REG3, 0); | 4355 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
4381 | 4356 | ||
4382 | sky2_reset(hw); | 4357 | sky2_reset(hw); |
4383 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); | 4358 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); |