diff options
Diffstat (limited to 'drivers/net/sky2.c')
-rw-r--r-- | drivers/net/sky2.c | 173 |
1 files changed, 104 insertions, 69 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c index bfeba5b9cd7a..ca8160d68229 100644 --- a/drivers/net/sky2.c +++ b/drivers/net/sky2.c | |||
@@ -195,11 +195,11 @@ static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) | |||
195 | pr_debug("sky2_set_power_state %d\n", state); | 195 | pr_debug("sky2_set_power_state %d\n", state); |
196 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | 196 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
197 | 197 | ||
198 | pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control); | 198 | power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC); |
199 | vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) && | 199 | vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) && |
200 | (power_control & PCI_PM_CAP_PME_D3cold); | 200 | (power_control & PCI_PM_CAP_PME_D3cold); |
201 | 201 | ||
202 | pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control); | 202 | power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL); |
203 | 203 | ||
204 | power_control |= PCI_PM_CTRL_PME_STATUS; | 204 | power_control |= PCI_PM_CTRL_PME_STATUS; |
205 | power_control &= ~(PCI_PM_CTRL_STATE_MASK); | 205 | power_control &= ~(PCI_PM_CTRL_STATE_MASK); |
@@ -223,7 +223,7 @@ static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) | |||
223 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | 223 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); |
224 | 224 | ||
225 | /* Turn off phy power saving */ | 225 | /* Turn off phy power saving */ |
226 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1); | 226 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
227 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | 227 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); |
228 | 228 | ||
229 | /* looks like this XL is back asswards .. */ | 229 | /* looks like this XL is back asswards .. */ |
@@ -232,18 +232,28 @@ static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) | |||
232 | if (hw->ports > 1) | 232 | if (hw->ports > 1) |
233 | reg1 |= PCI_Y2_PHY2_COMA; | 233 | reg1 |= PCI_Y2_PHY2_COMA; |
234 | } | 234 | } |
235 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1); | 235 | |
236 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | ||
237 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); | ||
238 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG4); | ||
239 | reg1 &= P_ASPM_CONTROL_MSK; | ||
240 | sky2_pci_write32(hw, PCI_DEV_REG4, reg1); | ||
241 | sky2_pci_write32(hw, PCI_DEV_REG5, 0); | ||
242 | } | ||
243 | |||
244 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); | ||
245 | |||
236 | break; | 246 | break; |
237 | 247 | ||
238 | case PCI_D3hot: | 248 | case PCI_D3hot: |
239 | case PCI_D3cold: | 249 | case PCI_D3cold: |
240 | /* Turn on phy power saving */ | 250 | /* Turn on phy power saving */ |
241 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1); | 251 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
242 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | 252 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) |
243 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | 253 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); |
244 | else | 254 | else |
245 | reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | 255 | reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); |
246 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1); | 256 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
247 | 257 | ||
248 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | 258 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) |
249 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | 259 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); |
@@ -265,7 +275,7 @@ static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) | |||
265 | ret = -1; | 275 | ret = -1; |
266 | } | 276 | } |
267 | 277 | ||
268 | pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control); | 278 | sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control); |
269 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | 279 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
270 | return ret; | 280 | return ret; |
271 | } | 281 | } |
@@ -463,16 +473,31 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |||
463 | ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); | 473 | ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); |
464 | } | 474 | } |
465 | 475 | ||
466 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | 476 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) { |
477 | /* apply fixes in PHY AFE */ | ||
478 | gm_phy_write(hw, port, 22, 255); | ||
479 | /* increase differential signal amplitude in 10BASE-T */ | ||
480 | gm_phy_write(hw, port, 24, 0xaa99); | ||
481 | gm_phy_write(hw, port, 23, 0x2011); | ||
467 | 482 | ||
468 | if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { | 483 | /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ |
469 | /* turn on 100 Mbps LED (LED_LINK100) */ | 484 | gm_phy_write(hw, port, 24, 0xa204); |
470 | ledover |= PHY_M_LED_MO_100(MO_LED_ON); | 485 | gm_phy_write(hw, port, 23, 0x2002); |
471 | } | ||
472 | 486 | ||
473 | if (ledover) | 487 | /* set page register to 0 */ |
474 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | 488 | gm_phy_write(hw, port, 22, 0); |
489 | } else { | ||
490 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | ||
475 | 491 | ||
492 | if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { | ||
493 | /* turn on 100 Mbps LED (LED_LINK100) */ | ||
494 | ledover |= PHY_M_LED_MO_100(MO_LED_ON); | ||
495 | } | ||
496 | |||
497 | if (ledover) | ||
498 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | ||
499 | |||
500 | } | ||
476 | /* Enable phy interrupt on auto-negotiation complete (or link up) */ | 501 | /* Enable phy interrupt on auto-negotiation complete (or link up) */ |
477 | if (sky2->autoneg == AUTONEG_ENABLE) | 502 | if (sky2->autoneg == AUTONEG_ENABLE) |
478 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); | 503 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); |
@@ -953,6 +978,12 @@ static int sky2_rx_start(struct sky2_port *sky2) | |||
953 | 978 | ||
954 | sky2->rx_put = sky2->rx_next = 0; | 979 | sky2->rx_put = sky2->rx_next = 0; |
955 | sky2_qset(hw, rxq); | 980 | sky2_qset(hw, rxq); |
981 | |||
982 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) { | ||
983 | /* MAC Rx RAM Read is controlled by hardware */ | ||
984 | sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); | ||
985 | } | ||
986 | |||
956 | sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); | 987 | sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); |
957 | 988 | ||
958 | rx_set_checksum(sky2); | 989 | rx_set_checksum(sky2); |
@@ -1035,9 +1066,10 @@ static int sky2_up(struct net_device *dev) | |||
1035 | RB_RST_SET); | 1066 | RB_RST_SET); |
1036 | 1067 | ||
1037 | sky2_qset(hw, txqaddr[port]); | 1068 | sky2_qset(hw, txqaddr[port]); |
1038 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) | ||
1039 | sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0); | ||
1040 | 1069 | ||
1070 | /* Set almost empty threshold */ | ||
1071 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1) | ||
1072 | sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0); | ||
1041 | 1073 | ||
1042 | sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, | 1074 | sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, |
1043 | TX_RING_SIZE - 1); | 1075 | TX_RING_SIZE - 1); |
@@ -1047,8 +1079,10 @@ static int sky2_up(struct net_device *dev) | |||
1047 | goto err_out; | 1079 | goto err_out; |
1048 | 1080 | ||
1049 | /* Enable interrupts from phy/mac for port */ | 1081 | /* Enable interrupts from phy/mac for port */ |
1082 | spin_lock_irq(&hw->hw_lock); | ||
1050 | hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2; | 1083 | hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2; |
1051 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | 1084 | sky2_write32(hw, B0_IMSK, hw->intr_mask); |
1085 | spin_unlock_irq(&hw->hw_lock); | ||
1052 | return 0; | 1086 | return 0; |
1053 | 1087 | ||
1054 | err_out: | 1088 | err_out: |
@@ -1348,10 +1382,10 @@ static int sky2_down(struct net_device *dev) | |||
1348 | netif_stop_queue(dev); | 1382 | netif_stop_queue(dev); |
1349 | 1383 | ||
1350 | /* Disable port IRQ */ | 1384 | /* Disable port IRQ */ |
1351 | local_irq_disable(); | 1385 | spin_lock_irq(&hw->hw_lock); |
1352 | hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2); | 1386 | hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2); |
1353 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | 1387 | sky2_write32(hw, B0_IMSK, hw->intr_mask); |
1354 | local_irq_enable(); | 1388 | spin_unlock_irq(&hw->hw_lock); |
1355 | 1389 | ||
1356 | flush_scheduled_work(); | 1390 | flush_scheduled_work(); |
1357 | 1391 | ||
@@ -1633,10 +1667,10 @@ static void sky2_phy_task(void *arg) | |||
1633 | out: | 1667 | out: |
1634 | up(&sky2->phy_sema); | 1668 | up(&sky2->phy_sema); |
1635 | 1669 | ||
1636 | local_irq_disable(); | 1670 | spin_lock_irq(&hw->hw_lock); |
1637 | hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2; | 1671 | hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2; |
1638 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | 1672 | sky2_write32(hw, B0_IMSK, hw->intr_mask); |
1639 | local_irq_enable(); | 1673 | spin_unlock_irq(&hw->hw_lock); |
1640 | } | 1674 | } |
1641 | 1675 | ||
1642 | 1676 | ||
@@ -1863,6 +1897,17 @@ static int sky2_poll(struct net_device *dev0, int *budget) | |||
1863 | 1897 | ||
1864 | sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); | 1898 | sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); |
1865 | 1899 | ||
1900 | /* | ||
1901 | * Kick the STAT_LEV_TIMER_CTRL timer. | ||
1902 | * This fixes my hangs on Yukon-EC (0xb6) rev 1. | ||
1903 | * The if clause is there to start the timer only if it has been | ||
1904 | * configured correctly and not been disabled via ethtool. | ||
1905 | */ | ||
1906 | if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_START) { | ||
1907 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); | ||
1908 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | ||
1909 | } | ||
1910 | |||
1866 | hwidx = sky2_read16(hw, STAT_PUT_IDX); | 1911 | hwidx = sky2_read16(hw, STAT_PUT_IDX); |
1867 | BUG_ON(hwidx >= STATUS_RING_SIZE); | 1912 | BUG_ON(hwidx >= STATUS_RING_SIZE); |
1868 | rmb(); | 1913 | rmb(); |
@@ -1945,16 +1990,19 @@ exit_loop: | |||
1945 | sky2_tx_check(hw, 0, tx_done[0]); | 1990 | sky2_tx_check(hw, 0, tx_done[0]); |
1946 | sky2_tx_check(hw, 1, tx_done[1]); | 1991 | sky2_tx_check(hw, 1, tx_done[1]); |
1947 | 1992 | ||
1993 | if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) { | ||
1994 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | ||
1995 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | ||
1996 | } | ||
1997 | |||
1948 | if (likely(work_done < to_do)) { | 1998 | if (likely(work_done < to_do)) { |
1949 | /* need to restart TX timer */ | 1999 | spin_lock_irq(&hw->hw_lock); |
1950 | if (is_ec_a1(hw)) { | 2000 | __netif_rx_complete(dev0); |
1951 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | ||
1952 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | ||
1953 | } | ||
1954 | 2001 | ||
1955 | netif_rx_complete(dev0); | ||
1956 | hw->intr_mask |= Y2_IS_STAT_BMU; | 2002 | hw->intr_mask |= Y2_IS_STAT_BMU; |
1957 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | 2003 | sky2_write32(hw, B0_IMSK, hw->intr_mask); |
2004 | spin_unlock_irq(&hw->hw_lock); | ||
2005 | |||
1958 | return 0; | 2006 | return 0; |
1959 | } else { | 2007 | } else { |
1960 | *budget -= work_done; | 2008 | *budget -= work_done; |
@@ -2017,13 +2065,13 @@ static void sky2_hw_intr(struct sky2_hw *hw) | |||
2017 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { | 2065 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { |
2018 | u16 pci_err; | 2066 | u16 pci_err; |
2019 | 2067 | ||
2020 | pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err); | 2068 | pci_err = sky2_pci_read16(hw, PCI_STATUS); |
2021 | if (net_ratelimit()) | 2069 | if (net_ratelimit()) |
2022 | printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n", | 2070 | printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n", |
2023 | pci_name(hw->pdev), pci_err); | 2071 | pci_name(hw->pdev), pci_err); |
2024 | 2072 | ||
2025 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | 2073 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
2026 | pci_write_config_word(hw->pdev, PCI_STATUS, | 2074 | sky2_pci_write16(hw, PCI_STATUS, |
2027 | pci_err | PCI_STATUS_ERROR_BITS); | 2075 | pci_err | PCI_STATUS_ERROR_BITS); |
2028 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | 2076 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
2029 | } | 2077 | } |
@@ -2032,7 +2080,7 @@ static void sky2_hw_intr(struct sky2_hw *hw) | |||
2032 | /* PCI-Express uncorrectable Error occurred */ | 2080 | /* PCI-Express uncorrectable Error occurred */ |
2033 | u32 pex_err; | 2081 | u32 pex_err; |
2034 | 2082 | ||
2035 | pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err); | 2083 | pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT); |
2036 | 2084 | ||
2037 | if (net_ratelimit()) | 2085 | if (net_ratelimit()) |
2038 | printk(KERN_ERR PFX "%s: pci express error (0x%x)\n", | 2086 | printk(KERN_ERR PFX "%s: pci express error (0x%x)\n", |
@@ -2040,7 +2088,7 @@ static void sky2_hw_intr(struct sky2_hw *hw) | |||
2040 | 2088 | ||
2041 | /* clear the interrupt */ | 2089 | /* clear the interrupt */ |
2042 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | 2090 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
2043 | pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT, | 2091 | sky2_pci_write32(hw, PEX_UNC_ERR_STAT, |
2044 | 0xffffffffUL); | 2092 | 0xffffffffUL); |
2045 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | 2093 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
2046 | 2094 | ||
@@ -2086,6 +2134,7 @@ static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) | |||
2086 | 2134 | ||
2087 | hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2); | 2135 | hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2); |
2088 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | 2136 | sky2_write32(hw, B0_IMSK, hw->intr_mask); |
2137 | |||
2089 | schedule_work(&sky2->phy_task); | 2138 | schedule_work(&sky2->phy_task); |
2090 | } | 2139 | } |
2091 | 2140 | ||
@@ -2099,6 +2148,7 @@ static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs) | |||
2099 | if (status == 0 || status == ~0) | 2148 | if (status == 0 || status == ~0) |
2100 | return IRQ_NONE; | 2149 | return IRQ_NONE; |
2101 | 2150 | ||
2151 | spin_lock(&hw->hw_lock); | ||
2102 | if (status & Y2_IS_HW_ERR) | 2152 | if (status & Y2_IS_HW_ERR) |
2103 | sky2_hw_intr(hw); | 2153 | sky2_hw_intr(hw); |
2104 | 2154 | ||
@@ -2127,7 +2177,7 @@ static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs) | |||
2127 | 2177 | ||
2128 | sky2_write32(hw, B0_Y2_SP_ICR, 2); | 2178 | sky2_write32(hw, B0_Y2_SP_ICR, 2); |
2129 | 2179 | ||
2130 | sky2_read32(hw, B0_IMSK); | 2180 | spin_unlock(&hw->hw_lock); |
2131 | 2181 | ||
2132 | return IRQ_HANDLED; | 2182 | return IRQ_HANDLED; |
2133 | } | 2183 | } |
@@ -2170,7 +2220,7 @@ static int sky2_reset(struct sky2_hw *hw) | |||
2170 | { | 2220 | { |
2171 | u16 status; | 2221 | u16 status; |
2172 | u8 t8, pmd_type; | 2222 | u8 t8, pmd_type; |
2173 | int i, err; | 2223 | int i; |
2174 | 2224 | ||
2175 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | 2225 | sky2_write8(hw, B0_CTST, CS_RST_CLR); |
2176 | 2226 | ||
@@ -2192,25 +2242,18 @@ static int sky2_reset(struct sky2_hw *hw) | |||
2192 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | 2242 | sky2_write8(hw, B0_CTST, CS_RST_CLR); |
2193 | 2243 | ||
2194 | /* clear PCI errors, if any */ | 2244 | /* clear PCI errors, if any */ |
2195 | err = pci_read_config_word(hw->pdev, PCI_STATUS, &status); | 2245 | status = sky2_pci_read16(hw, PCI_STATUS); |
2196 | if (err) | ||
2197 | goto pci_err; | ||
2198 | 2246 | ||
2199 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | 2247 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
2200 | err = pci_write_config_word(hw->pdev, PCI_STATUS, | 2248 | sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS); |
2201 | status | PCI_STATUS_ERROR_BITS); | 2249 | |
2202 | if (err) | ||
2203 | goto pci_err; | ||
2204 | 2250 | ||
2205 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); | 2251 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); |
2206 | 2252 | ||
2207 | /* clear any PEX errors */ | 2253 | /* clear any PEX errors */ |
2208 | if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) { | 2254 | if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) |
2209 | err = pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT, | 2255 | sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL); |
2210 | 0xffffffffUL); | 2256 | |
2211 | if (err) | ||
2212 | goto pci_err; | ||
2213 | } | ||
2214 | 2257 | ||
2215 | pmd_type = sky2_read8(hw, B2_PMD_TYP); | 2258 | pmd_type = sky2_read8(hw, B2_PMD_TYP); |
2216 | hw->copper = !(pmd_type == 'L' || pmd_type == 'S'); | 2259 | hw->copper = !(pmd_type == 'L' || pmd_type == 'S'); |
@@ -2309,8 +2352,7 @@ static int sky2_reset(struct sky2_hw *hw) | |||
2309 | sky2_write8(hw, STAT_FIFO_ISR_WM, 16); | 2352 | sky2_write8(hw, STAT_FIFO_ISR_WM, 16); |
2310 | 2353 | ||
2311 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); | 2354 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); |
2312 | sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); | 2355 | sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 7)); |
2313 | sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); | ||
2314 | } | 2356 | } |
2315 | 2357 | ||
2316 | /* enable status unit */ | 2358 | /* enable status unit */ |
@@ -2321,14 +2363,6 @@ static int sky2_reset(struct sky2_hw *hw) | |||
2321 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | 2363 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); |
2322 | 2364 | ||
2323 | return 0; | 2365 | return 0; |
2324 | |||
2325 | pci_err: | ||
2326 | /* This is to catch a BIOS bug workaround where | ||
2327 | * mmconfig table doesn't have other buses. | ||
2328 | */ | ||
2329 | printk(KERN_ERR PFX "%s: can't access PCI config space\n", | ||
2330 | pci_name(hw->pdev)); | ||
2331 | return err; | ||
2332 | } | 2366 | } |
2333 | 2367 | ||
2334 | static u32 sky2_supported_modes(const struct sky2_hw *hw) | 2368 | static u32 sky2_supported_modes(const struct sky2_hw *hw) |
@@ -2852,11 +2886,11 @@ static int sky2_set_coalesce(struct net_device *dev, | |||
2852 | (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax)) | 2886 | (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax)) |
2853 | return -EINVAL; | 2887 | return -EINVAL; |
2854 | 2888 | ||
2855 | if (ecmd->tx_max_coalesced_frames > 0xffff) | 2889 | if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1) |
2856 | return -EINVAL; | 2890 | return -EINVAL; |
2857 | if (ecmd->rx_max_coalesced_frames > 0xff) | 2891 | if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) |
2858 | return -EINVAL; | 2892 | return -EINVAL; |
2859 | if (ecmd->rx_max_coalesced_frames_irq > 0xff) | 2893 | if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING) |
2860 | return -EINVAL; | 2894 | return -EINVAL; |
2861 | 2895 | ||
2862 | if (ecmd->tx_coalesce_usecs == 0) | 2896 | if (ecmd->tx_coalesce_usecs == 0) |
@@ -3198,17 +3232,6 @@ static int __devinit sky2_probe(struct pci_dev *pdev, | |||
3198 | } | 3232 | } |
3199 | } | 3233 | } |
3200 | 3234 | ||
3201 | #ifdef __BIG_ENDIAN | ||
3202 | /* byte swap descriptors in hardware */ | ||
3203 | { | ||
3204 | u32 reg; | ||
3205 | |||
3206 | pci_read_config_dword(pdev, PCI_DEV_REG2, ®); | ||
3207 | reg |= PCI_REV_DESC; | ||
3208 | pci_write_config_dword(pdev, PCI_DEV_REG2, reg); | ||
3209 | } | ||
3210 | #endif | ||
3211 | |||
3212 | err = -ENOMEM; | 3235 | err = -ENOMEM; |
3213 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); | 3236 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); |
3214 | if (!hw) { | 3237 | if (!hw) { |
@@ -3226,6 +3249,18 @@ static int __devinit sky2_probe(struct pci_dev *pdev, | |||
3226 | goto err_out_free_hw; | 3249 | goto err_out_free_hw; |
3227 | } | 3250 | } |
3228 | hw->pm_cap = pm_cap; | 3251 | hw->pm_cap = pm_cap; |
3252 | spin_lock_init(&hw->hw_lock); | ||
3253 | |||
3254 | #ifdef __BIG_ENDIAN | ||
3255 | /* byte swap descriptors in hardware */ | ||
3256 | { | ||
3257 | u32 reg; | ||
3258 | |||
3259 | reg = sky2_pci_read32(hw, PCI_DEV_REG2); | ||
3260 | reg |= PCI_REV_DESC; | ||
3261 | sky2_pci_write32(hw, PCI_DEV_REG2, reg); | ||
3262 | } | ||
3263 | #endif | ||
3229 | 3264 | ||
3230 | /* ring for status responses */ | 3265 | /* ring for status responses */ |
3231 | hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES, | 3266 | hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES, |