diff options
Diffstat (limited to 'drivers/net/skge.h')
| -rw-r--r-- | drivers/net/skge.h | 37 |
1 files changed, 30 insertions, 7 deletions
diff --git a/drivers/net/skge.h b/drivers/net/skge.h index 79e09271bcf9..d0b47d46cf9d 100644 --- a/drivers/net/skge.h +++ b/drivers/net/skge.h | |||
| @@ -934,7 +934,7 @@ enum { | |||
| 934 | PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */ | 934 | PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */ |
| 935 | PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */ | 935 | PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */ |
| 936 | PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */ | 936 | PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */ |
| 937 | PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */ | 937 | PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */ |
| 938 | PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */ | 938 | PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */ |
| 939 | 939 | ||
| 940 | PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */ | 940 | PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */ |
| @@ -1097,13 +1097,36 @@ enum { | |||
| 1097 | 1097 | ||
| 1098 | /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */ | 1098 | /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */ |
| 1099 | enum { | 1099 | enum { |
| 1100 | PHY_X_P_NO_PAUSE = 0<<7,/* Bit 8..7: no Pause Mode */ | 1100 | PHY_X_P_NO_PAUSE= 0<<7,/* Bit 8..7: no Pause Mode */ |
| 1101 | PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */ | 1101 | PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */ |
| 1102 | PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */ | 1102 | PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */ |
| 1103 | PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */ | 1103 | PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */ |
| 1104 | }; | 1104 | }; |
| 1105 | 1105 | ||
| 1106 | 1106 | ||
| 1107 | /***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/ | ||
| 1108 | enum { | ||
| 1109 | PHY_X_EX_FD = 1<<15, /* Bit 15: Device Supports Full Duplex */ | ||
| 1110 | PHY_X_EX_HD = 1<<14, /* Bit 14: Device Supports Half Duplex */ | ||
| 1111 | }; | ||
| 1112 | |||
| 1113 | /***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/ | ||
| 1114 | enum { | ||
| 1115 | PHY_X_RS_PAUSE = 3<<7, /* Bit 8..7: selected Pause Mode */ | ||
| 1116 | PHY_X_RS_HD = 1<<6, /* Bit 6: Half Duplex Mode selected */ | ||
| 1117 | PHY_X_RS_FD = 1<<5, /* Bit 5: Full Duplex Mode selected */ | ||
| 1118 | PHY_X_RS_ABLMIS = 1<<4, /* Bit 4: duplex or pause cap mismatch */ | ||
| 1119 | PHY_X_RS_PAUMIS = 1<<3, /* Bit 3: pause capability mismatch */ | ||
| 1120 | }; | ||
| 1121 | |||
| 1122 | /* Remote Fault Bits (PHY_X_AN_RFB) encoding */ | ||
| 1123 | enum { | ||
| 1124 | X_RFB_OK = 0<<12,/* Bit 13..12 No errors, Link OK */ | ||
| 1125 | X_RFB_LF = 1<<12,/* Bit 13..12 Link Failure */ | ||
| 1126 | X_RFB_OFF = 2<<12,/* Bit 13..12 Offline */ | ||
| 1127 | X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */ | ||
| 1128 | }; | ||
| 1129 | |||
| 1107 | /* Broadcom-Specific */ | 1130 | /* Broadcom-Specific */ |
| 1108 | /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ | 1131 | /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ |
| 1109 | enum { | 1132 | enum { |
| @@ -2158,8 +2181,8 @@ enum { | |||
| 2158 | XM_IS_LNK_AE = 1<<14, /* Bit 14: Link Asynchronous Event */ | 2181 | XM_IS_LNK_AE = 1<<14, /* Bit 14: Link Asynchronous Event */ |
| 2159 | XM_IS_TX_ABORT = 1<<13, /* Bit 13: Transmit Abort, late Col. etc */ | 2182 | XM_IS_TX_ABORT = 1<<13, /* Bit 13: Transmit Abort, late Col. etc */ |
| 2160 | XM_IS_FRC_INT = 1<<12, /* Bit 12: Force INT bit set in GP */ | 2183 | XM_IS_FRC_INT = 1<<12, /* Bit 12: Force INT bit set in GP */ |
| 2161 | XM_IS_INP_ASS = 1<<11, /* Bit 11: Input Asserted, GP bit 0 set */ | 2184 | XM_IS_INP_ASS = 1<<11, /* Bit 11: Input Asserted, GP bit 0 set */ |
| 2162 | XM_IS_LIPA_RC = 1<<10, /* Bit 10: Link Partner requests config */ | 2185 | XM_IS_LIPA_RC = 1<<10, /* Bit 10: Link Partner requests config */ |
| 2163 | XM_IS_RX_PAGE = 1<<9, /* Bit 9: Page Received */ | 2186 | XM_IS_RX_PAGE = 1<<9, /* Bit 9: Page Received */ |
| 2164 | XM_IS_TX_PAGE = 1<<8, /* Bit 8: Next Page Loaded for Transmit */ | 2187 | XM_IS_TX_PAGE = 1<<8, /* Bit 8: Next Page Loaded for Transmit */ |
| 2165 | XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */ | 2188 | XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */ |
| @@ -2172,9 +2195,7 @@ enum { | |||
| 2172 | XM_IS_RX_COMP = 1<<0, /* Bit 0: Frame Rx Complete */ | 2195 | XM_IS_RX_COMP = 1<<0, /* Bit 0: Frame Rx Complete */ |
| 2173 | }; | 2196 | }; |
| 2174 | 2197 | ||
| 2175 | #define XM_DEF_MSK (~(XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | \ | 2198 | #define XM_DEF_MSK (~(XM_IS_RXC_OV | XM_IS_TXC_OV | XM_IS_RXF_OV | XM_IS_TXF_UR)) |
| 2176 | XM_IS_AND | XM_IS_RXC_OV | XM_IS_TXC_OV | \ | ||
| 2177 | XM_IS_RXF_OV | XM_IS_TXF_UR)) | ||
| 2178 | 2199 | ||
| 2179 | 2200 | ||
| 2180 | /* XM_HW_CFG 16 bit r/w Hardware Config Register */ | 2201 | /* XM_HW_CFG 16 bit r/w Hardware Config Register */ |
| @@ -2396,6 +2417,7 @@ struct skge_hw { | |||
| 2396 | u8 chip_rev; | 2417 | u8 chip_rev; |
| 2397 | u8 copper; | 2418 | u8 copper; |
| 2398 | u8 ports; | 2419 | u8 ports; |
| 2420 | u8 phy_type; | ||
| 2399 | 2421 | ||
| 2400 | u32 ram_size; | 2422 | u32 ram_size; |
| 2401 | u32 ram_offset; | 2423 | u32 ram_offset; |
| @@ -2422,6 +2444,7 @@ struct skge_port { | |||
| 2422 | 2444 | ||
| 2423 | struct net_device_stats net_stats; | 2445 | struct net_device_stats net_stats; |
| 2424 | 2446 | ||
| 2447 | struct work_struct link_thread; | ||
| 2425 | u8 rx_csum; | 2448 | u8 rx_csum; |
| 2426 | u8 blink_on; | 2449 | u8 blink_on; |
| 2427 | u8 flow_control; | 2450 | u8 flow_control; |
