aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/skge.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/skge.c')
-rw-r--r--drivers/net/skge.c577
1 files changed, 375 insertions, 202 deletions
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index 19a4a16055dc..705e9a8fa30f 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -24,7 +24,6 @@
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */ 25 */
26 26
27#include <linux/config.h>
28#include <linux/in.h> 27#include <linux/in.h>
29#include <linux/kernel.h> 28#include <linux/kernel.h>
30#include <linux/module.h> 29#include <linux/module.h>
@@ -44,7 +43,7 @@
44#include "skge.h" 43#include "skge.h"
45 44
46#define DRV_NAME "skge" 45#define DRV_NAME "skge"
47#define DRV_VERSION "1.6" 46#define DRV_VERSION "1.8"
48#define PFX DRV_NAME " " 47#define PFX DRV_NAME " "
49 48
50#define DEFAULT_TX_RING_SIZE 128 49#define DEFAULT_TX_RING_SIZE 128
@@ -59,6 +58,7 @@
59#define TX_WATCHDOG (5 * HZ) 58#define TX_WATCHDOG (5 * HZ)
60#define NAPI_WEIGHT 64 59#define NAPI_WEIGHT 64
61#define BLINK_MS 250 60#define BLINK_MS 250
61#define LINK_HZ (HZ/2)
62 62
63MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver"); 63MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
64MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>"); 64MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
@@ -92,7 +92,7 @@ MODULE_DEVICE_TABLE(pci, skge_id_table);
92static int skge_up(struct net_device *dev); 92static int skge_up(struct net_device *dev);
93static int skge_down(struct net_device *dev); 93static int skge_down(struct net_device *dev);
94static void skge_phy_reset(struct skge_port *skge); 94static void skge_phy_reset(struct skge_port *skge);
95static void skge_tx_clean(struct skge_port *skge); 95static void skge_tx_clean(struct net_device *dev);
96static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); 96static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); 97static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
98static void genesis_get_stats(struct skge_port *skge, u64 *data); 98static void genesis_get_stats(struct skge_port *skge, u64 *data);
@@ -106,6 +106,7 @@ static const int txqaddr[] = { Q_XA1, Q_XA2 };
106static const int rxqaddr[] = { Q_R1, Q_R2 }; 106static const int rxqaddr[] = { Q_R1, Q_R2 };
107static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F }; 107static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
108static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F }; 108static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
109static const u32 irqmask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
109 110
110static int skge_get_regs_len(struct net_device *dev) 111static int skge_get_regs_len(struct net_device *dev)
111{ 112{
@@ -517,10 +518,7 @@ static int skge_set_pauseparam(struct net_device *dev,
517/* Chip internal frequency for clock calculations */ 518/* Chip internal frequency for clock calculations */
518static inline u32 hwkhz(const struct skge_hw *hw) 519static inline u32 hwkhz(const struct skge_hw *hw)
519{ 520{
520 if (hw->chip_id == CHIP_ID_GENESIS) 521 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
521 return 53215; /* or: 53.125 MHz */
522 else
523 return 78215; /* or: 78.125 MHz */
524} 522}
525 523
526/* Chip HZ to microseconds */ 524/* Chip HZ to microseconds */
@@ -608,7 +606,12 @@ static void skge_led(struct skge_port *skge, enum led_mode mode)
608 if (hw->chip_id == CHIP_ID_GENESIS) { 606 if (hw->chip_id == CHIP_ID_GENESIS) {
609 switch (mode) { 607 switch (mode) {
610 case LED_MODE_OFF: 608 case LED_MODE_OFF:
611 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF); 609 if (hw->phy_type == SK_PHY_BCOM)
610 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
611 else {
612 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
613 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
614 }
612 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); 615 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
613 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0); 616 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
614 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF); 617 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
@@ -628,8 +631,14 @@ static void skge_led(struct skge_port *skge, enum led_mode mode)
628 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100); 631 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
629 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); 632 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
630 633
631 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON); 634 if (hw->phy_type == SK_PHY_BCOM)
632 break; 635 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
636 else {
637 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
638 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
639 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
640 }
641
633 } 642 }
634 } else { 643 } else {
635 switch (mode) { 644 switch (mode) {
@@ -694,7 +703,7 @@ static int skge_phys_id(struct net_device *dev, u32 data)
694 return 0; 703 return 0;
695} 704}
696 705
697static struct ethtool_ops skge_ethtool_ops = { 706static const struct ethtool_ops skge_ethtool_ops = {
698 .get_settings = skge_get_settings, 707 .get_settings = skge_get_settings,
699 .set_settings = skge_set_settings, 708 .set_settings = skge_set_settings,
700 .get_drvinfo = skge_get_drvinfo, 709 .get_drvinfo = skge_get_drvinfo,
@@ -822,8 +831,9 @@ static void skge_rx_clean(struct skge_port *skge)
822/* Allocate buffers for receive ring 831/* Allocate buffers for receive ring
823 * For receive: to_clean is next received frame. 832 * For receive: to_clean is next received frame.
824 */ 833 */
825static int skge_rx_fill(struct skge_port *skge) 834static int skge_rx_fill(struct net_device *dev)
826{ 835{
836 struct skge_port *skge = netdev_priv(dev);
827 struct skge_ring *ring = &skge->rx_ring; 837 struct skge_ring *ring = &skge->rx_ring;
828 struct skge_element *e; 838 struct skge_element *e;
829 839
@@ -831,7 +841,8 @@ static int skge_rx_fill(struct skge_port *skge)
831 do { 841 do {
832 struct sk_buff *skb; 842 struct sk_buff *skb;
833 843
834 skb = alloc_skb(skge->rx_buf_size + NET_IP_ALIGN, GFP_KERNEL); 844 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
845 GFP_KERNEL);
835 if (!skb) 846 if (!skb)
836 return -ENOMEM; 847 return -ENOMEM;
837 848
@@ -880,6 +891,9 @@ static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
880 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); 891 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
881 *val = xm_read16(hw, port, XM_PHY_DATA); 892 *val = xm_read16(hw, port, XM_PHY_DATA);
882 893
894 if (hw->phy_type == SK_PHY_XMAC)
895 goto ready;
896
883 for (i = 0; i < PHY_RETRIES; i++) { 897 for (i = 0; i < PHY_RETRIES; i++) {
884 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY) 898 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
885 goto ready; 899 goto ready;
@@ -966,7 +980,8 @@ static void genesis_reset(struct skge_hw *hw, int port)
966 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ 980 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
967 981
968 /* disable Broadcom PHY IRQ */ 982 /* disable Broadcom PHY IRQ */
969 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff); 983 if (hw->phy_type == SK_PHY_BCOM)
984 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
970 985
971 xm_outhash(hw, port, XM_HSM, zero); 986 xm_outhash(hw, port, XM_HSM, zero);
972} 987}
@@ -1001,60 +1016,64 @@ static void bcom_check_link(struct skge_hw *hw, int port)
1001 1016
1002 if (netif_carrier_ok(dev)) 1017 if (netif_carrier_ok(dev))
1003 skge_link_down(skge); 1018 skge_link_down(skge);
1004 } else { 1019 return;
1005 if (skge->autoneg == AUTONEG_ENABLE && 1020 }
1006 (status & PHY_ST_AN_OVER)) {
1007 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1008 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1009
1010 if (lpa & PHY_B_AN_RF) {
1011 printk(KERN_NOTICE PFX "%s: remote fault\n",
1012 dev->name);
1013 return;
1014 }
1015 1021
1016 /* Check Duplex mismatch */ 1022 if (skge->autoneg == AUTONEG_ENABLE) {
1017 switch (aux & PHY_B_AS_AN_RES_MSK) { 1023 u16 lpa, aux;
1018 case PHY_B_RES_1000FD:
1019 skge->duplex = DUPLEX_FULL;
1020 break;
1021 case PHY_B_RES_1000HD:
1022 skge->duplex = DUPLEX_HALF;
1023 break;
1024 default:
1025 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1026 dev->name);
1027 return;
1028 }
1029 1024
1025 if (!(status & PHY_ST_AN_OVER))
1026 return;
1030 1027
1031 /* We are using IEEE 802.3z/D5.0 Table 37-4 */ 1028 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1032 switch (aux & PHY_B_AS_PAUSE_MSK) { 1029 if (lpa & PHY_B_AN_RF) {
1033 case PHY_B_AS_PAUSE_MSK: 1030 printk(KERN_NOTICE PFX "%s: remote fault\n",
1034 skge->flow_control = FLOW_MODE_SYMMETRIC; 1031 dev->name);
1035 break; 1032 return;
1036 case PHY_B_AS_PRR: 1033 }
1037 skge->flow_control = FLOW_MODE_REM_SEND; 1034
1038 break; 1035 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1039 case PHY_B_AS_PRT:
1040 skge->flow_control = FLOW_MODE_LOC_SEND;
1041 break;
1042 default:
1043 skge->flow_control = FLOW_MODE_NONE;
1044 }
1045 1036
1046 skge->speed = SPEED_1000; 1037 /* Check Duplex mismatch */
1038 switch (aux & PHY_B_AS_AN_RES_MSK) {
1039 case PHY_B_RES_1000FD:
1040 skge->duplex = DUPLEX_FULL;
1041 break;
1042 case PHY_B_RES_1000HD:
1043 skge->duplex = DUPLEX_HALF;
1044 break;
1045 default:
1046 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1047 dev->name);
1048 return;
1047 } 1049 }
1048 1050
1049 if (!netif_carrier_ok(dev)) 1051
1050 genesis_link_up(skge); 1052 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1053 switch (aux & PHY_B_AS_PAUSE_MSK) {
1054 case PHY_B_AS_PAUSE_MSK:
1055 skge->flow_control = FLOW_MODE_SYMMETRIC;
1056 break;
1057 case PHY_B_AS_PRR:
1058 skge->flow_control = FLOW_MODE_REM_SEND;
1059 break;
1060 case PHY_B_AS_PRT:
1061 skge->flow_control = FLOW_MODE_LOC_SEND;
1062 break;
1063 default:
1064 skge->flow_control = FLOW_MODE_NONE;
1065 }
1066 skge->speed = SPEED_1000;
1051 } 1067 }
1068
1069 if (!netif_carrier_ok(dev))
1070 genesis_link_up(skge);
1052} 1071}
1053 1072
1054/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional 1073/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1055 * Phy on for 100 or 10Mbit operation 1074 * Phy on for 100 or 10Mbit operation
1056 */ 1075 */
1057static void bcom_phy_init(struct skge_port *skge, int jumbo) 1076static void bcom_phy_init(struct skge_port *skge)
1058{ 1077{
1059 struct skge_hw *hw = skge->hw; 1078 struct skge_hw *hw = skge->hw;
1060 int port = skge->port; 1079 int port = skge->port;
@@ -1145,7 +1164,7 @@ static void bcom_phy_init(struct skge_port *skge, int jumbo)
1145 phy_pause_map[skge->flow_control] | PHY_AN_CSMA); 1164 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1146 1165
1147 /* Handle Jumbo frames */ 1166 /* Handle Jumbo frames */
1148 if (jumbo) { 1167 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1149 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, 1168 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1150 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK); 1169 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1151 1170
@@ -1158,8 +1177,154 @@ static void bcom_phy_init(struct skge_port *skge, int jumbo)
1158 1177
1159 /* Use link status change interrupt */ 1178 /* Use link status change interrupt */
1160 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); 1179 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1180}
1181
1182static void xm_phy_init(struct skge_port *skge)
1183{
1184 struct skge_hw *hw = skge->hw;
1185 int port = skge->port;
1186 u16 ctrl = 0;
1187
1188 if (skge->autoneg == AUTONEG_ENABLE) {
1189 if (skge->advertising & ADVERTISED_1000baseT_Half)
1190 ctrl |= PHY_X_AN_HD;
1191 if (skge->advertising & ADVERTISED_1000baseT_Full)
1192 ctrl |= PHY_X_AN_FD;
1193
1194 switch(skge->flow_control) {
1195 case FLOW_MODE_NONE:
1196 ctrl |= PHY_X_P_NO_PAUSE;
1197 break;
1198 case FLOW_MODE_LOC_SEND:
1199 ctrl |= PHY_X_P_ASYM_MD;
1200 break;
1201 case FLOW_MODE_SYMMETRIC:
1202 ctrl |= PHY_X_P_BOTH_MD;
1203 break;
1204 }
1205
1206 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1207
1208 /* Restart Auto-negotiation */
1209 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1210 } else {
1211 /* Set DuplexMode in Config register */
1212 if (skge->duplex == DUPLEX_FULL)
1213 ctrl |= PHY_CT_DUP_MD;
1214 /*
1215 * Do NOT enable Auto-negotiation here. This would hold
1216 * the link down because no IDLEs are transmitted
1217 */
1218 }
1219
1220 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1221
1222 /* Poll PHY for status changes */
1223 schedule_delayed_work(&skge->link_thread, LINK_HZ);
1224}
1225
1226static void xm_check_link(struct net_device *dev)
1227{
1228 struct skge_port *skge = netdev_priv(dev);
1229 struct skge_hw *hw = skge->hw;
1230 int port = skge->port;
1231 u16 status;
1232
1233 /* read twice because of latch */
1234 (void) xm_phy_read(hw, port, PHY_XMAC_STAT);
1235 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1236
1237 if ((status & PHY_ST_LSYNC) == 0) {
1238 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1239 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1240 xm_write16(hw, port, XM_MMU_CMD, cmd);
1241 /* dummy read to ensure writing */
1242 (void) xm_read16(hw, port, XM_MMU_CMD);
1243
1244 if (netif_carrier_ok(dev))
1245 skge_link_down(skge);
1246 return;
1247 }
1248
1249 if (skge->autoneg == AUTONEG_ENABLE) {
1250 u16 lpa, res;
1251
1252 if (!(status & PHY_ST_AN_OVER))
1253 return;
1254
1255 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1256 if (lpa & PHY_B_AN_RF) {
1257 printk(KERN_NOTICE PFX "%s: remote fault\n",
1258 dev->name);
1259 return;
1260 }
1261
1262 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1263
1264 /* Check Duplex mismatch */
1265 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1266 case PHY_X_RS_FD:
1267 skge->duplex = DUPLEX_FULL;
1268 break;
1269 case PHY_X_RS_HD:
1270 skge->duplex = DUPLEX_HALF;
1271 break;
1272 default:
1273 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1274 dev->name);
1275 return;
1276 }
1277
1278 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1279 if (lpa & PHY_X_P_SYM_MD)
1280 skge->flow_control = FLOW_MODE_SYMMETRIC;
1281 else if ((lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1282 skge->flow_control = FLOW_MODE_REM_SEND;
1283 else if ((lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1284 skge->flow_control = FLOW_MODE_LOC_SEND;
1285 else
1286 skge->flow_control = FLOW_MODE_NONE;
1287
1288
1289 skge->speed = SPEED_1000;
1290 }
1291
1292 if (!netif_carrier_ok(dev))
1293 genesis_link_up(skge);
1294}
1295
1296/* Poll to check for link coming up.
1297 * Since internal PHY is wired to a level triggered pin, can't
1298 * get an interrupt when carrier is detected.
1299 */
1300static void xm_link_timer(void *arg)
1301{
1302 struct net_device *dev = arg;
1303 struct skge_port *skge = netdev_priv(arg);
1304 struct skge_hw *hw = skge->hw;
1305 int port = skge->port;
1306
1307 if (!netif_running(dev))
1308 return;
1309
1310 if (netif_carrier_ok(dev)) {
1311 xm_read16(hw, port, XM_ISRC);
1312 if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS))
1313 goto nochange;
1314 } else {
1315 if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1316 goto nochange;
1317 xm_read16(hw, port, XM_ISRC);
1318 if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1319 goto nochange;
1320 }
1321
1322 mutex_lock(&hw->phy_mutex);
1323 xm_check_link(dev);
1324 mutex_unlock(&hw->phy_mutex);
1161 1325
1162 bcom_check_link(hw, port); 1326nochange:
1327 schedule_delayed_work(&skge->link_thread, LINK_HZ);
1163} 1328}
1164 1329
1165static void genesis_mac_init(struct skge_hw *hw, int port) 1330static void genesis_mac_init(struct skge_hw *hw, int port)
@@ -1190,20 +1355,29 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1190 * namely for the 1000baseTX cards that use the XMAC's 1355 * namely for the 1000baseTX cards that use the XMAC's
1191 * GMII mode. 1356 * GMII mode.
1192 */ 1357 */
1193 /* Take external Phy out of reset */ 1358 if (hw->phy_type != SK_PHY_XMAC) {
1194 r = skge_read32(hw, B2_GP_IO); 1359 /* Take external Phy out of reset */
1195 if (port == 0) 1360 r = skge_read32(hw, B2_GP_IO);
1196 r |= GP_DIR_0|GP_IO_0; 1361 if (port == 0)
1197 else 1362 r |= GP_DIR_0|GP_IO_0;
1198 r |= GP_DIR_2|GP_IO_2; 1363 else
1364 r |= GP_DIR_2|GP_IO_2;
1199 1365
1200 skge_write32(hw, B2_GP_IO, r); 1366 skge_write32(hw, B2_GP_IO, r);
1201 1367
1368 /* Enable GMII interface */
1369 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1370 }
1202 1371
1203 /* Enable GMII interface */
1204 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1205 1372
1206 bcom_phy_init(skge, jumbo); 1373 switch(hw->phy_type) {
1374 case SK_PHY_XMAC:
1375 xm_phy_init(skge);
1376 break;
1377 case SK_PHY_BCOM:
1378 bcom_phy_init(skge);
1379 bcom_check_link(hw, port);
1380 }
1207 1381
1208 /* Set Station Address */ 1382 /* Set Station Address */
1209 xm_outaddr(hw, port, XM_SA, dev->dev_addr); 1383 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
@@ -1336,16 +1510,18 @@ static void genesis_stop(struct skge_port *skge)
1336 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST); 1510 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1337 1511
1338 /* For external PHYs there must be special handling */ 1512 /* For external PHYs there must be special handling */
1339 reg = skge_read32(hw, B2_GP_IO); 1513 if (hw->phy_type != SK_PHY_XMAC) {
1340 if (port == 0) { 1514 reg = skge_read32(hw, B2_GP_IO);
1341 reg |= GP_DIR_0; 1515 if (port == 0) {
1342 reg &= ~GP_IO_0; 1516 reg |= GP_DIR_0;
1343 } else { 1517 reg &= ~GP_IO_0;
1344 reg |= GP_DIR_2; 1518 } else {
1345 reg &= ~GP_IO_2; 1519 reg |= GP_DIR_2;
1520 reg &= ~GP_IO_2;
1521 }
1522 skge_write32(hw, B2_GP_IO, reg);
1523 skge_read32(hw, B2_GP_IO);
1346 } 1524 }
1347 skge_write32(hw, B2_GP_IO, reg);
1348 skge_read32(hw, B2_GP_IO);
1349 1525
1350 xm_write16(hw, port, XM_MMU_CMD, 1526 xm_write16(hw, port, XM_MMU_CMD,
1351 xm_read16(hw, port, XM_MMU_CMD) 1527 xm_read16(hw, port, XM_MMU_CMD)
@@ -1407,7 +1583,7 @@ static void genesis_link_up(struct skge_port *skge)
1407 struct skge_hw *hw = skge->hw; 1583 struct skge_hw *hw = skge->hw;
1408 int port = skge->port; 1584 int port = skge->port;
1409 u16 cmd; 1585 u16 cmd;
1410 u32 mode, msk; 1586 u32 mode;
1411 1587
1412 cmd = xm_read16(hw, port, XM_MMU_CMD); 1588 cmd = xm_read16(hw, port, XM_MMU_CMD);
1413 1589
@@ -1455,27 +1631,24 @@ static void genesis_link_up(struct skge_port *skge)
1455 } 1631 }
1456 1632
1457 xm_write32(hw, port, XM_MODE, mode); 1633 xm_write32(hw, port, XM_MODE, mode);
1458 1634 xm_write16(hw, port, XM_IMSK, XM_DEF_MSK);
1459 msk = XM_DEF_MSK;
1460 /* disable GP0 interrupt bit for external Phy */
1461 msk |= XM_IS_INP_ASS;
1462
1463 xm_write16(hw, port, XM_IMSK, msk);
1464 xm_read16(hw, port, XM_ISRC); 1635 xm_read16(hw, port, XM_ISRC);
1465 1636
1466 /* get MMU Command Reg. */ 1637 /* get MMU Command Reg. */
1467 cmd = xm_read16(hw, port, XM_MMU_CMD); 1638 cmd = xm_read16(hw, port, XM_MMU_CMD);
1468 if (skge->duplex == DUPLEX_FULL) 1639 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1469 cmd |= XM_MMU_GMII_FD; 1640 cmd |= XM_MMU_GMII_FD;
1470 1641
1471 /* 1642 /*
1472 * Workaround BCOM Errata (#10523) for all BCom Phys 1643 * Workaround BCOM Errata (#10523) for all BCom Phys
1473 * Enable Power Management after link up 1644 * Enable Power Management after link up
1474 */ 1645 */
1475 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, 1646 if (hw->phy_type == SK_PHY_BCOM) {
1476 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) 1647 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1477 & ~PHY_B_AC_DIS_PM); 1648 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1478 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); 1649 & ~PHY_B_AC_DIS_PM);
1650 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1651 }
1479 1652
1480 /* enable Rx/Tx */ 1653 /* enable Rx/Tx */
1481 xm_write16(hw, port, XM_MMU_CMD, 1654 xm_write16(hw, port, XM_MMU_CMD,
@@ -2182,7 +2355,7 @@ static int skge_up(struct net_device *dev)
2182 if (err) 2355 if (err)
2183 goto free_pci_mem; 2356 goto free_pci_mem;
2184 2357
2185 err = skge_rx_fill(skge); 2358 err = skge_rx_fill(dev);
2186 if (err) 2359 if (err)
2187 goto free_rx_ring; 2360 goto free_rx_ring;
2188 2361
@@ -2215,6 +2388,7 @@ static int skge_up(struct net_device *dev)
2215 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); 2388 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2216 skge_led(skge, LED_MODE_ON); 2389 skge_led(skge, LED_MODE_ON);
2217 2390
2391 netif_poll_enable(dev);
2218 return 0; 2392 return 0;
2219 2393
2220 free_rx_ring: 2394 free_rx_ring:
@@ -2240,6 +2414,8 @@ static int skge_down(struct net_device *dev)
2240 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); 2414 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2241 2415
2242 netif_stop_queue(dev); 2416 netif_stop_queue(dev);
2417 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2418 cancel_rearming_delayed_work(&skge->link_thread);
2243 2419
2244 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); 2420 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2245 if (hw->chip_id == CHIP_ID_GENESIS) 2421 if (hw->chip_id == CHIP_ID_GENESIS)
@@ -2283,7 +2459,8 @@ static int skge_down(struct net_device *dev)
2283 2459
2284 skge_led(skge, LED_MODE_OFF); 2460 skge_led(skge, LED_MODE_OFF);
2285 2461
2286 skge_tx_clean(skge); 2462 netif_poll_disable(dev);
2463 skge_tx_clean(dev);
2287 skge_rx_clean(skge); 2464 skge_rx_clean(skge);
2288 2465
2289 kfree(skge->rx_ring.start); 2466 kfree(skge->rx_ring.start);
@@ -2308,25 +2485,12 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2308 int i; 2485 int i;
2309 u32 control, len; 2486 u32 control, len;
2310 u64 map; 2487 u64 map;
2311 unsigned long flags;
2312 2488
2313 if (skb_padto(skb, ETH_ZLEN)) 2489 if (skb_padto(skb, ETH_ZLEN))
2314 return NETDEV_TX_OK; 2490 return NETDEV_TX_OK;
2315 2491
2316 if (!spin_trylock_irqsave(&skge->tx_lock, flags)) 2492 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2317 /* Collision - tell upper layer to requeue */
2318 return NETDEV_TX_LOCKED;
2319
2320 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1)) {
2321 if (!netif_queue_stopped(dev)) {
2322 netif_stop_queue(dev);
2323
2324 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2325 dev->name);
2326 }
2327 spin_unlock_irqrestore(&skge->tx_lock, flags);
2328 return NETDEV_TX_BUSY; 2493 return NETDEV_TX_BUSY;
2329 }
2330 2494
2331 e = skge->tx_ring.to_use; 2495 e = skge->tx_ring.to_use;
2332 td = e->desc; 2496 td = e->desc;
@@ -2340,7 +2504,7 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2340 td->dma_lo = map; 2504 td->dma_lo = map;
2341 td->dma_hi = map >> 32; 2505 td->dma_hi = map >> 32;
2342 2506
2343 if (skb->ip_summed == CHECKSUM_HW) { 2507 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2344 int offset = skb->h.raw - skb->data; 2508 int offset = skb->h.raw - skb->data;
2345 2509
2346 /* This seems backwards, but it is what the sk98lin 2510 /* This seems backwards, but it is what the sk98lin
@@ -2401,8 +2565,6 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2401 netif_stop_queue(dev); 2565 netif_stop_queue(dev);
2402 } 2566 }
2403 2567
2404 spin_unlock_irqrestore(&skge->tx_lock, flags);
2405
2406 dev->trans_start = jiffies; 2568 dev->trans_start = jiffies;
2407 2569
2408 return NETDEV_TX_OK; 2570 return NETDEV_TX_OK;
@@ -2432,18 +2594,18 @@ static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2432 printk(KERN_DEBUG PFX "%s: tx done slot %td\n", 2594 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2433 skge->netdev->name, e - skge->tx_ring.start); 2595 skge->netdev->name, e - skge->tx_ring.start);
2434 2596
2435 dev_kfree_skb_any(e->skb); 2597 dev_kfree_skb(e->skb);
2436 } 2598 }
2437 e->skb = NULL; 2599 e->skb = NULL;
2438} 2600}
2439 2601
2440/* Free all buffers in transmit ring */ 2602/* Free all buffers in transmit ring */
2441static void skge_tx_clean(struct skge_port *skge) 2603static void skge_tx_clean(struct net_device *dev)
2442{ 2604{
2605 struct skge_port *skge = netdev_priv(dev);
2443 struct skge_element *e; 2606 struct skge_element *e;
2444 unsigned long flags;
2445 2607
2446 spin_lock_irqsave(&skge->tx_lock, flags); 2608 netif_tx_lock_bh(dev);
2447 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) { 2609 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2448 struct skge_tx_desc *td = e->desc; 2610 struct skge_tx_desc *td = e->desc;
2449 skge_tx_free(skge, e, td->control); 2611 skge_tx_free(skge, e, td->control);
@@ -2451,8 +2613,8 @@ static void skge_tx_clean(struct skge_port *skge)
2451 } 2613 }
2452 2614
2453 skge->tx_ring.to_clean = e; 2615 skge->tx_ring.to_clean = e;
2454 netif_wake_queue(skge->netdev); 2616 netif_wake_queue(dev);
2455 spin_unlock_irqrestore(&skge->tx_lock, flags); 2617 netif_tx_unlock_bh(dev);
2456} 2618}
2457 2619
2458static void skge_tx_timeout(struct net_device *dev) 2620static void skge_tx_timeout(struct net_device *dev)
@@ -2463,7 +2625,7 @@ static void skge_tx_timeout(struct net_device *dev)
2463 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name); 2625 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2464 2626
2465 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP); 2627 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2466 skge_tx_clean(skge); 2628 skge_tx_clean(dev);
2467} 2629}
2468 2630
2469static int skge_change_mtu(struct net_device *dev, int new_mtu) 2631static int skge_change_mtu(struct net_device *dev, int new_mtu)
@@ -2586,16 +2748,17 @@ static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2586/* Get receive buffer from descriptor. 2748/* Get receive buffer from descriptor.
2587 * Handles copy of small buffers and reallocation failures 2749 * Handles copy of small buffers and reallocation failures
2588 */ 2750 */
2589static inline struct sk_buff *skge_rx_get(struct skge_port *skge, 2751static struct sk_buff *skge_rx_get(struct net_device *dev,
2590 struct skge_element *e, 2752 struct skge_element *e,
2591 u32 control, u32 status, u16 csum) 2753 u32 control, u32 status, u16 csum)
2592{ 2754{
2755 struct skge_port *skge = netdev_priv(dev);
2593 struct sk_buff *skb; 2756 struct sk_buff *skb;
2594 u16 len = control & BMU_BBC; 2757 u16 len = control & BMU_BBC;
2595 2758
2596 if (unlikely(netif_msg_rx_status(skge))) 2759 if (unlikely(netif_msg_rx_status(skge)))
2597 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n", 2760 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2598 skge->netdev->name, e - skge->rx_ring.start, 2761 dev->name, e - skge->rx_ring.start,
2599 status, len); 2762 status, len);
2600 2763
2601 if (len > skge->rx_buf_size) 2764 if (len > skge->rx_buf_size)
@@ -2611,7 +2774,7 @@ static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2611 goto error; 2774 goto error;
2612 2775
2613 if (len < RX_COPY_THRESHOLD) { 2776 if (len < RX_COPY_THRESHOLD) {
2614 skb = alloc_skb(len + 2, GFP_ATOMIC); 2777 skb = netdev_alloc_skb(dev, len + 2);
2615 if (!skb) 2778 if (!skb)
2616 goto resubmit; 2779 goto resubmit;
2617 2780
@@ -2626,7 +2789,7 @@ static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2626 skge_rx_reuse(e, skge->rx_buf_size); 2789 skge_rx_reuse(e, skge->rx_buf_size);
2627 } else { 2790 } else {
2628 struct sk_buff *nskb; 2791 struct sk_buff *nskb;
2629 nskb = alloc_skb(skge->rx_buf_size + NET_IP_ALIGN, GFP_ATOMIC); 2792 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
2630 if (!nskb) 2793 if (!nskb)
2631 goto resubmit; 2794 goto resubmit;
2632 2795
@@ -2641,20 +2804,19 @@ static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2641 } 2804 }
2642 2805
2643 skb_put(skb, len); 2806 skb_put(skb, len);
2644 skb->dev = skge->netdev;
2645 if (skge->rx_csum) { 2807 if (skge->rx_csum) {
2646 skb->csum = csum; 2808 skb->csum = csum;
2647 skb->ip_summed = CHECKSUM_HW; 2809 skb->ip_summed = CHECKSUM_COMPLETE;
2648 } 2810 }
2649 2811
2650 skb->protocol = eth_type_trans(skb, skge->netdev); 2812 skb->protocol = eth_type_trans(skb, dev);
2651 2813
2652 return skb; 2814 return skb;
2653error: 2815error:
2654 2816
2655 if (netif_msg_rx_err(skge)) 2817 if (netif_msg_rx_err(skge))
2656 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n", 2818 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2657 skge->netdev->name, e - skge->rx_ring.start, 2819 dev->name, e - skge->rx_ring.start,
2658 control, status); 2820 control, status);
2659 2821
2660 if (skge->hw->chip_id == CHIP_ID_GENESIS) { 2822 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
@@ -2679,15 +2841,15 @@ resubmit:
2679} 2841}
2680 2842
2681/* Free all buffers in Tx ring which are no longer owned by device */ 2843/* Free all buffers in Tx ring which are no longer owned by device */
2682static void skge_txirq(struct net_device *dev) 2844static void skge_tx_done(struct net_device *dev)
2683{ 2845{
2684 struct skge_port *skge = netdev_priv(dev); 2846 struct skge_port *skge = netdev_priv(dev);
2685 struct skge_ring *ring = &skge->tx_ring; 2847 struct skge_ring *ring = &skge->tx_ring;
2686 struct skge_element *e; 2848 struct skge_element *e;
2687 2849
2688 rmb(); 2850 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2689 2851
2690 spin_lock(&skge->tx_lock); 2852 netif_tx_lock(dev);
2691 for (e = ring->to_clean; e != ring->to_use; e = e->next) { 2853 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2692 struct skge_tx_desc *td = e->desc; 2854 struct skge_tx_desc *td = e->desc;
2693 2855
@@ -2698,11 +2860,10 @@ static void skge_txirq(struct net_device *dev)
2698 } 2860 }
2699 skge->tx_ring.to_clean = e; 2861 skge->tx_ring.to_clean = e;
2700 2862
2701 if (netif_queue_stopped(skge->netdev) 2863 if (skge_avail(&skge->tx_ring) > TX_LOW_WATER)
2702 && skge_avail(&skge->tx_ring) > TX_LOW_WATER) 2864 netif_wake_queue(dev);
2703 netif_wake_queue(skge->netdev);
2704 2865
2705 spin_unlock(&skge->tx_lock); 2866 netif_tx_unlock(dev);
2706} 2867}
2707 2868
2708static int skge_poll(struct net_device *dev, int *budget) 2869static int skge_poll(struct net_device *dev, int *budget)
@@ -2714,6 +2875,10 @@ static int skge_poll(struct net_device *dev, int *budget)
2714 int to_do = min(dev->quota, *budget); 2875 int to_do = min(dev->quota, *budget);
2715 int work_done = 0; 2876 int work_done = 0;
2716 2877
2878 skge_tx_done(dev);
2879
2880 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2881
2717 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) { 2882 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
2718 struct skge_rx_desc *rd = e->desc; 2883 struct skge_rx_desc *rd = e->desc;
2719 struct sk_buff *skb; 2884 struct sk_buff *skb;
@@ -2724,7 +2889,7 @@ static int skge_poll(struct net_device *dev, int *budget)
2724 if (control & BMU_OWN) 2889 if (control & BMU_OWN)
2725 break; 2890 break;
2726 2891
2727 skb = skge_rx_get(skge, e, control, rd->status, rd->csum2); 2892 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
2728 if (likely(skb)) { 2893 if (likely(skb)) {
2729 dev->last_rx = jiffies; 2894 dev->last_rx = jiffies;
2730 netif_receive_skb(skb); 2895 netif_receive_skb(skb);
@@ -2744,12 +2909,11 @@ static int skge_poll(struct net_device *dev, int *budget)
2744 if (work_done >= to_do) 2909 if (work_done >= to_do)
2745 return 1; /* not done */ 2910 return 1; /* not done */
2746 2911
2747 netif_rx_complete(dev);
2748
2749 spin_lock_irq(&hw->hw_lock); 2912 spin_lock_irq(&hw->hw_lock);
2750 hw->intr_mask |= rxirqmask[skge->port]; 2913 __netif_rx_complete(dev);
2914 hw->intr_mask |= irqmask[skge->port];
2751 skge_write32(hw, B0_IMSK, hw->intr_mask); 2915 skge_write32(hw, B0_IMSK, hw->intr_mask);
2752 mmiowb(); 2916 skge_read32(hw, B0_IMSK);
2753 spin_unlock_irq(&hw->hw_lock); 2917 spin_unlock_irq(&hw->hw_lock);
2754 2918
2755 return 0; 2919 return 0;
@@ -2874,7 +3038,7 @@ static void skge_extirq(void *arg)
2874 if (netif_running(dev)) { 3038 if (netif_running(dev)) {
2875 if (hw->chip_id != CHIP_ID_GENESIS) 3039 if (hw->chip_id != CHIP_ID_GENESIS)
2876 yukon_phy_intr(skge); 3040 yukon_phy_intr(skge);
2877 else 3041 else if (hw->phy_type == SK_PHY_BCOM)
2878 bcom_phy_intr(skge); 3042 bcom_phy_intr(skge);
2879 } 3043 }
2880 } 3044 }
@@ -2883,6 +3047,7 @@ static void skge_extirq(void *arg)
2883 spin_lock_irq(&hw->hw_lock); 3047 spin_lock_irq(&hw->hw_lock);
2884 hw->intr_mask |= IS_EXT_REG; 3048 hw->intr_mask |= IS_EXT_REG;
2885 skge_write32(hw, B0_IMSK, hw->intr_mask); 3049 skge_write32(hw, B0_IMSK, hw->intr_mask);
3050 skge_read32(hw, B0_IMSK);
2886 spin_unlock_irq(&hw->hw_lock); 3051 spin_unlock_irq(&hw->hw_lock);
2887} 3052}
2888 3053
@@ -2890,27 +3055,23 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2890{ 3055{
2891 struct skge_hw *hw = dev_id; 3056 struct skge_hw *hw = dev_id;
2892 u32 status; 3057 u32 status;
3058 int handled = 0;
2893 3059
3060 spin_lock(&hw->hw_lock);
2894 /* Reading this register masks IRQ */ 3061 /* Reading this register masks IRQ */
2895 status = skge_read32(hw, B0_SP_ISRC); 3062 status = skge_read32(hw, B0_SP_ISRC);
2896 if (status == 0) 3063 if (status == 0 || status == ~0)
2897 return IRQ_NONE; 3064 goto out;
2898 3065
2899 spin_lock(&hw->hw_lock); 3066 handled = 1;
2900 status &= hw->intr_mask; 3067 status &= hw->intr_mask;
2901 if (status & IS_EXT_REG) { 3068 if (status & IS_EXT_REG) {
2902 hw->intr_mask &= ~IS_EXT_REG; 3069 hw->intr_mask &= ~IS_EXT_REG;
2903 schedule_work(&hw->phy_work); 3070 schedule_work(&hw->phy_work);
2904 } 3071 }
2905 3072
2906 if (status & IS_XA1_F) { 3073 if (status & (IS_XA1_F|IS_R1_F)) {
2907 skge_write8(hw, Q_ADDR(Q_XA1, Q_CSR), CSR_IRQ_CL_F); 3074 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
2908 skge_txirq(hw->dev[0]);
2909 }
2910
2911 if (status & IS_R1_F) {
2912 skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
2913 hw->intr_mask &= ~IS_R1_F;
2914 netif_rx_schedule(hw->dev[0]); 3075 netif_rx_schedule(hw->dev[0]);
2915 } 3076 }
2916 3077
@@ -2929,14 +3090,8 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2929 skge_mac_intr(hw, 0); 3090 skge_mac_intr(hw, 0);
2930 3091
2931 if (hw->dev[1]) { 3092 if (hw->dev[1]) {
2932 if (status & IS_XA2_F) { 3093 if (status & (IS_XA2_F|IS_R2_F)) {
2933 skge_write8(hw, Q_ADDR(Q_XA2, Q_CSR), CSR_IRQ_CL_F); 3094 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
2934 skge_txirq(hw->dev[1]);
2935 }
2936
2937 if (status & IS_R2_F) {
2938 skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);
2939 hw->intr_mask &= ~IS_R2_F;
2940 netif_rx_schedule(hw->dev[1]); 3095 netif_rx_schedule(hw->dev[1]);
2941 } 3096 }
2942 3097
@@ -2957,9 +3112,11 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2957 skge_error_irq(hw); 3112 skge_error_irq(hw);
2958 3113
2959 skge_write32(hw, B0_IMSK, hw->intr_mask); 3114 skge_write32(hw, B0_IMSK, hw->intr_mask);
3115 skge_read32(hw, B0_IMSK);
3116out:
2960 spin_unlock(&hw->hw_lock); 3117 spin_unlock(&hw->hw_lock);
2961 3118
2962 return IRQ_HANDLED; 3119 return IRQ_RETVAL(handled);
2963} 3120}
2964 3121
2965#ifdef CONFIG_NET_POLL_CONTROLLER 3122#ifdef CONFIG_NET_POLL_CONTROLLER
@@ -3033,7 +3190,7 @@ static int skge_reset(struct skge_hw *hw)
3033{ 3190{
3034 u32 reg; 3191 u32 reg;
3035 u16 ctst, pci_status; 3192 u16 ctst, pci_status;
3036 u8 t8, mac_cfg, pmd_type, phy_type; 3193 u8 t8, mac_cfg, pmd_type;
3037 int i; 3194 int i;
3038 3195
3039 ctst = skge_read16(hw, B0_CTST); 3196 ctst = skge_read16(hw, B0_CTST);
@@ -3057,19 +3214,22 @@ static int skge_reset(struct skge_hw *hw)
3057 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA)); 3214 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3058 3215
3059 hw->chip_id = skge_read8(hw, B2_CHIP_ID); 3216 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3060 phy_type = skge_read8(hw, B2_E_1) & 0xf; 3217 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3061 pmd_type = skge_read8(hw, B2_PMD_TYP); 3218 pmd_type = skge_read8(hw, B2_PMD_TYP);
3062 hw->copper = (pmd_type == 'T' || pmd_type == '1'); 3219 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3063 3220
3064 switch (hw->chip_id) { 3221 switch (hw->chip_id) {
3065 case CHIP_ID_GENESIS: 3222 case CHIP_ID_GENESIS:
3066 switch (phy_type) { 3223 switch (hw->phy_type) {
3224 case SK_PHY_XMAC:
3225 hw->phy_addr = PHY_ADDR_XMAC;
3226 break;
3067 case SK_PHY_BCOM: 3227 case SK_PHY_BCOM:
3068 hw->phy_addr = PHY_ADDR_BCOM; 3228 hw->phy_addr = PHY_ADDR_BCOM;
3069 break; 3229 break;
3070 default: 3230 default:
3071 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n", 3231 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
3072 pci_name(hw->pdev), phy_type); 3232 pci_name(hw->pdev), hw->phy_type);
3073 return -EOPNOTSUPP; 3233 return -EOPNOTSUPP;
3074 } 3234 }
3075 break; 3235 break;
@@ -3077,7 +3237,7 @@ static int skge_reset(struct skge_hw *hw)
3077 case CHIP_ID_YUKON: 3237 case CHIP_ID_YUKON:
3078 case CHIP_ID_YUKON_LITE: 3238 case CHIP_ID_YUKON_LITE:
3079 case CHIP_ID_YUKON_LP: 3239 case CHIP_ID_YUKON_LP:
3080 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S') 3240 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3081 hw->copper = 1; 3241 hw->copper = 1;
3082 3242
3083 hw->phy_addr = PHY_ADDR_MARV; 3243 hw->phy_addr = PHY_ADDR_MARV;
@@ -3108,11 +3268,13 @@ static int skge_reset(struct skge_hw *hw)
3108 else 3268 else
3109 hw->ram_size = t8 * 4096; 3269 hw->ram_size = t8 * 4096;
3110 3270
3111 spin_lock_init(&hw->hw_lock); 3271 hw->intr_mask = IS_HW_ERR | IS_PORT_1;
3112 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
3113 if (hw->ports > 1) 3272 if (hw->ports > 1)
3114 hw->intr_mask |= IS_PORT_2; 3273 hw->intr_mask |= IS_PORT_2;
3115 3274
3275 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3276 hw->intr_mask |= IS_EXT_REG;
3277
3116 if (hw->chip_id == CHIP_ID_GENESIS) 3278 if (hw->chip_id == CHIP_ID_GENESIS)
3117 genesis_init(hw); 3279 genesis_init(hw);
3118 else { 3280 else {
@@ -3224,7 +3386,7 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3224 dev->poll_controller = skge_netpoll; 3386 dev->poll_controller = skge_netpoll;
3225#endif 3387#endif
3226 dev->irq = hw->pdev->irq; 3388 dev->irq = hw->pdev->irq;
3227 dev->features = NETIF_F_LLTX; 3389
3228 if (highmem) 3390 if (highmem)
3229 dev->features |= NETIF_F_HIGHDMA; 3391 dev->features |= NETIF_F_HIGHDMA;
3230 3392
@@ -3246,7 +3408,8 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3246 3408
3247 skge->port = port; 3409 skge->port = port;
3248 3410
3249 spin_lock_init(&skge->tx_lock); 3411 /* Only used for Genesis XMAC */
3412 INIT_WORK(&skge->link_thread, xm_link_timer, dev);
3250 3413
3251 if (hw->chip_id != CHIP_ID_GENESIS) { 3414 if (hw->chip_id != CHIP_ID_GENESIS) {
3252 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; 3415 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
@@ -3334,6 +3497,7 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3334 hw->pdev = pdev; 3497 hw->pdev = pdev;
3335 mutex_init(&hw->phy_mutex); 3498 mutex_init(&hw->phy_mutex);
3336 INIT_WORK(&hw->phy_work, skge_extirq, hw); 3499 INIT_WORK(&hw->phy_work, skge_extirq, hw);
3500 spin_lock_init(&hw->hw_lock);
3337 3501
3338 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); 3502 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3339 if (!hw->regs) { 3503 if (!hw->regs) {
@@ -3342,23 +3506,16 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3342 goto err_out_free_hw; 3506 goto err_out_free_hw;
3343 } 3507 }
3344 3508
3345 err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw);
3346 if (err) {
3347 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3348 pci_name(pdev), pdev->irq);
3349 goto err_out_iounmap;
3350 }
3351 pci_set_drvdata(pdev, hw);
3352
3353 err = skge_reset(hw); 3509 err = skge_reset(hw);
3354 if (err) 3510 if (err)
3355 goto err_out_free_irq; 3511 goto err_out_iounmap;
3356 3512
3357 printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n", 3513 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3358 pci_resource_start(pdev, 0), pdev->irq, 3514 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3359 skge_board_name(hw), hw->chip_rev); 3515 skge_board_name(hw), hw->chip_rev);
3360 3516
3361 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL) 3517 dev = skge_devinit(hw, 0, using_dac);
3518 if (!dev)
3362 goto err_out_led_off; 3519 goto err_out_led_off;
3363 3520
3364 if (!is_valid_ether_addr(dev->dev_addr)) { 3521 if (!is_valid_ether_addr(dev->dev_addr)) {
@@ -3368,7 +3525,6 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3368 goto err_out_free_netdev; 3525 goto err_out_free_netdev;
3369 } 3526 }
3370 3527
3371
3372 err = register_netdev(dev); 3528 err = register_netdev(dev);
3373 if (err) { 3529 if (err) {
3374 printk(KERN_ERR PFX "%s: cannot register net device\n", 3530 printk(KERN_ERR PFX "%s: cannot register net device\n",
@@ -3376,6 +3532,12 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3376 goto err_out_free_netdev; 3532 goto err_out_free_netdev;
3377 } 3533 }
3378 3534
3535 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3536 if (err) {
3537 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3538 dev->name, pdev->irq);
3539 goto err_out_unregister;
3540 }
3379 skge_show_addr(dev); 3541 skge_show_addr(dev);
3380 3542
3381 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) { 3543 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
@@ -3388,15 +3550,16 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3388 free_netdev(dev1); 3550 free_netdev(dev1);
3389 } 3551 }
3390 } 3552 }
3553 pci_set_drvdata(pdev, hw);
3391 3554
3392 return 0; 3555 return 0;
3393 3556
3557err_out_unregister:
3558 unregister_netdev(dev);
3394err_out_free_netdev: 3559err_out_free_netdev:
3395 free_netdev(dev); 3560 free_netdev(dev);
3396err_out_led_off: 3561err_out_led_off:
3397 skge_write16(hw, B0_LED, LED_STAT_OFF); 3562 skge_write16(hw, B0_LED, LED_STAT_OFF);
3398err_out_free_irq:
3399 free_irq(pdev->irq, hw);
3400err_out_iounmap: 3563err_out_iounmap:
3401 iounmap(hw->regs); 3564 iounmap(hw->regs);
3402err_out_free_hw: 3565err_out_free_hw:
@@ -3426,6 +3589,7 @@ static void __devexit skge_remove(struct pci_dev *pdev)
3426 spin_lock_irq(&hw->hw_lock); 3589 spin_lock_irq(&hw->hw_lock);
3427 hw->intr_mask = 0; 3590 hw->intr_mask = 0;
3428 skge_write32(hw, B0_IMSK, 0); 3591 skge_write32(hw, B0_IMSK, 0);
3592 skge_read32(hw, B0_IMSK);
3429 spin_unlock_irq(&hw->hw_lock); 3593 spin_unlock_irq(&hw->hw_lock);
3430 3594
3431 skge_write16(hw, B0_LED, LED_STAT_OFF); 3595 skge_write16(hw, B0_LED, LED_STAT_OFF);
@@ -3451,26 +3615,25 @@ static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3451 struct skge_hw *hw = pci_get_drvdata(pdev); 3615 struct skge_hw *hw = pci_get_drvdata(pdev);
3452 int i, wol = 0; 3616 int i, wol = 0;
3453 3617
3454 for (i = 0; i < 2; i++) { 3618 pci_save_state(pdev);
3619 for (i = 0; i < hw->ports; i++) {
3455 struct net_device *dev = hw->dev[i]; 3620 struct net_device *dev = hw->dev[i];
3456 3621
3457 if (dev) { 3622 if (netif_running(dev)) {
3458 struct skge_port *skge = netdev_priv(dev); 3623 struct skge_port *skge = netdev_priv(dev);
3459 if (netif_running(dev)) { 3624
3460 netif_carrier_off(dev); 3625 netif_carrier_off(dev);
3461 if (skge->wol) 3626 if (skge->wol)
3462 netif_stop_queue(dev); 3627 netif_stop_queue(dev);
3463 else 3628 else
3464 skge_down(dev); 3629 skge_down(dev);
3465 }
3466 netif_device_detach(dev);
3467 wol |= skge->wol; 3630 wol |= skge->wol;
3468 } 3631 }
3632 netif_device_detach(dev);
3469 } 3633 }
3470 3634
3471 pci_save_state(pdev); 3635 skge_write32(hw, B0_IMSK, 0);
3472 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol); 3636 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3473 pci_disable_device(pdev);
3474 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 3637 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3475 3638
3476 return 0; 3639 return 0;
@@ -3479,23 +3642,33 @@ static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3479static int skge_resume(struct pci_dev *pdev) 3642static int skge_resume(struct pci_dev *pdev)
3480{ 3643{
3481 struct skge_hw *hw = pci_get_drvdata(pdev); 3644 struct skge_hw *hw = pci_get_drvdata(pdev);
3482 int i; 3645 int i, err;
3483 3646
3484 pci_set_power_state(pdev, PCI_D0); 3647 pci_set_power_state(pdev, PCI_D0);
3485 pci_restore_state(pdev); 3648 pci_restore_state(pdev);
3486 pci_enable_wake(pdev, PCI_D0, 0); 3649 pci_enable_wake(pdev, PCI_D0, 0);
3487 3650
3488 skge_reset(hw); 3651 err = skge_reset(hw);
3652 if (err)
3653 goto out;
3489 3654
3490 for (i = 0; i < 2; i++) { 3655 for (i = 0; i < hw->ports; i++) {
3491 struct net_device *dev = hw->dev[i]; 3656 struct net_device *dev = hw->dev[i];
3492 if (dev) { 3657
3493 netif_device_attach(dev); 3658 netif_device_attach(dev);
3494 if (netif_running(dev) && skge_up(dev)) 3659 if (netif_running(dev)) {
3660 err = skge_up(dev);
3661
3662 if (err) {
3663 printk(KERN_ERR PFX "%s: could not up: %d\n",
3664 dev->name, err);
3495 dev_close(dev); 3665 dev_close(dev);
3666 goto out;
3667 }
3496 } 3668 }
3497 } 3669 }
3498 return 0; 3670out:
3671 return err;
3499} 3672}
3500#endif 3673#endif
3501 3674
@@ -3512,7 +3685,7 @@ static struct pci_driver skge_driver = {
3512 3685
3513static int __init skge_init_module(void) 3686static int __init skge_init_module(void)
3514{ 3687{
3515 return pci_module_init(&skge_driver); 3688 return pci_register_driver(&skge_driver);
3516} 3689}
3517 3690
3518static void __exit skge_cleanup_module(void) 3691static void __exit skge_cleanup_module(void)