diff options
Diffstat (limited to 'drivers/net/skge.c')
-rw-r--r-- | drivers/net/skge.c | 28 |
1 files changed, 20 insertions, 8 deletions
diff --git a/drivers/net/skge.c b/drivers/net/skge.c index a1cfead5827b..ea68d4d3d57c 100644 --- a/drivers/net/skge.c +++ b/drivers/net/skge.c | |||
@@ -1804,6 +1804,25 @@ static void yukon_mac_init(struct skge_hw *hw, int port) | |||
1804 | skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | 1804 | skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); |
1805 | } | 1805 | } |
1806 | 1806 | ||
1807 | /* Go into power down mode */ | ||
1808 | static void yukon_suspend(struct skge_hw *hw, int port) | ||
1809 | { | ||
1810 | u16 ctrl; | ||
1811 | |||
1812 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | ||
1813 | ctrl |= PHY_M_PC_POL_R_DIS; | ||
1814 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | ||
1815 | |||
1816 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | ||
1817 | ctrl |= PHY_CT_RESET; | ||
1818 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | ||
1819 | |||
1820 | /* switch IEEE compatible power down mode on */ | ||
1821 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | ||
1822 | ctrl |= PHY_CT_PDOWN; | ||
1823 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | ||
1824 | } | ||
1825 | |||
1807 | static void yukon_stop(struct skge_port *skge) | 1826 | static void yukon_stop(struct skge_port *skge) |
1808 | { | 1827 | { |
1809 | struct skge_hw *hw = skge->hw; | 1828 | struct skge_hw *hw = skge->hw; |
@@ -1817,14 +1836,7 @@ static void yukon_stop(struct skge_port *skge) | |||
1817 | & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA)); | 1836 | & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA)); |
1818 | gma_read16(hw, port, GM_GP_CTRL); | 1837 | gma_read16(hw, port, GM_GP_CTRL); |
1819 | 1838 | ||
1820 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | 1839 | yukon_suspend(hw, port); |
1821 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { | ||
1822 | u32 io = skge_read32(hw, B2_GP_IO); | ||
1823 | |||
1824 | io |= GP_DIR_9 | GP_IO_9; | ||
1825 | skge_write32(hw, B2_GP_IO, io); | ||
1826 | skge_read32(hw, B2_GP_IO); | ||
1827 | } | ||
1828 | 1840 | ||
1829 | /* set GPHY Control reset */ | 1841 | /* set GPHY Control reset */ |
1830 | skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | 1842 | skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |