aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/skge.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/skge.c')
-rw-r--r--drivers/net/skge.c275
1 files changed, 137 insertions, 138 deletions
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index 25e028b7ce48..4eda81d41b10 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -44,7 +44,7 @@
44#include "skge.h" 44#include "skge.h"
45 45
46#define DRV_NAME "skge" 46#define DRV_NAME "skge"
47#define DRV_VERSION "1.3" 47#define DRV_VERSION "1.4"
48#define PFX DRV_NAME " " 48#define PFX DRV_NAME " "
49 49
50#define DEFAULT_TX_RING_SIZE 128 50#define DEFAULT_TX_RING_SIZE 128
@@ -104,7 +104,6 @@ static const int txqaddr[] = { Q_XA1, Q_XA2 };
104static const int rxqaddr[] = { Q_R1, Q_R2 }; 104static const int rxqaddr[] = { Q_R1, Q_R2 };
105static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F }; 105static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
106static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F }; 106static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
107static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
108 107
109static int skge_get_regs_len(struct net_device *dev) 108static int skge_get_regs_len(struct net_device *dev)
110{ 109{
@@ -728,19 +727,18 @@ static struct ethtool_ops skge_ethtool_ops = {
728 * Allocate ring elements and chain them together 727 * Allocate ring elements and chain them together
729 * One-to-one association of board descriptors with ring elements 728 * One-to-one association of board descriptors with ring elements
730 */ 729 */
731static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base) 730static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
732{ 731{
733 struct skge_tx_desc *d; 732 struct skge_tx_desc *d;
734 struct skge_element *e; 733 struct skge_element *e;
735 int i; 734 int i;
736 735
737 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL); 736 ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL);
738 if (!ring->start) 737 if (!ring->start)
739 return -ENOMEM; 738 return -ENOMEM;
740 739
741 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) { 740 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
742 e->desc = d; 741 e->desc = d;
743 e->skb = NULL;
744 if (i == ring->count - 1) { 742 if (i == ring->count - 1) {
745 e->next = ring->start; 743 e->next = ring->start;
746 d->next_offset = base; 744 d->next_offset = base;
@@ -2169,27 +2167,31 @@ static int skge_up(struct net_device *dev)
2169 if (!skge->mem) 2167 if (!skge->mem)
2170 return -ENOMEM; 2168 return -ENOMEM;
2171 2169
2170 BUG_ON(skge->dma & 7);
2171
2172 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2173 printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");
2174 err = -EINVAL;
2175 goto free_pci_mem;
2176 }
2177
2172 memset(skge->mem, 0, skge->mem_size); 2178 memset(skge->mem, 0, skge->mem_size);
2173 2179
2174 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma))) 2180 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2181 if (err)
2175 goto free_pci_mem; 2182 goto free_pci_mem;
2176 2183
2177 err = skge_rx_fill(skge); 2184 err = skge_rx_fill(skge);
2178 if (err) 2185 if (err)
2179 goto free_rx_ring; 2186 goto free_rx_ring;
2180 2187
2181 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size, 2188 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2182 skge->dma + rx_size))) 2189 skge->dma + rx_size);
2190 if (err)
2183 goto free_rx_ring; 2191 goto free_rx_ring;
2184 2192
2185 skge->tx_avail = skge->tx_ring.count - 1; 2193 skge->tx_avail = skge->tx_ring.count - 1;
2186 2194
2187 /* Enable IRQ from port */
2188 spin_lock_irq(&hw->hw_lock);
2189 hw->intr_mask |= portirqmask[port];
2190 skge_write32(hw, B0_IMSK, hw->intr_mask);
2191 spin_unlock_irq(&hw->hw_lock);
2192
2193 /* Initialize MAC */ 2195 /* Initialize MAC */
2194 spin_lock_bh(&hw->phy_lock); 2196 spin_lock_bh(&hw->phy_lock);
2195 if (hw->chip_id == CHIP_ID_GENESIS) 2197 if (hw->chip_id == CHIP_ID_GENESIS)
@@ -2246,11 +2248,6 @@ static int skge_down(struct net_device *dev)
2246 else 2248 else
2247 yukon_stop(skge); 2249 yukon_stop(skge);
2248 2250
2249 spin_lock_irq(&hw->hw_lock);
2250 hw->intr_mask &= ~portirqmask[skge->port];
2251 skge_write32(hw, B0_IMSK, hw->intr_mask);
2252 spin_unlock_irq(&hw->hw_lock);
2253
2254 /* Stop transmitter */ 2251 /* Stop transmitter */
2255 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); 2252 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2256 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), 2253 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
@@ -2307,18 +2304,15 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2307 int i; 2304 int i;
2308 u32 control, len; 2305 u32 control, len;
2309 u64 map; 2306 u64 map;
2310 unsigned long flags;
2311 2307
2312 skb = skb_padto(skb, ETH_ZLEN); 2308 skb = skb_padto(skb, ETH_ZLEN);
2313 if (!skb) 2309 if (!skb)
2314 return NETDEV_TX_OK; 2310 return NETDEV_TX_OK;
2315 2311
2316 local_irq_save(flags);
2317 if (!spin_trylock(&skge->tx_lock)) { 2312 if (!spin_trylock(&skge->tx_lock)) {
2318 /* Collision - tell upper layer to requeue */ 2313 /* Collision - tell upper layer to requeue */
2319 local_irq_restore(flags); 2314 return NETDEV_TX_LOCKED;
2320 return NETDEV_TX_LOCKED; 2315 }
2321 }
2322 2316
2323 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) { 2317 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2324 if (!netif_queue_stopped(dev)) { 2318 if (!netif_queue_stopped(dev)) {
@@ -2327,7 +2321,7 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2327 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n", 2321 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2328 dev->name); 2322 dev->name);
2329 } 2323 }
2330 spin_unlock_irqrestore(&skge->tx_lock, flags); 2324 spin_unlock(&skge->tx_lock);
2331 return NETDEV_TX_BUSY; 2325 return NETDEV_TX_BUSY;
2332 } 2326 }
2333 2327
@@ -2402,8 +2396,10 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2402 netif_stop_queue(dev); 2396 netif_stop_queue(dev);
2403 } 2397 }
2404 2398
2399 mmiowb();
2400 spin_unlock(&skge->tx_lock);
2401
2405 dev->trans_start = jiffies; 2402 dev->trans_start = jiffies;
2406 spin_unlock_irqrestore(&skge->tx_lock, flags);
2407 2403
2408 return NETDEV_TX_OK; 2404 return NETDEV_TX_OK;
2409} 2405}
@@ -2416,7 +2412,7 @@ static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2416 pci_unmap_addr(e, mapaddr), 2412 pci_unmap_addr(e, mapaddr),
2417 pci_unmap_len(e, maplen), 2413 pci_unmap_len(e, maplen),
2418 PCI_DMA_TODEVICE); 2414 PCI_DMA_TODEVICE);
2419 dev_kfree_skb_any(e->skb); 2415 dev_kfree_skb(e->skb);
2420 e->skb = NULL; 2416 e->skb = NULL;
2421 } else { 2417 } else {
2422 pci_unmap_page(hw->pdev, 2418 pci_unmap_page(hw->pdev,
@@ -2430,15 +2426,14 @@ static void skge_tx_clean(struct skge_port *skge)
2430{ 2426{
2431 struct skge_ring *ring = &skge->tx_ring; 2427 struct skge_ring *ring = &skge->tx_ring;
2432 struct skge_element *e; 2428 struct skge_element *e;
2433 unsigned long flags;
2434 2429
2435 spin_lock_irqsave(&skge->tx_lock, flags); 2430 spin_lock_bh(&skge->tx_lock);
2436 for (e = ring->to_clean; e != ring->to_use; e = e->next) { 2431 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2437 ++skge->tx_avail; 2432 ++skge->tx_avail;
2438 skge_tx_free(skge->hw, e); 2433 skge_tx_free(skge->hw, e);
2439 } 2434 }
2440 ring->to_clean = e; 2435 ring->to_clean = e;
2441 spin_unlock_irqrestore(&skge->tx_lock, flags); 2436 spin_unlock_bh(&skge->tx_lock);
2442} 2437}
2443 2438
2444static void skge_tx_timeout(struct net_device *dev) 2439static void skge_tx_timeout(struct net_device *dev)
@@ -2663,6 +2658,37 @@ resubmit:
2663 return NULL; 2658 return NULL;
2664} 2659}
2665 2660
2661static void skge_tx_done(struct skge_port *skge)
2662{
2663 struct skge_ring *ring = &skge->tx_ring;
2664 struct skge_element *e;
2665
2666 spin_lock(&skge->tx_lock);
2667 for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {
2668 struct skge_tx_desc *td = e->desc;
2669 u32 control;
2670
2671 rmb();
2672 control = td->control;
2673 if (control & BMU_OWN)
2674 break;
2675
2676 if (unlikely(netif_msg_tx_done(skge)))
2677 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2678 skge->netdev->name, e - ring->start, td->status);
2679
2680 skge_tx_free(skge->hw, e);
2681 e->skb = NULL;
2682 ++skge->tx_avail;
2683 }
2684 ring->to_clean = e;
2685 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2686
2687 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2688 netif_wake_queue(skge->netdev);
2689
2690 spin_unlock(&skge->tx_lock);
2691}
2666 2692
2667static int skge_poll(struct net_device *dev, int *budget) 2693static int skge_poll(struct net_device *dev, int *budget)
2668{ 2694{
@@ -2670,8 +2696,10 @@ static int skge_poll(struct net_device *dev, int *budget)
2670 struct skge_hw *hw = skge->hw; 2696 struct skge_hw *hw = skge->hw;
2671 struct skge_ring *ring = &skge->rx_ring; 2697 struct skge_ring *ring = &skge->rx_ring;
2672 struct skge_element *e; 2698 struct skge_element *e;
2673 unsigned int to_do = min(dev->quota, *budget); 2699 int to_do = min(dev->quota, *budget);
2674 unsigned int work_done = 0; 2700 int work_done = 0;
2701
2702 skge_tx_done(skge);
2675 2703
2676 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) { 2704 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
2677 struct skge_rx_desc *rd = e->desc; 2705 struct skge_rx_desc *rd = e->desc;
@@ -2683,8 +2711,8 @@ static int skge_poll(struct net_device *dev, int *budget)
2683 if (control & BMU_OWN) 2711 if (control & BMU_OWN)
2684 break; 2712 break;
2685 2713
2686 skb = skge_rx_get(skge, e, control, rd->status, 2714 skb = skge_rx_get(skge, e, control, rd->status,
2687 le16_to_cpu(rd->csum2)); 2715 le16_to_cpu(rd->csum2));
2688 if (likely(skb)) { 2716 if (likely(skb)) {
2689 dev->last_rx = jiffies; 2717 dev->last_rx = jiffies;
2690 netif_receive_skb(skb); 2718 netif_receive_skb(skb);
@@ -2705,49 +2733,15 @@ static int skge_poll(struct net_device *dev, int *budget)
2705 if (work_done >= to_do) 2733 if (work_done >= to_do)
2706 return 1; /* not done */ 2734 return 1; /* not done */
2707 2735
2708 spin_lock_irq(&hw->hw_lock); 2736 netif_rx_complete(dev);
2709 __netif_rx_complete(dev); 2737 mmiowb();
2710 hw->intr_mask |= portirqmask[skge->port]; 2738
2739 hw->intr_mask |= skge->port == 0 ? (IS_R1_F|IS_XA1_F) : (IS_R2_F|IS_XA2_F);
2711 skge_write32(hw, B0_IMSK, hw->intr_mask); 2740 skge_write32(hw, B0_IMSK, hw->intr_mask);
2712 spin_unlock_irq(&hw->hw_lock);
2713 2741
2714 return 0; 2742 return 0;
2715} 2743}
2716 2744
2717static inline void skge_tx_intr(struct net_device *dev)
2718{
2719 struct skge_port *skge = netdev_priv(dev);
2720 struct skge_hw *hw = skge->hw;
2721 struct skge_ring *ring = &skge->tx_ring;
2722 struct skge_element *e;
2723
2724 spin_lock(&skge->tx_lock);
2725 for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {
2726 struct skge_tx_desc *td = e->desc;
2727 u32 control;
2728
2729 rmb();
2730 control = td->control;
2731 if (control & BMU_OWN)
2732 break;
2733
2734 if (unlikely(netif_msg_tx_done(skge)))
2735 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2736 dev->name, e - ring->start, td->status);
2737
2738 skge_tx_free(hw, e);
2739 e->skb = NULL;
2740 ++skge->tx_avail;
2741 }
2742 ring->to_clean = e;
2743 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2744
2745 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2746 netif_wake_queue(dev);
2747
2748 spin_unlock(&skge->tx_lock);
2749}
2750
2751/* Parity errors seem to happen when Genesis is connected to a switch 2745/* Parity errors seem to happen when Genesis is connected to a switch
2752 * with no other ports present. Heartbeat error?? 2746 * with no other ports present. Heartbeat error??
2753 */ 2747 */
@@ -2770,17 +2764,6 @@ static void skge_mac_parity(struct skge_hw *hw, int port)
2770 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE); 2764 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2771} 2765}
2772 2766
2773static void skge_pci_clear(struct skge_hw *hw)
2774{
2775 u16 status;
2776
2777 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2778 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2779 pci_write_config_word(hw->pdev, PCI_STATUS,
2780 status | PCI_STATUS_ERROR_BITS);
2781 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2782}
2783
2784static void skge_mac_intr(struct skge_hw *hw, int port) 2767static void skge_mac_intr(struct skge_hw *hw, int port)
2785{ 2768{
2786 if (hw->chip_id == CHIP_ID_GENESIS) 2769 if (hw->chip_id == CHIP_ID_GENESIS)
@@ -2822,23 +2805,39 @@ static void skge_error_irq(struct skge_hw *hw)
2822 if (hwstatus & IS_M2_PAR_ERR) 2805 if (hwstatus & IS_M2_PAR_ERR)
2823 skge_mac_parity(hw, 1); 2806 skge_mac_parity(hw, 1);
2824 2807
2825 if (hwstatus & IS_R1_PAR_ERR) 2808 if (hwstatus & IS_R1_PAR_ERR) {
2809 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2810 hw->dev[0]->name);
2826 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P); 2811 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2812 }
2827 2813
2828 if (hwstatus & IS_R2_PAR_ERR) 2814 if (hwstatus & IS_R2_PAR_ERR) {
2815 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2816 hw->dev[1]->name);
2829 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P); 2817 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2818 }
2830 2819
2831 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) { 2820 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2832 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n", 2821 u16 pci_status, pci_cmd;
2833 hwstatus); 2822
2823 pci_read_config_word(hw->pdev, PCI_COMMAND, &pci_cmd);
2824 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
2834 2825
2835 skge_pci_clear(hw); 2826 printk(KERN_ERR PFX "%s: PCI error cmd=%#x status=%#x\n",
2827 pci_name(hw->pdev), pci_cmd, pci_status);
2828
2829 /* Write the error bits back to clear them. */
2830 pci_status &= PCI_STATUS_ERROR_BITS;
2831 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2832 pci_write_config_word(hw->pdev, PCI_COMMAND,
2833 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2834 pci_write_config_word(hw->pdev, PCI_STATUS, pci_status);
2835 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2836 2836
2837 /* if error still set then just ignore it */ 2837 /* if error still set then just ignore it */
2838 hwstatus = skge_read32(hw, B0_HWE_ISRC); 2838 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2839 if (hwstatus & IS_IRQ_STAT) { 2839 if (hwstatus & IS_IRQ_STAT) {
2840 pr_debug("IRQ status %x: still set ignoring hardware errors\n", 2840 printk(KERN_INFO PFX "unable to clear error (so ignoring them)\n");
2841 hwstatus);
2842 hw->intr_mask &= ~IS_HW_ERR; 2841 hw->intr_mask &= ~IS_HW_ERR;
2843 } 2842 }
2844 } 2843 }
@@ -2855,12 +2854,11 @@ static void skge_extirq(unsigned long data)
2855 int port; 2854 int port;
2856 2855
2857 spin_lock(&hw->phy_lock); 2856 spin_lock(&hw->phy_lock);
2858 for (port = 0; port < 2; port++) { 2857 for (port = 0; port < hw->ports; port++) {
2859 struct net_device *dev = hw->dev[port]; 2858 struct net_device *dev = hw->dev[port];
2859 struct skge_port *skge = netdev_priv(dev);
2860 2860
2861 if (dev && netif_running(dev)) { 2861 if (netif_running(dev)) {
2862 struct skge_port *skge = netdev_priv(dev);
2863
2864 if (hw->chip_id != CHIP_ID_GENESIS) 2862 if (hw->chip_id != CHIP_ID_GENESIS)
2865 yukon_phy_intr(skge); 2863 yukon_phy_intr(skge);
2866 else 2864 else
@@ -2869,38 +2867,39 @@ static void skge_extirq(unsigned long data)
2869 } 2867 }
2870 spin_unlock(&hw->phy_lock); 2868 spin_unlock(&hw->phy_lock);
2871 2869
2872 spin_lock_irq(&hw->hw_lock);
2873 hw->intr_mask |= IS_EXT_REG; 2870 hw->intr_mask |= IS_EXT_REG;
2874 skge_write32(hw, B0_IMSK, hw->intr_mask); 2871 skge_write32(hw, B0_IMSK, hw->intr_mask);
2875 spin_unlock_irq(&hw->hw_lock);
2876} 2872}
2877 2873
2878static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs) 2874static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2879{ 2875{
2880 struct skge_hw *hw = dev_id; 2876 struct skge_hw *hw = dev_id;
2881 u32 status = skge_read32(hw, B0_SP_ISRC); 2877 u32 status;
2882 2878
2883 if (status == 0 || status == ~0) /* hotplug or shared irq */ 2879 /* Reading this register masks IRQ */
2880 status = skge_read32(hw, B0_SP_ISRC);
2881 if (status == 0)
2884 return IRQ_NONE; 2882 return IRQ_NONE;
2885 2883
2886 spin_lock(&hw->hw_lock); 2884 if (status & IS_EXT_REG) {
2887 if (status & IS_R1_F) { 2885 hw->intr_mask &= ~IS_EXT_REG;
2886 tasklet_schedule(&hw->ext_tasklet);
2887 }
2888
2889 if (status & (IS_R1_F|IS_XA1_F)) {
2888 skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F); 2890 skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
2889 hw->intr_mask &= ~IS_R1_F; 2891 hw->intr_mask &= ~(IS_R1_F|IS_XA1_F);
2890 netif_rx_schedule(hw->dev[0]); 2892 netif_rx_schedule(hw->dev[0]);
2891 } 2893 }
2892 2894
2893 if (status & IS_R2_F) { 2895 if (status & (IS_R2_F|IS_XA2_F)) {
2894 skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F); 2896 skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);
2895 hw->intr_mask &= ~IS_R2_F; 2897 hw->intr_mask &= ~(IS_R2_F|IS_XA2_F);
2896 netif_rx_schedule(hw->dev[1]); 2898 netif_rx_schedule(hw->dev[1]);
2897 } 2899 }
2898 2900
2899 if (status & IS_XA1_F) 2901 if (likely((status & hw->intr_mask) == 0))
2900 skge_tx_intr(hw->dev[0]); 2902 return IRQ_HANDLED;
2901
2902 if (status & IS_XA2_F)
2903 skge_tx_intr(hw->dev[1]);
2904 2903
2905 if (status & IS_PA_TO_RX1) { 2904 if (status & IS_PA_TO_RX1) {
2906 struct skge_port *skge = netdev_priv(hw->dev[0]); 2905 struct skge_port *skge = netdev_priv(hw->dev[0]);
@@ -2929,13 +2928,7 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2929 if (status & IS_HW_ERR) 2928 if (status & IS_HW_ERR)
2930 skge_error_irq(hw); 2929 skge_error_irq(hw);
2931 2930
2932 if (status & IS_EXT_REG) {
2933 hw->intr_mask &= ~IS_EXT_REG;
2934 tasklet_schedule(&hw->ext_tasklet);
2935 }
2936
2937 skge_write32(hw, B0_IMSK, hw->intr_mask); 2931 skge_write32(hw, B0_IMSK, hw->intr_mask);
2938 spin_unlock(&hw->hw_lock);
2939 2932
2940 return IRQ_HANDLED; 2933 return IRQ_HANDLED;
2941} 2934}
@@ -3010,7 +3003,7 @@ static const char *skge_board_name(const struct skge_hw *hw)
3010static int skge_reset(struct skge_hw *hw) 3003static int skge_reset(struct skge_hw *hw)
3011{ 3004{
3012 u32 reg; 3005 u32 reg;
3013 u16 ctst; 3006 u16 ctst, pci_status;
3014 u8 t8, mac_cfg, pmd_type, phy_type; 3007 u8 t8, mac_cfg, pmd_type, phy_type;
3015 int i; 3008 int i;
3016 3009
@@ -3021,8 +3014,13 @@ static int skge_reset(struct skge_hw *hw)
3021 skge_write8(hw, B0_CTST, CS_RST_CLR); 3014 skge_write8(hw, B0_CTST, CS_RST_CLR);
3022 3015
3023 /* clear PCI errors, if any */ 3016 /* clear PCI errors, if any */
3024 skge_pci_clear(hw); 3017 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3018 skge_write8(hw, B2_TST_CTRL2, 0);
3025 3019
3020 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3021 pci_write_config_word(hw->pdev, PCI_STATUS,
3022 pci_status | PCI_STATUS_ERROR_BITS);
3023 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3026 skge_write8(hw, B0_CTST, CS_MRST_CLR); 3024 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3027 3025
3028 /* restore CLK_RUN bits (for Yukon-Lite) */ 3026 /* restore CLK_RUN bits (for Yukon-Lite) */
@@ -3081,7 +3079,10 @@ static int skge_reset(struct skge_hw *hw)
3081 else 3079 else
3082 hw->ram_size = t8 * 4096; 3080 hw->ram_size = t8 * 4096;
3083 3081
3084 hw->intr_mask = IS_HW_ERR | IS_EXT_REG; 3082 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
3083 if (hw->ports > 1)
3084 hw->intr_mask |= IS_PORT_2;
3085
3085 if (hw->chip_id == CHIP_ID_GENESIS) 3086 if (hw->chip_id == CHIP_ID_GENESIS)
3086 genesis_init(hw); 3087 genesis_init(hw);
3087 else { 3088 else {
@@ -3251,13 +3252,15 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3251 struct skge_hw *hw; 3252 struct skge_hw *hw;
3252 int err, using_dac = 0; 3253 int err, using_dac = 0;
3253 3254
3254 if ((err = pci_enable_device(pdev))) { 3255 err = pci_enable_device(pdev);
3256 if (err) {
3255 printk(KERN_ERR PFX "%s cannot enable PCI device\n", 3257 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3256 pci_name(pdev)); 3258 pci_name(pdev));
3257 goto err_out; 3259 goto err_out;
3258 } 3260 }
3259 3261
3260 if ((err = pci_request_regions(pdev, DRV_NAME))) { 3262 err = pci_request_regions(pdev, DRV_NAME);
3263 if (err) {
3261 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n", 3264 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3262 pci_name(pdev)); 3265 pci_name(pdev));
3263 goto err_out_disable_pdev; 3266 goto err_out_disable_pdev;
@@ -3265,22 +3268,18 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3265 3268
3266 pci_set_master(pdev); 3269 pci_set_master(pdev);
3267 3270
3268 if (sizeof(dma_addr_t) > sizeof(u32) && 3271 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3269 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3270 using_dac = 1; 3272 using_dac = 1;
3271 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 3273 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3272 if (err < 0) { 3274 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3273 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA " 3275 using_dac = 0;
3274 "for consistent allocations\n", pci_name(pdev)); 3276 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3275 goto err_out_free_regions; 3277 }
3276 } 3278
3277 } else { 3279 if (err) {
3278 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 3280 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3279 if (err) { 3281 pci_name(pdev));
3280 printk(KERN_ERR PFX "%s no usable DMA configuration\n", 3282 goto err_out_free_regions;
3281 pci_name(pdev));
3282 goto err_out_free_regions;
3283 }
3284 } 3283 }
3285 3284
3286#ifdef __BIG_ENDIAN 3285#ifdef __BIG_ENDIAN
@@ -3304,7 +3303,6 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3304 3303
3305 hw->pdev = pdev; 3304 hw->pdev = pdev;
3306 spin_lock_init(&hw->phy_lock); 3305 spin_lock_init(&hw->phy_lock);
3307 spin_lock_init(&hw->hw_lock);
3308 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw); 3306 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3309 3307
3310 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); 3308 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
@@ -3314,7 +3312,8 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3314 goto err_out_free_hw; 3312 goto err_out_free_hw;
3315 } 3313 }
3316 3314
3317 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) { 3315 err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw);
3316 if (err) {
3318 printk(KERN_ERR PFX "%s: cannot assign irq %d\n", 3317 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3319 pci_name(pdev), pdev->irq); 3318 pci_name(pdev), pdev->irq);
3320 goto err_out_iounmap; 3319 goto err_out_iounmap;
@@ -3332,7 +3331,8 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3332 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL) 3331 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3333 goto err_out_led_off; 3332 goto err_out_led_off;
3334 3333
3335 if ((err = register_netdev(dev))) { 3334 err = register_netdev(dev);
3335 if (err) {
3336 printk(KERN_ERR PFX "%s: cannot register net device\n", 3336 printk(KERN_ERR PFX "%s: cannot register net device\n",
3337 pci_name(pdev)); 3337 pci_name(pdev));
3338 goto err_out_free_netdev; 3338 goto err_out_free_netdev;
@@ -3387,7 +3387,6 @@ static void __devexit skge_remove(struct pci_dev *pdev)
3387 3387
3388 skge_write32(hw, B0_IMSK, 0); 3388 skge_write32(hw, B0_IMSK, 0);
3389 skge_write16(hw, B0_LED, LED_STAT_OFF); 3389 skge_write16(hw, B0_LED, LED_STAT_OFF);
3390 skge_pci_clear(hw);
3391 skge_write8(hw, B0_CTST, CS_RST_SET); 3390 skge_write8(hw, B0_CTST, CS_RST_SET);
3392 3391
3393 tasklet_kill(&hw->ext_tasklet); 3392 tasklet_kill(&hw->ext_tasklet);