aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/sis900.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/sis900.h')
-rw-r--r--drivers/net/sis900.h18
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/net/sis900.h b/drivers/net/sis900.h
index 4834e3a15694..150511a922ef 100644
--- a/drivers/net/sis900.h
+++ b/drivers/net/sis900.h
@@ -1,4 +1,4 @@
1/* sis900.h Definitions for SiS ethernet controllers including 7014/7016 and 900 1/* sis900.h Definitions for SiS ethernet controllers including 7014/7016 and 900
2 * Copyright 1999 Silicon Integrated System Corporation 2 * Copyright 1999 Silicon Integrated System Corporation
3 * References: 3 * References:
4 * SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support, 4 * SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support,
@@ -49,7 +49,7 @@ enum sis900_command_register_bits {
49 49
50enum sis900_configuration_register_bits { 50enum sis900_configuration_register_bits {
51 DESCRFMT = 0x00000100 /* 7016 specific */, REQALG = 0x00000080, 51 DESCRFMT = 0x00000100 /* 7016 specific */, REQALG = 0x00000080,
52 SB = 0x00000040, POW = 0x00000020, EXD = 0x00000010, 52 SB = 0x00000040, POW = 0x00000020, EXD = 0x00000010,
53 PESEL = 0x00000008, LPM = 0x00000004, BEM = 0x00000001, 53 PESEL = 0x00000008, LPM = 0x00000004, BEM = 0x00000001,
54 /* 635 & 900B Specific */ 54 /* 635 & 900B Specific */
55 RND_CNT = 0x00000400, FAIR_BACKOFF = 0x00000200, 55 RND_CNT = 0x00000400, FAIR_BACKOFF = 0x00000200,
@@ -57,7 +57,7 @@ enum sis900_configuration_register_bits {
57}; 57};
58 58
59enum sis900_eeprom_access_reigster_bits { 59enum sis900_eeprom_access_reigster_bits {
60 MDC = 0x00000040, MDDIR = 0x00000020, MDIO = 0x00000010, /* 7016 specific */ 60 MDC = 0x00000040, MDDIR = 0x00000020, MDIO = 0x00000010, /* 7016 specific */
61 EECS = 0x00000008, EECLK = 0x00000004, EEDO = 0x00000002, 61 EECS = 0x00000008, EECLK = 0x00000004, EEDO = 0x00000002,
62 EEDI = 0x00000001 62 EEDI = 0x00000001
63}; 63};
@@ -129,9 +129,9 @@ enum sis900_eeprom_address {
129 129
130/* The EEPROM commands include the alway-set leading bit. Refer to NM93Cxx datasheet */ 130/* The EEPROM commands include the alway-set leading bit. Refer to NM93Cxx datasheet */
131enum sis900_eeprom_command { 131enum sis900_eeprom_command {
132 EEread = 0x0180, EEwrite = 0x0140, EEerase = 0x01C0, 132 EEread = 0x0180, EEwrite = 0x0140, EEerase = 0x01C0,
133 EEwriteEnable = 0x0130, EEwriteDisable = 0x0100, 133 EEwriteEnable = 0x0130, EEwriteDisable = 0x0100,
134 EEeraseAll = 0x0120, EEwriteAll = 0x0110, 134 EEeraseAll = 0x0120, EEwriteAll = 0x0110,
135 EEaddrMask = 0x013F, EEcmdShift = 16 135 EEaddrMask = 0x013F, EEcmdShift = 16
136}; 136};
137 137
@@ -148,7 +148,7 @@ enum sis900_pci_registers {
148 148
149/* Power management capabilities bits */ 149/* Power management capabilities bits */
150enum sis900_cfgpmc_register_bits { 150enum sis900_cfgpmc_register_bits {
151 PMVER = 0x00070000, 151 PMVER = 0x00070000,
152 DSI = 0x00100000, 152 DSI = 0x00100000,
153 PMESP = 0xf8000000 153 PMESP = 0xf8000000
154}; 154};
@@ -238,7 +238,7 @@ enum amd_mii_registers {
238 238
239/* MII Control register bit definitions. */ 239/* MII Control register bit definitions. */
240enum mii_control_register_bits { 240enum mii_control_register_bits {
241 MII_CNTL_FDX = 0x0100, MII_CNTL_RST_AUTO = 0x0200, 241 MII_CNTL_FDX = 0x0100, MII_CNTL_RST_AUTO = 0x0200,
242 MII_CNTL_ISOLATE = 0x0400, MII_CNTL_PWRDWN = 0x0800, 242 MII_CNTL_ISOLATE = 0x0400, MII_CNTL_PWRDWN = 0x0800,
243 MII_CNTL_AUTO = 0x1000, MII_CNTL_SPEED = 0x2000, 243 MII_CNTL_AUTO = 0x1000, MII_CNTL_SPEED = 0x2000,
244 MII_CNTL_LPBK = 0x4000, MII_CNTL_RESET = 0x8000 244 MII_CNTL_LPBK = 0x4000, MII_CNTL_RESET = 0x8000
@@ -246,8 +246,8 @@ enum mii_control_register_bits {
246 246
247/* MII Status register bit */ 247/* MII Status register bit */
248enum mii_status_register_bits { 248enum mii_status_register_bits {
249 MII_STAT_EXT = 0x0001, MII_STAT_JAB = 0x0002, 249 MII_STAT_EXT = 0x0001, MII_STAT_JAB = 0x0002,
250 MII_STAT_LINK = 0x0004, MII_STAT_CAN_AUTO = 0x0008, 250 MII_STAT_LINK = 0x0004, MII_STAT_CAN_AUTO = 0x0008,
251 MII_STAT_FAULT = 0x0010, MII_STAT_AUTO_DONE = 0x0020, 251 MII_STAT_FAULT = 0x0010, MII_STAT_AUTO_DONE = 0x0020,
252 MII_STAT_CAN_T = 0x0800, MII_STAT_CAN_T_FDX = 0x1000, 252 MII_STAT_CAN_T = 0x0800, MII_STAT_CAN_T_FDX = 0x1000,
253 MII_STAT_CAN_TX = 0x2000, MII_STAT_CAN_TX_FDX = 0x4000, 253 MII_STAT_CAN_TX = 0x2000, MII_STAT_CAN_TX_FDX = 0x4000,