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path: root/drivers/net/sfc/tenxpress.c
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Diffstat (limited to 'drivers/net/sfc/tenxpress.c')
-rw-r--r--drivers/net/sfc/tenxpress.c91
1 files changed, 87 insertions, 4 deletions
diff --git a/drivers/net/sfc/tenxpress.c b/drivers/net/sfc/tenxpress.c
index a2e9f79e47b1..b1cd6deec01f 100644
--- a/drivers/net/sfc/tenxpress.c
+++ b/drivers/net/sfc/tenxpress.c
@@ -24,6 +24,11 @@
24 MDIO_MMDREG_DEVS0_PCS | \ 24 MDIO_MMDREG_DEVS0_PCS | \
25 MDIO_MMDREG_DEVS0_PHYXS) 25 MDIO_MMDREG_DEVS0_PHYXS)
26 26
27#define TENXPRESS_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
28 (1 << LOOPBACK_PCS) | \
29 (1 << LOOPBACK_PMAPMD) | \
30 (1 << LOOPBACK_NETWORK))
31
27/* We complain if we fail to see the link partner as 10G capable this many 32/* We complain if we fail to see the link partner as 10G capable this many
28 * times in a row (must be > 1 as sampling the autoneg. registers is racy) 33 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
29 */ 34 */
@@ -72,6 +77,10 @@
72#define PMA_PMD_BIST_RXD_LBN (1) 77#define PMA_PMD_BIST_RXD_LBN (1)
73#define PMA_PMD_BIST_AFE_LBN (0) 78#define PMA_PMD_BIST_AFE_LBN (0)
74 79
80/* Special Software reset register */
81#define PMA_PMD_EXT_CTRL_REG 49152
82#define PMA_PMD_EXT_SSR_LBN 15
83
75#define BIST_MAX_DELAY (1000) 84#define BIST_MAX_DELAY (1000)
76#define BIST_POLL_DELAY (10) 85#define BIST_POLL_DELAY (10)
77 86
@@ -86,6 +95,11 @@
86#define PCS_TEST_SELECT_REG 0xd807 /* PRM 10.5.8 */ 95#define PCS_TEST_SELECT_REG 0xd807 /* PRM 10.5.8 */
87#define CLK312_EN_LBN 3 96#define CLK312_EN_LBN 3
88 97
98/* PHYXS registers */
99#define PHYXS_TEST1 (49162)
100#define LOOPBACK_NEAR_LBN (8)
101#define LOOPBACK_NEAR_WIDTH (1)
102
89/* Boot status register */ 103/* Boot status register */
90#define PCS_BOOT_STATUS_REG (0xd000) 104#define PCS_BOOT_STATUS_REG (0xd000)
91#define PCS_BOOT_FATAL_ERR_LBN (0) 105#define PCS_BOOT_FATAL_ERR_LBN (0)
@@ -106,7 +120,9 @@ MODULE_PARM_DESC(crc_error_reset_threshold,
106 120
107struct tenxpress_phy_data { 121struct tenxpress_phy_data {
108 enum tenxpress_state state; 122 enum tenxpress_state state;
123 enum efx_loopback_mode loopback_mode;
109 atomic_t bad_crc_count; 124 atomic_t bad_crc_count;
125 int tx_disabled;
110 int bad_lp_tries; 126 int bad_lp_tries;
111}; 127};
112 128
@@ -199,10 +215,12 @@ static int tenxpress_phy_init(struct efx_nic *efx)
199 215
200 tenxpress_set_state(efx, TENXPRESS_STATUS_NORMAL); 216 tenxpress_set_state(efx, TENXPRESS_STATUS_NORMAL);
201 217
202 rc = mdio_clause45_wait_reset_mmds(efx, 218 if (!sfe4001_phy_flash_cfg) {
203 TENXPRESS_REQUIRED_DEVS); 219 rc = mdio_clause45_wait_reset_mmds(efx,
204 if (rc < 0) 220 TENXPRESS_REQUIRED_DEVS);
205 goto fail; 221 if (rc < 0)
222 goto fail;
223 }
206 224
207 rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0); 225 rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
208 if (rc < 0) 226 if (rc < 0)
@@ -225,6 +243,35 @@ static int tenxpress_phy_init(struct efx_nic *efx)
225 return rc; 243 return rc;
226} 244}
227 245
246static int tenxpress_special_reset(struct efx_nic *efx)
247{
248 int rc, reg;
249
250 EFX_TRACE(efx, "%s\n", __func__);
251
252 /* Initiate reset */
253 reg = mdio_clause45_read(efx, efx->mii.phy_id,
254 MDIO_MMD_PMAPMD, PMA_PMD_EXT_CTRL_REG);
255 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
256 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
257 PMA_PMD_EXT_CTRL_REG, reg);
258
259 msleep(200);
260
261 /* Wait for the blocks to come out of reset */
262 rc = mdio_clause45_wait_reset_mmds(efx,
263 TENXPRESS_REQUIRED_DEVS);
264 if (rc < 0)
265 return rc;
266
267 /* Try and reconfigure the device */
268 rc = tenxpress_init(efx);
269 if (rc < 0)
270 return rc;
271
272 return 0;
273}
274
228static void tenxpress_set_bad_lp(struct efx_nic *efx, int bad_lp) 275static void tenxpress_set_bad_lp(struct efx_nic *efx, int bad_lp)
229{ 276{
230 struct tenxpress_phy_data *pd = efx->phy_data; 277 struct tenxpress_phy_data *pd = efx->phy_data;
@@ -299,11 +346,46 @@ static int tenxpress_link_ok(struct efx_nic *efx, int check_lp)
299 return ok; 346 return ok;
300} 347}
301 348
349static void tenxpress_phyxs_loopback(struct efx_nic *efx)
350{
351 int phy_id = efx->mii.phy_id;
352 int ctrl1, ctrl2;
353
354 ctrl1 = ctrl2 = mdio_clause45_read(efx, phy_id, MDIO_MMD_PHYXS,
355 PHYXS_TEST1);
356 if (efx->loopback_mode == LOOPBACK_PHYXS)
357 ctrl2 |= (1 << LOOPBACK_NEAR_LBN);
358 else
359 ctrl2 &= ~(1 << LOOPBACK_NEAR_LBN);
360 if (ctrl1 != ctrl2)
361 mdio_clause45_write(efx, phy_id, MDIO_MMD_PHYXS,
362 PHYXS_TEST1, ctrl2);
363}
364
302static void tenxpress_phy_reconfigure(struct efx_nic *efx) 365static void tenxpress_phy_reconfigure(struct efx_nic *efx)
303{ 366{
367 struct tenxpress_phy_data *phy_data = efx->phy_data;
368 int loop_change = LOOPBACK_OUT_OF(phy_data, efx,
369 TENXPRESS_LOOPBACKS);
370
304 if (!tenxpress_state_is(efx, TENXPRESS_STATUS_NORMAL)) 371 if (!tenxpress_state_is(efx, TENXPRESS_STATUS_NORMAL))
305 return; 372 return;
306 373
374 /* When coming out of transmit disable, coming out of low power
375 * mode, or moving out of any PHY internal loopback mode,
376 * perform a special software reset */
377 if ((phy_data->tx_disabled && !efx->tx_disabled) ||
378 loop_change) {
379 (void) tenxpress_special_reset(efx);
380 falcon_reset_xaui(efx);
381 }
382
383 mdio_clause45_transmit_disable(efx);
384 mdio_clause45_phy_reconfigure(efx);
385 tenxpress_phyxs_loopback(efx);
386
387 phy_data->tx_disabled = efx->tx_disabled;
388 phy_data->loopback_mode = efx->loopback_mode;
307 efx->link_up = tenxpress_link_ok(efx, 0); 389 efx->link_up = tenxpress_link_ok(efx, 0);
308 efx->link_options = GM_LPA_10000FULL; 390 efx->link_options = GM_LPA_10000FULL;
309} 391}
@@ -431,4 +513,5 @@ struct efx_phy_operations falcon_tenxpress_phy_ops = {
431 .clear_interrupt = tenxpress_phy_clear_interrupt, 513 .clear_interrupt = tenxpress_phy_clear_interrupt,
432 .reset_xaui = tenxpress_reset_xaui, 514 .reset_xaui = tenxpress_reset_xaui,
433 .mmds = TENXPRESS_REQUIRED_DEVS, 515 .mmds = TENXPRESS_REQUIRED_DEVS,
516 .loopbacks = TENXPRESS_LOOPBACKS,
434}; 517};