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path: root/drivers/net/sfc/siena.c
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-rw-r--r--drivers/net/sfc/siena.c604
1 files changed, 604 insertions, 0 deletions
diff --git a/drivers/net/sfc/siena.c b/drivers/net/sfc/siena.c
new file mode 100644
index 000000000000..de07a4f031b2
--- /dev/null
+++ b/drivers/net/sfc/siena.c
@@ -0,0 +1,604 @@
1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2009 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
15#include "net_driver.h"
16#include "bitfield.h"
17#include "efx.h"
18#include "nic.h"
19#include "mac.h"
20#include "spi.h"
21#include "regs.h"
22#include "io.h"
23#include "phy.h"
24#include "workarounds.h"
25#include "mcdi.h"
26#include "mcdi_pcol.h"
27
28/* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
29
30static void siena_init_wol(struct efx_nic *efx);
31
32
33static void siena_push_irq_moderation(struct efx_channel *channel)
34{
35 efx_dword_t timer_cmd;
36
37 if (channel->irq_moderation)
38 EFX_POPULATE_DWORD_2(timer_cmd,
39 FRF_CZ_TC_TIMER_MODE,
40 FFE_CZ_TIMER_MODE_INT_HLDOFF,
41 FRF_CZ_TC_TIMER_VAL,
42 channel->irq_moderation - 1);
43 else
44 EFX_POPULATE_DWORD_2(timer_cmd,
45 FRF_CZ_TC_TIMER_MODE,
46 FFE_CZ_TIMER_MODE_DIS,
47 FRF_CZ_TC_TIMER_VAL, 0);
48 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
49 channel->channel);
50}
51
52static void siena_push_multicast_hash(struct efx_nic *efx)
53{
54 WARN_ON(!mutex_is_locked(&efx->mac_lock));
55
56 efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
57 efx->multicast_hash.byte, sizeof(efx->multicast_hash),
58 NULL, 0, NULL);
59}
60
61static int siena_mdio_write(struct net_device *net_dev,
62 int prtad, int devad, u16 addr, u16 value)
63{
64 struct efx_nic *efx = netdev_priv(net_dev);
65 uint32_t status;
66 int rc;
67
68 rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad,
69 addr, value, &status);
70 if (rc)
71 return rc;
72 if (status != MC_CMD_MDIO_STATUS_GOOD)
73 return -EIO;
74
75 return 0;
76}
77
78static int siena_mdio_read(struct net_device *net_dev,
79 int prtad, int devad, u16 addr)
80{
81 struct efx_nic *efx = netdev_priv(net_dev);
82 uint16_t value;
83 uint32_t status;
84 int rc;
85
86 rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad,
87 addr, &value, &status);
88 if (rc)
89 return rc;
90 if (status != MC_CMD_MDIO_STATUS_GOOD)
91 return -EIO;
92
93 return (int)value;
94}
95
96/* This call is responsible for hooking in the MAC and PHY operations */
97static int siena_probe_port(struct efx_nic *efx)
98{
99 int rc;
100
101 /* Hook in PHY operations table */
102 efx->phy_op = &efx_mcdi_phy_ops;
103
104 /* Set up MDIO structure for PHY */
105 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
106 efx->mdio.mdio_read = siena_mdio_read;
107 efx->mdio.mdio_write = siena_mdio_write;
108
109 /* Fill out MDIO structure and loopback modes */
110 rc = efx->phy_op->probe(efx);
111 if (rc != 0)
112 return rc;
113
114 /* Initial assumption */
115 efx->link_state.speed = 10000;
116 efx->link_state.fd = true;
117 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
118
119 /* Allocate buffer for stats */
120 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
121 MC_CMD_MAC_NSTATS * sizeof(u64));
122 if (rc)
123 return rc;
124 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
125 (u64)efx->stats_buffer.dma_addr,
126 efx->stats_buffer.addr,
127 (u64)virt_to_phys(efx->stats_buffer.addr));
128
129 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1);
130
131 return 0;
132}
133
134void siena_remove_port(struct efx_nic *efx)
135{
136 efx_nic_free_buffer(efx, &efx->stats_buffer);
137}
138
139static const struct efx_nic_register_test siena_register_tests[] = {
140 { FR_AZ_ADR_REGION,
141 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
142 { FR_CZ_USR_EV_CFG,
143 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
144 { FR_AZ_RX_CFG,
145 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
146 { FR_AZ_TX_CFG,
147 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
148 { FR_AZ_TX_RESERVED,
149 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
150 { FR_AZ_SRM_TX_DC_CFG,
151 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
152 { FR_AZ_RX_DC_CFG,
153 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
154 { FR_AZ_RX_DC_PF_WM,
155 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
156 { FR_BZ_DP_CTRL,
157 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
158 { FR_BZ_RX_RSS_TKEY,
159 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
160 { FR_CZ_RX_RSS_IPV6_REG1,
161 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
162 { FR_CZ_RX_RSS_IPV6_REG2,
163 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
164 { FR_CZ_RX_RSS_IPV6_REG3,
165 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
166};
167
168static int siena_test_registers(struct efx_nic *efx)
169{
170 return efx_nic_test_registers(efx, siena_register_tests,
171 ARRAY_SIZE(siena_register_tests));
172}
173
174/**************************************************************************
175 *
176 * Device reset
177 *
178 **************************************************************************
179 */
180
181static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
182{
183
184 if (method == RESET_TYPE_WORLD)
185 return efx_mcdi_reset_mc(efx);
186 else
187 return efx_mcdi_reset_port(efx);
188}
189
190static int siena_probe_nvconfig(struct efx_nic *efx)
191{
192 int rc;
193
194 rc = efx_mcdi_get_board_cfg(efx, efx->mac_address, NULL);
195 if (rc)
196 return rc;
197
198 return 0;
199}
200
201static int siena_probe_nic(struct efx_nic *efx)
202{
203 struct siena_nic_data *nic_data;
204 bool already_attached = 0;
205 int rc;
206
207 /* Allocate storage for hardware specific data */
208 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
209 if (!nic_data)
210 return -ENOMEM;
211 efx->nic_data = nic_data;
212
213 if (efx_nic_fpga_ver(efx) != 0) {
214 EFX_ERR(efx, "Siena FPGA not supported\n");
215 rc = -ENODEV;
216 goto fail1;
217 }
218
219 efx_mcdi_init(efx);
220
221 /* Recover from a failed assertion before probing */
222 rc = efx_mcdi_handle_assertion(efx);
223 if (rc)
224 goto fail1;
225
226 rc = efx_mcdi_fwver(efx, &nic_data->fw_version, &nic_data->fw_build);
227 if (rc) {
228 EFX_ERR(efx, "Failed to read MCPU firmware version - "
229 "rc %d\n", rc);
230 goto fail1; /* MCPU absent? */
231 }
232
233 /* Let the BMC know that the driver is now in charge of link and
234 * filter settings. We must do this before we reset the NIC */
235 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
236 if (rc) {
237 EFX_ERR(efx, "Unable to register driver with MCPU\n");
238 goto fail2;
239 }
240 if (already_attached)
241 /* Not a fatal error */
242 EFX_ERR(efx, "Host already registered with MCPU\n");
243
244 /* Now we can reset the NIC */
245 rc = siena_reset_hw(efx, RESET_TYPE_ALL);
246 if (rc) {
247 EFX_ERR(efx, "failed to reset NIC\n");
248 goto fail3;
249 }
250
251 siena_init_wol(efx);
252
253 /* Allocate memory for INT_KER */
254 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
255 if (rc)
256 goto fail4;
257 BUG_ON(efx->irq_status.dma_addr & 0x0f);
258
259 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
260 (unsigned long long)efx->irq_status.dma_addr,
261 efx->irq_status.addr,
262 (unsigned long long)virt_to_phys(efx->irq_status.addr));
263
264 /* Read in the non-volatile configuration */
265 rc = siena_probe_nvconfig(efx);
266 if (rc == -EINVAL) {
267 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
268 efx->phy_type = PHY_TYPE_NONE;
269 efx->mdio.prtad = MDIO_PRTAD_NONE;
270 } else if (rc) {
271 goto fail5;
272 }
273
274 return 0;
275
276fail5:
277 efx_nic_free_buffer(efx, &efx->irq_status);
278fail4:
279fail3:
280 efx_mcdi_drv_attach(efx, false, NULL);
281fail2:
282fail1:
283 kfree(efx->nic_data);
284 return rc;
285}
286
287/* This call performs hardware-specific global initialisation, such as
288 * defining the descriptor cache sizes and number of RSS channels.
289 * It does not set up any buffers, descriptor rings or event queues.
290 */
291static int siena_init_nic(struct efx_nic *efx)
292{
293 efx_oword_t temp;
294 int rc;
295
296 /* Recover from a failed assertion post-reset */
297 rc = efx_mcdi_handle_assertion(efx);
298 if (rc)
299 return rc;
300
301 /* Squash TX of packets of 16 bytes or less */
302 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
303 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
304 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
305
306 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
307 * descriptors (which is bad).
308 */
309 efx_reado(efx, &temp, FR_AZ_TX_CFG);
310 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
311 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
312 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
313
314 efx_reado(efx, &temp, FR_AZ_RX_CFG);
315 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
316 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
317 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
318
319 if (efx_nic_rx_xoff_thresh >= 0 || efx_nic_rx_xon_thresh >= 0)
320 /* No MCDI operation has been defined to set thresholds */
321 EFX_ERR(efx, "ignoring RX flow control thresholds\n");
322
323 /* Enable event logging */
324 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
325 if (rc)
326 return rc;
327
328 /* Set destination of both TX and RX Flush events */
329 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
330 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
331
332 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
333 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
334
335 efx_nic_init_common(efx);
336 return 0;
337}
338
339static void siena_remove_nic(struct efx_nic *efx)
340{
341 efx_nic_free_buffer(efx, &efx->irq_status);
342
343 siena_reset_hw(efx, RESET_TYPE_ALL);
344
345 /* Relinquish the device back to the BMC */
346 if (efx_nic_has_mc(efx))
347 efx_mcdi_drv_attach(efx, false, NULL);
348
349 /* Tear down the private nic state */
350 kfree(efx->nic_data);
351 efx->nic_data = NULL;
352}
353
354#define STATS_GENERATION_INVALID ((u64)(-1))
355
356static int siena_try_update_nic_stats(struct efx_nic *efx)
357{
358 u64 *dma_stats;
359 struct efx_mac_stats *mac_stats;
360 u64 generation_start;
361 u64 generation_end;
362
363 mac_stats = &efx->mac_stats;
364 dma_stats = (u64 *)efx->stats_buffer.addr;
365
366 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
367 if (generation_end == STATS_GENERATION_INVALID)
368 return 0;
369 rmb();
370
371#define MAC_STAT(M, D) \
372 mac_stats->M = dma_stats[MC_CMD_MAC_ ## D]
373
374 MAC_STAT(tx_bytes, TX_BYTES);
375 MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
376 mac_stats->tx_good_bytes = (mac_stats->tx_bytes -
377 mac_stats->tx_bad_bytes);
378 MAC_STAT(tx_packets, TX_PKTS);
379 MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
380 MAC_STAT(tx_pause, TX_PAUSE_PKTS);
381 MAC_STAT(tx_control, TX_CONTROL_PKTS);
382 MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
383 MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
384 MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
385 MAC_STAT(tx_lt64, TX_LT64_PKTS);
386 MAC_STAT(tx_64, TX_64_PKTS);
387 MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
388 MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
389 MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
390 MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
391 MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
392 MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
393 MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
394 mac_stats->tx_collision = 0;
395 MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
396 MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
397 MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
398 MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
399 MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
400 mac_stats->tx_collision = (mac_stats->tx_single_collision +
401 mac_stats->tx_multiple_collision +
402 mac_stats->tx_excessive_collision +
403 mac_stats->tx_late_collision);
404 MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
405 MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
406 MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
407 MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
408 MAC_STAT(rx_bytes, RX_BYTES);
409 MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
410 mac_stats->rx_good_bytes = (mac_stats->rx_bytes -
411 mac_stats->rx_bad_bytes);
412 MAC_STAT(rx_packets, RX_PKTS);
413 MAC_STAT(rx_good, RX_GOOD_PKTS);
414 mac_stats->rx_bad = mac_stats->rx_packets - mac_stats->rx_good;
415 MAC_STAT(rx_pause, RX_PAUSE_PKTS);
416 MAC_STAT(rx_control, RX_CONTROL_PKTS);
417 MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
418 MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
419 MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
420 MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
421 MAC_STAT(rx_64, RX_64_PKTS);
422 MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
423 MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
424 MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
425 MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
426 MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
427 MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
428 MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
429 mac_stats->rx_bad_lt64 = 0;
430 mac_stats->rx_bad_64_to_15xx = 0;
431 mac_stats->rx_bad_15xx_to_jumbo = 0;
432 MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
433 MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
434 mac_stats->rx_missed = 0;
435 MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
436 MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
437 MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
438 MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
439 MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
440 mac_stats->rx_good_lt64 = 0;
441
442 efx->n_rx_nodesc_drop_cnt = dma_stats[MC_CMD_MAC_RX_NODESC_DROPS];
443
444#undef MAC_STAT
445
446 rmb();
447 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
448 if (generation_end != generation_start)
449 return -EAGAIN;
450
451 return 0;
452}
453
454static void siena_update_nic_stats(struct efx_nic *efx)
455{
456 while (siena_try_update_nic_stats(efx) == -EAGAIN)
457 cpu_relax();
458}
459
460static void siena_start_nic_stats(struct efx_nic *efx)
461{
462 u64 *dma_stats = (u64 *)efx->stats_buffer.addr;
463
464 dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID;
465
466 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr,
467 MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0);
468}
469
470static void siena_stop_nic_stats(struct efx_nic *efx)
471{
472 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0);
473}
474
475void siena_print_fwver(struct efx_nic *efx, char *buf, size_t len)
476{
477 struct siena_nic_data *nic_data = efx->nic_data;
478 snprintf(buf, len, "%u.%u.%u.%u",
479 (unsigned int)(nic_data->fw_version >> 48),
480 (unsigned int)(nic_data->fw_version >> 32 & 0xffff),
481 (unsigned int)(nic_data->fw_version >> 16 & 0xffff),
482 (unsigned int)(nic_data->fw_version & 0xffff));
483}
484
485/**************************************************************************
486 *
487 * Wake on LAN
488 *
489 **************************************************************************
490 */
491
492static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
493{
494 struct siena_nic_data *nic_data = efx->nic_data;
495
496 wol->supported = WAKE_MAGIC;
497 if (nic_data->wol_filter_id != -1)
498 wol->wolopts = WAKE_MAGIC;
499 else
500 wol->wolopts = 0;
501 memset(&wol->sopass, 0, sizeof(wol->sopass));
502}
503
504
505static int siena_set_wol(struct efx_nic *efx, u32 type)
506{
507 struct siena_nic_data *nic_data = efx->nic_data;
508 int rc;
509
510 if (type & ~WAKE_MAGIC)
511 return -EINVAL;
512
513 if (type & WAKE_MAGIC) {
514 if (nic_data->wol_filter_id != -1)
515 efx_mcdi_wol_filter_remove(efx,
516 nic_data->wol_filter_id);
517 rc = efx_mcdi_wol_filter_set_magic(efx, efx->mac_address,
518 &nic_data->wol_filter_id);
519 if (rc)
520 goto fail;
521
522 pci_wake_from_d3(efx->pci_dev, true);
523 } else {
524 rc = efx_mcdi_wol_filter_reset(efx);
525 nic_data->wol_filter_id = -1;
526 pci_wake_from_d3(efx->pci_dev, false);
527 if (rc)
528 goto fail;
529 }
530
531 return 0;
532 fail:
533 EFX_ERR(efx, "%s failed: type=%d rc=%d\n", __func__, type, rc);
534 return rc;
535}
536
537
538static void siena_init_wol(struct efx_nic *efx)
539{
540 struct siena_nic_data *nic_data = efx->nic_data;
541 int rc;
542
543 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
544
545 if (rc != 0) {
546 /* If it failed, attempt to get into a synchronised
547 * state with MC by resetting any set WoL filters */
548 efx_mcdi_wol_filter_reset(efx);
549 nic_data->wol_filter_id = -1;
550 } else if (nic_data->wol_filter_id != -1) {
551 pci_wake_from_d3(efx->pci_dev, true);
552 }
553}
554
555
556/**************************************************************************
557 *
558 * Revision-dependent attributes used by efx.c and nic.c
559 *
560 **************************************************************************
561 */
562
563struct efx_nic_type siena_a0_nic_type = {
564 .probe = siena_probe_nic,
565 .remove = siena_remove_nic,
566 .init = siena_init_nic,
567 .fini = efx_port_dummy_op_void,
568 .monitor = NULL,
569 .reset = siena_reset_hw,
570 .probe_port = siena_probe_port,
571 .remove_port = siena_remove_port,
572 .prepare_flush = efx_port_dummy_op_void,
573 .update_stats = siena_update_nic_stats,
574 .start_stats = siena_start_nic_stats,
575 .stop_stats = siena_stop_nic_stats,
576 .set_id_led = efx_mcdi_set_id_led,
577 .push_irq_moderation = siena_push_irq_moderation,
578 .push_multicast_hash = siena_push_multicast_hash,
579 .reconfigure_port = efx_mcdi_phy_reconfigure,
580 .get_wol = siena_get_wol,
581 .set_wol = siena_set_wol,
582 .resume_wol = siena_init_wol,
583 .test_registers = siena_test_registers,
584 .default_mac_ops = &efx_mcdi_mac_operations,
585
586 .revision = EFX_REV_SIENA_A0,
587 .mem_map_size = (FR_CZ_MC_TREG_SMEM +
588 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS),
589 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
590 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
591 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
592 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
593 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
594 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
595 .rx_buffer_padding = 0,
596 .max_interrupt_mode = EFX_INT_MODE_MSIX,
597 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
598 * interrupt handler only supports 32
599 * channels */
600 .tx_dc_base = 0x88000,
601 .rx_dc_base = 0x68000,
602 .offload_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM,
603 .reset_world_flags = ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT,
604};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 04:46:43 -0500