diff options
Diffstat (limited to 'drivers/net/sfc/falcon_xmac.c')
-rw-r--r-- | drivers/net/sfc/falcon_xmac.c | 88 |
1 files changed, 1 insertions, 87 deletions
diff --git a/drivers/net/sfc/falcon_xmac.c b/drivers/net/sfc/falcon_xmac.c index 0d9f68ff71e7..d4012314dd01 100644 --- a/drivers/net/sfc/falcon_xmac.c +++ b/drivers/net/sfc/falcon_xmac.c | |||
@@ -78,79 +78,7 @@ static void falcon_setup_xaui(struct efx_nic *efx) | |||
78 | falcon_write(efx, &txdrv, XX_TXDRV_CTL_REG); | 78 | falcon_write(efx, &txdrv, XX_TXDRV_CTL_REG); |
79 | } | 79 | } |
80 | 80 | ||
81 | static void falcon_hold_xaui_in_rst(struct efx_nic *efx) | 81 | int falcon_reset_xaui(struct efx_nic *efx) |
82 | { | ||
83 | efx_oword_t reg; | ||
84 | |||
85 | EFX_ZERO_OWORD(reg); | ||
86 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNA_EN, 1); | ||
87 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNB_EN, 1); | ||
88 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNC_EN, 1); | ||
89 | EFX_SET_OWORD_FIELD(reg, XX_PWRDND_EN, 1); | ||
90 | EFX_SET_OWORD_FIELD(reg, XX_RSTPLLAB_EN, 1); | ||
91 | EFX_SET_OWORD_FIELD(reg, XX_RSTPLLCD_EN, 1); | ||
92 | EFX_SET_OWORD_FIELD(reg, XX_RESETA_EN, 1); | ||
93 | EFX_SET_OWORD_FIELD(reg, XX_RESETB_EN, 1); | ||
94 | EFX_SET_OWORD_FIELD(reg, XX_RESETC_EN, 1); | ||
95 | EFX_SET_OWORD_FIELD(reg, XX_RESETD_EN, 1); | ||
96 | EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSRX_EN, 1); | ||
97 | EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSTX_EN, 1); | ||
98 | falcon_write(efx, ®, XX_PWR_RST_REG); | ||
99 | udelay(10); | ||
100 | } | ||
101 | |||
102 | static int _falcon_reset_xaui_a(struct efx_nic *efx) | ||
103 | { | ||
104 | efx_oword_t reg; | ||
105 | |||
106 | falcon_hold_xaui_in_rst(efx); | ||
107 | falcon_read(efx, ®, XX_PWR_RST_REG); | ||
108 | |||
109 | /* Follow the RAMBUS XAUI data reset sequencing | ||
110 | * Channels A and B first: power down, reset PLL, reset, clear | ||
111 | */ | ||
112 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNA_EN, 0); | ||
113 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNB_EN, 0); | ||
114 | falcon_write(efx, ®, XX_PWR_RST_REG); | ||
115 | udelay(10); | ||
116 | |||
117 | EFX_SET_OWORD_FIELD(reg, XX_RSTPLLAB_EN, 0); | ||
118 | falcon_write(efx, ®, XX_PWR_RST_REG); | ||
119 | udelay(10); | ||
120 | |||
121 | EFX_SET_OWORD_FIELD(reg, XX_RESETA_EN, 0); | ||
122 | EFX_SET_OWORD_FIELD(reg, XX_RESETB_EN, 0); | ||
123 | falcon_write(efx, ®, XX_PWR_RST_REG); | ||
124 | udelay(10); | ||
125 | |||
126 | /* Channels C and D: power down, reset PLL, reset, clear */ | ||
127 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNC_EN, 0); | ||
128 | EFX_SET_OWORD_FIELD(reg, XX_PWRDND_EN, 0); | ||
129 | falcon_write(efx, ®, XX_PWR_RST_REG); | ||
130 | udelay(10); | ||
131 | |||
132 | EFX_SET_OWORD_FIELD(reg, XX_RSTPLLCD_EN, 0); | ||
133 | falcon_write(efx, ®, XX_PWR_RST_REG); | ||
134 | udelay(10); | ||
135 | |||
136 | EFX_SET_OWORD_FIELD(reg, XX_RESETC_EN, 0); | ||
137 | EFX_SET_OWORD_FIELD(reg, XX_RESETD_EN, 0); | ||
138 | falcon_write(efx, ®, XX_PWR_RST_REG); | ||
139 | udelay(10); | ||
140 | |||
141 | /* Setup XAUI */ | ||
142 | falcon_setup_xaui(efx); | ||
143 | udelay(10); | ||
144 | |||
145 | /* Take XGXS out of reset */ | ||
146 | EFX_ZERO_OWORD(reg); | ||
147 | falcon_write(efx, ®, XX_PWR_RST_REG); | ||
148 | udelay(10); | ||
149 | |||
150 | return 0; | ||
151 | } | ||
152 | |||
153 | static int _falcon_reset_xaui_b(struct efx_nic *efx) | ||
154 | { | 82 | { |
155 | efx_oword_t reg; | 83 | efx_oword_t reg; |
156 | int count; | 84 | int count; |
@@ -171,20 +99,6 @@ static int _falcon_reset_xaui_b(struct efx_nic *efx) | |||
171 | return -ETIMEDOUT; | 99 | return -ETIMEDOUT; |
172 | } | 100 | } |
173 | 101 | ||
174 | int falcon_reset_xaui(struct efx_nic *efx) | ||
175 | { | ||
176 | int rc; | ||
177 | |||
178 | if (EFX_WORKAROUND_9388(efx)) { | ||
179 | falcon_hold_xaui_in_rst(efx); | ||
180 | efx->phy_op->reset_xaui(efx); | ||
181 | rc = _falcon_reset_xaui_a(efx); | ||
182 | } else { | ||
183 | rc = _falcon_reset_xaui_b(efx); | ||
184 | } | ||
185 | return rc; | ||
186 | } | ||
187 | |||
188 | static bool falcon_xgmii_status(struct efx_nic *efx) | 102 | static bool falcon_xgmii_status(struct efx_nic *efx) |
189 | { | 103 | { |
190 | efx_oword_t reg; | 104 | efx_oword_t reg; |