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path: root/drivers/net/sfc/falcon.c
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Diffstat (limited to 'drivers/net/sfc/falcon.c')
-rw-r--r--drivers/net/sfc/falcon.c13
1 files changed, 6 insertions, 7 deletions
diff --git a/drivers/net/sfc/falcon.c b/drivers/net/sfc/falcon.c
index 08f540f072b8..040f553de665 100644
--- a/drivers/net/sfc/falcon.c
+++ b/drivers/net/sfc/falcon.c
@@ -1939,7 +1939,6 @@ void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1939 struct efx_link_state *link_state = &efx->link_state; 1939 struct efx_link_state *link_state = &efx->link_state;
1940 efx_oword_t reg; 1940 efx_oword_t reg;
1941 int link_speed; 1941 int link_speed;
1942 bool tx_fc;
1943 1942
1944 switch (link_state->speed) { 1943 switch (link_state->speed) {
1945 case 10000: link_speed = 3; break; 1944 case 10000: link_speed = 3; break;
@@ -1969,13 +1968,10 @@ void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1969 /* Restore the multicast hash registers. */ 1968 /* Restore the multicast hash registers. */
1970 falcon_push_multicast_hash(efx); 1969 falcon_push_multicast_hash(efx);
1971 1970
1972 /* Transmission of pause frames when RX crosses the threshold is
1973 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1974 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1975 tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
1976 efx_reado(efx, &reg, FR_AZ_RX_CFG); 1971 efx_reado(efx, &reg, FR_AZ_RX_CFG);
1977 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc); 1972 /* Enable XOFF signal from RX FIFO (we enabled it during NIC
1978 1973 * initialisation but it may read back as 0) */
1974 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1979 /* Unisolate the MAC -> RX */ 1975 /* Unisolate the MAC -> RX */
1980 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) 1976 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1981 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); 1977 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
@@ -3000,6 +2996,9 @@ static void falcon_init_rx_cfg(struct efx_nic *efx)
3000 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr); 2996 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
3001 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); 2997 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
3002 } 2998 }
2999 /* Always enable XOFF signal from RX FIFO. We enable
3000 * or disable transmission of pause frames at the MAC. */
3001 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
3003 efx_writeo(efx, &reg, FR_AZ_RX_CFG); 3002 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
3004} 3003}
3005 3004