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-rw-r--r--drivers/net/sb1250-mac.c1119
1 files changed, 519 insertions, 600 deletions
diff --git a/drivers/net/sb1250-mac.c b/drivers/net/sb1250-mac.c
index 0cffd46724df..7b53d658e337 100644
--- a/drivers/net/sb1250-mac.c
+++ b/drivers/net/sb1250-mac.c
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation 2 * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
3 * Copyright (c) 2006, 2007 Maciej W. Rozycki
3 * 4 *
4 * This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
@@ -18,7 +19,12 @@
18 * 19 *
19 * This driver is designed for the Broadcom SiByte SOC built-in 20 * This driver is designed for the Broadcom SiByte SOC built-in
20 * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp. 21 * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
22 *
23 * Updated to the driver model and the PHY abstraction layer
24 * by Maciej W. Rozycki.
21 */ 25 */
26
27#include <linux/bug.h>
22#include <linux/module.h> 28#include <linux/module.h>
23#include <linux/kernel.h> 29#include <linux/kernel.h>
24#include <linux/string.h> 30#include <linux/string.h>
@@ -32,9 +38,15 @@
32#include <linux/skbuff.h> 38#include <linux/skbuff.h>
33#include <linux/init.h> 39#include <linux/init.h>
34#include <linux/bitops.h> 40#include <linux/bitops.h>
35#include <asm/processor.h> /* Processor type for cache alignment. */ 41#include <linux/err.h>
36#include <asm/io.h> 42#include <linux/ethtool.h>
43#include <linux/mii.h>
44#include <linux/phy.h>
45#include <linux/platform_device.h>
46
37#include <asm/cache.h> 47#include <asm/cache.h>
48#include <asm/io.h>
49#include <asm/processor.h> /* Processor type for cache alignment. */
38 50
39/* This is only here until the firmware is ready. In that case, 51/* This is only here until the firmware is ready. In that case,
40 the firmware leaves the ethernet address in the register for us. */ 52 the firmware leaves the ethernet address in the register for us. */
@@ -48,7 +60,7 @@
48 60
49/* These identify the driver base version and may not be removed. */ 61/* These identify the driver base version and may not be removed. */
50#if 0 62#if 0
51static char version1[] __devinitdata = 63static char version1[] __initdata =
52"sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n"; 64"sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
53#endif 65#endif
54 66
@@ -57,8 +69,6 @@ static char version1[] __devinitdata =
57 69
58#define CONFIG_SBMAC_COALESCE 70#define CONFIG_SBMAC_COALESCE
59 71
60#define MAX_UNITS 4 /* More are supported, limit only on options */
61
62/* Time in jiffies before concluding the transmitter is hung. */ 72/* Time in jiffies before concluding the transmitter is hung. */
63#define TX_TIMEOUT (2*HZ) 73#define TX_TIMEOUT (2*HZ)
64 74
@@ -74,26 +84,6 @@ static int debug = 1;
74module_param(debug, int, S_IRUGO); 84module_param(debug, int, S_IRUGO);
75MODULE_PARM_DESC(debug, "Debug messages"); 85MODULE_PARM_DESC(debug, "Debug messages");
76 86
77/* mii status msgs */
78static int noisy_mii = 1;
79module_param(noisy_mii, int, S_IRUGO);
80MODULE_PARM_DESC(noisy_mii, "MII status messages");
81
82/* Used to pass the media type, etc.
83 Both 'options[]' and 'full_duplex[]' should exist for driver
84 interoperability.
85 The media type is usually passed in 'options[]'.
86*/
87#ifdef MODULE
88static int options[MAX_UNITS] = {-1, -1, -1, -1};
89module_param_array(options, int, NULL, S_IRUGO);
90MODULE_PARM_DESC(options, "1-" __MODULE_STRING(MAX_UNITS));
91
92static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1};
93module_param_array(full_duplex, int, NULL, S_IRUGO);
94MODULE_PARM_DESC(full_duplex, "1-" __MODULE_STRING(MAX_UNITS));
95#endif
96
97#ifdef CONFIG_SBMAC_COALESCE 87#ifdef CONFIG_SBMAC_COALESCE
98static int int_pktcnt_tx = 255; 88static int int_pktcnt_tx = 255;
99module_param(int_pktcnt_tx, int, S_IRUGO); 89module_param(int_pktcnt_tx, int, S_IRUGO);
@@ -112,6 +102,7 @@ module_param(int_timeout_rx, int, S_IRUGO);
112MODULE_PARM_DESC(int_timeout_rx, "RX timeout value"); 102MODULE_PARM_DESC(int_timeout_rx, "RX timeout value");
113#endif 103#endif
114 104
105#include <asm/sibyte/board.h>
115#include <asm/sibyte/sb1250.h> 106#include <asm/sibyte/sb1250.h>
116#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 107#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
117#include <asm/sibyte/bcm1480_regs.h> 108#include <asm/sibyte/bcm1480_regs.h>
@@ -135,22 +126,43 @@ MODULE_PARM_DESC(int_timeout_rx, "RX timeout value");
135#error invalid SiByte MAC configuation 126#error invalid SiByte MAC configuation
136#endif 127#endif
137 128
129#ifdef K_INT_PHY
130#define SBMAC_PHY_INT K_INT_PHY
131#else
132#define SBMAC_PHY_INT PHY_POLL
133#endif
134
138/********************************************************************** 135/**********************************************************************
139 * Simple types 136 * Simple types
140 ********************************************************************* */ 137 ********************************************************************* */
141 138
139enum sbmac_speed {
140 sbmac_speed_none = 0,
141 sbmac_speed_10 = SPEED_10,
142 sbmac_speed_100 = SPEED_100,
143 sbmac_speed_1000 = SPEED_1000,
144};
142 145
143enum sbmac_speed { sbmac_speed_auto, sbmac_speed_10, 146enum sbmac_duplex {
144 sbmac_speed_100, sbmac_speed_1000 }; 147 sbmac_duplex_none = -1,
145 148 sbmac_duplex_half = DUPLEX_HALF,
146enum sbmac_duplex { sbmac_duplex_auto, sbmac_duplex_half, 149 sbmac_duplex_full = DUPLEX_FULL,
147 sbmac_duplex_full }; 150};
148 151
149enum sbmac_fc { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame, 152enum sbmac_fc {
150 sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t; 153 sbmac_fc_none,
154 sbmac_fc_disabled,
155 sbmac_fc_frame,
156 sbmac_fc_collision,
157 sbmac_fc_carrier,
158};
151 159
152enum sbmac_state { sbmac_state_uninit, sbmac_state_off, sbmac_state_on, 160enum sbmac_state {
153 sbmac_state_broken }; 161 sbmac_state_uninit,
162 sbmac_state_off,
163 sbmac_state_on,
164 sbmac_state_broken,
165};
154 166
155 167
156/********************************************************************** 168/**********************************************************************
@@ -244,18 +256,14 @@ struct sbmac_softc {
244 */ 256 */
245 struct net_device *sbm_dev; /* pointer to linux device */ 257 struct net_device *sbm_dev; /* pointer to linux device */
246 struct napi_struct napi; 258 struct napi_struct napi;
259 struct phy_device *phy_dev; /* the associated PHY device */
260 struct mii_bus mii_bus; /* the MII bus */
261 int phy_irq[PHY_MAX_ADDR];
247 spinlock_t sbm_lock; /* spin lock */ 262 spinlock_t sbm_lock; /* spin lock */
248 struct timer_list sbm_timer; /* for monitoring MII */
249 int sbm_devflags; /* current device flags */ 263 int sbm_devflags; /* current device flags */
250 264
251 int sbm_phy_oldbmsr;
252 int sbm_phy_oldanlpar;
253 int sbm_phy_oldk1stsr;
254 int sbm_phy_oldlinkstat;
255 int sbm_buffersize; 265 int sbm_buffersize;
256 266
257 unsigned char sbm_phys[2];
258
259 /* 267 /*
260 * Controller-specific things 268 * Controller-specific things
261 */ 269 */
@@ -274,6 +282,8 @@ struct sbmac_softc {
274 enum sbmac_speed sbm_speed; /* current speed */ 282 enum sbmac_speed sbm_speed; /* current speed */
275 enum sbmac_duplex sbm_duplex; /* current duplex */ 283 enum sbmac_duplex sbm_duplex; /* current duplex */
276 enum sbmac_fc sbm_fc; /* cur. flow control setting */ 284 enum sbmac_fc sbm_fc; /* cur. flow control setting */
285 int sbm_pause; /* current pause setting */
286 int sbm_link; /* current link state */
277 287
278 unsigned char sbm_hwaddr[ETHER_ADDR_LEN]; 288 unsigned char sbm_hwaddr[ETHER_ADDR_LEN];
279 289
@@ -313,36 +323,37 @@ static uint64_t sbmac_addr2reg(unsigned char *ptr);
313static irqreturn_t sbmac_intr(int irq, void *dev_instance); 323static irqreturn_t sbmac_intr(int irq, void *dev_instance);
314static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev); 324static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
315static void sbmac_setmulti(struct sbmac_softc *sc); 325static void sbmac_setmulti(struct sbmac_softc *sc);
316static int sbmac_init(struct net_device *dev, int idx); 326static int sbmac_init(struct platform_device *pldev, long long base);
317static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed); 327static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed);
318static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex, 328static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
319 enum sbmac_fc fc); 329 enum sbmac_fc fc);
320 330
321static int sbmac_open(struct net_device *dev); 331static int sbmac_open(struct net_device *dev);
322static void sbmac_timer(unsigned long data);
323static void sbmac_tx_timeout (struct net_device *dev); 332static void sbmac_tx_timeout (struct net_device *dev);
324static void sbmac_set_rx_mode(struct net_device *dev); 333static void sbmac_set_rx_mode(struct net_device *dev);
325static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 334static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
326static int sbmac_close(struct net_device *dev); 335static int sbmac_close(struct net_device *dev);
327static int sbmac_poll(struct napi_struct *napi, int budget); 336static int sbmac_poll(struct napi_struct *napi, int budget);
328 337
329static int sbmac_mii_poll(struct sbmac_softc *s, int noisy); 338static void sbmac_mii_poll(struct net_device *dev);
330static int sbmac_mii_probe(struct net_device *dev); 339static int sbmac_mii_probe(struct net_device *dev);
331 340
332static void sbmac_mii_sync(struct sbmac_softc *s); 341static void sbmac_mii_sync(void __iomem *sbm_mdio);
333static void sbmac_mii_senddata(struct sbmac_softc *s, unsigned int data, 342static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,
334 int bitcnt); 343 int bitcnt);
335static unsigned int sbmac_mii_read(struct sbmac_softc *s, int phyaddr, 344static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx);
336 int regidx); 345static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
337static void sbmac_mii_write(struct sbmac_softc *s, int phyaddr, int regidx, 346 u16 val);
338 unsigned int regval);
339 347
340 348
341/********************************************************************** 349/**********************************************************************
342 * Globals 350 * Globals
343 ********************************************************************* */ 351 ********************************************************************* */
344 352
345static uint64_t sbmac_orig_hwaddr[MAX_UNITS]; 353static char sbmac_string[] = "sb1250-mac";
354static char sbmac_pretty[] = "SB1250 MAC";
355
356static char sbmac_mdio_string[] = "sb1250-mac-mdio";
346 357
347 358
348/********************************************************************** 359/**********************************************************************
@@ -354,185 +365,66 @@ static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
354#define MII_COMMAND_WRITE 0x01 365#define MII_COMMAND_WRITE 0x01
355#define MII_COMMAND_ACK 0x02 366#define MII_COMMAND_ACK 0x02
356 367
357#define BMCR_RESET 0x8000
358#define BMCR_LOOPBACK 0x4000
359#define BMCR_SPEED0 0x2000
360#define BMCR_ANENABLE 0x1000
361#define BMCR_POWERDOWN 0x0800
362#define BMCR_ISOLATE 0x0400
363#define BMCR_RESTARTAN 0x0200
364#define BMCR_DUPLEX 0x0100
365#define BMCR_COLTEST 0x0080
366#define BMCR_SPEED1 0x0040
367#define BMCR_SPEED1000 BMCR_SPEED1
368#define BMCR_SPEED100 BMCR_SPEED0
369#define BMCR_SPEED10 0
370
371#define BMSR_100BT4 0x8000
372#define BMSR_100BT_FDX 0x4000
373#define BMSR_100BT_HDX 0x2000
374#define BMSR_10BT_FDX 0x1000
375#define BMSR_10BT_HDX 0x0800
376#define BMSR_100BT2_FDX 0x0400
377#define BMSR_100BT2_HDX 0x0200
378#define BMSR_1000BT_XSR 0x0100
379#define BMSR_PRESUP 0x0040
380#define BMSR_ANCOMPLT 0x0020
381#define BMSR_REMFAULT 0x0010
382#define BMSR_AUTONEG 0x0008
383#define BMSR_LINKSTAT 0x0004
384#define BMSR_JABDETECT 0x0002
385#define BMSR_EXTCAPAB 0x0001
386
387#define PHYIDR1 0x2000
388#define PHYIDR2 0x5C60
389
390#define ANAR_NP 0x8000
391#define ANAR_RF 0x2000
392#define ANAR_ASYPAUSE 0x0800
393#define ANAR_PAUSE 0x0400
394#define ANAR_T4 0x0200
395#define ANAR_TXFD 0x0100
396#define ANAR_TXHD 0x0080
397#define ANAR_10FD 0x0040
398#define ANAR_10HD 0x0020
399#define ANAR_PSB 0x0001
400
401#define ANLPAR_NP 0x8000
402#define ANLPAR_ACK 0x4000
403#define ANLPAR_RF 0x2000
404#define ANLPAR_ASYPAUSE 0x0800
405#define ANLPAR_PAUSE 0x0400
406#define ANLPAR_T4 0x0200
407#define ANLPAR_TXFD 0x0100
408#define ANLPAR_TXHD 0x0080
409#define ANLPAR_10FD 0x0040
410#define ANLPAR_10HD 0x0020
411#define ANLPAR_PSB 0x0001 /* 802.3 */
412
413#define ANER_PDF 0x0010
414#define ANER_LPNPABLE 0x0008
415#define ANER_NPABLE 0x0004
416#define ANER_PAGERX 0x0002
417#define ANER_LPANABLE 0x0001
418
419#define ANNPTR_NP 0x8000
420#define ANNPTR_MP 0x2000
421#define ANNPTR_ACK2 0x1000
422#define ANNPTR_TOGTX 0x0800
423#define ANNPTR_CODE 0x0008
424
425#define ANNPRR_NP 0x8000
426#define ANNPRR_MP 0x2000
427#define ANNPRR_ACK3 0x1000
428#define ANNPRR_TOGTX 0x0800
429#define ANNPRR_CODE 0x0008
430
431#define K1TCR_TESTMODE 0x0000
432#define K1TCR_MSMCE 0x1000
433#define K1TCR_MSCV 0x0800
434#define K1TCR_RPTR 0x0400
435#define K1TCR_1000BT_FDX 0x200
436#define K1TCR_1000BT_HDX 0x100
437
438#define K1STSR_MSMCFLT 0x8000
439#define K1STSR_MSCFGRES 0x4000
440#define K1STSR_LRSTAT 0x2000
441#define K1STSR_RRSTAT 0x1000
442#define K1STSR_LP1KFD 0x0800
443#define K1STSR_LP1KHD 0x0400
444#define K1STSR_LPASMDIR 0x0200
445
446#define K1SCR_1KX_FDX 0x8000
447#define K1SCR_1KX_HDX 0x4000
448#define K1SCR_1KT_FDX 0x2000
449#define K1SCR_1KT_HDX 0x1000
450
451#define STRAP_PHY1 0x0800
452#define STRAP_NCMODE 0x0400
453#define STRAP_MANMSCFG 0x0200
454#define STRAP_ANENABLE 0x0100
455#define STRAP_MSVAL 0x0080
456#define STRAP_1KHDXADV 0x0010
457#define STRAP_1KFDXADV 0x0008
458#define STRAP_100ADV 0x0004
459#define STRAP_SPEEDSEL 0x0000
460#define STRAP_SPEED100 0x0001
461
462#define PHYSUP_SPEED1000 0x10
463#define PHYSUP_SPEED100 0x08
464#define PHYSUP_SPEED10 0x00
465#define PHYSUP_LINKUP 0x04
466#define PHYSUP_FDX 0x02
467
468#define MII_BMCR 0x00 /* Basic mode control register (rw) */
469#define MII_BMSR 0x01 /* Basic mode status register (ro) */
470#define MII_PHYIDR1 0x02
471#define MII_PHYIDR2 0x03
472
473#define MII_K1STSR 0x0A /* 1K Status Register (ro) */
474#define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */
475
476
477#define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */ 368#define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */
478 369
479#define ENABLE 1 370#define ENABLE 1
480#define DISABLE 0 371#define DISABLE 0
481 372
482/********************************************************************** 373/**********************************************************************
483 * SBMAC_MII_SYNC(s) 374 * SBMAC_MII_SYNC(sbm_mdio)
484 * 375 *
485 * Synchronize with the MII - send a pattern of bits to the MII 376 * Synchronize with the MII - send a pattern of bits to the MII
486 * that will guarantee that it is ready to accept a command. 377 * that will guarantee that it is ready to accept a command.
487 * 378 *
488 * Input parameters: 379 * Input parameters:
489 * s - sbmac structure 380 * sbm_mdio - address of the MAC's MDIO register
490 * 381 *
491 * Return value: 382 * Return value:
492 * nothing 383 * nothing
493 ********************************************************************* */ 384 ********************************************************************* */
494 385
495static void sbmac_mii_sync(struct sbmac_softc *s) 386static void sbmac_mii_sync(void __iomem *sbm_mdio)
496{ 387{
497 int cnt; 388 int cnt;
498 uint64_t bits; 389 uint64_t bits;
499 int mac_mdio_genc; 390 int mac_mdio_genc;
500 391
501 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC; 392 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
502 393
503 bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT; 394 bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
504 395
505 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); 396 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
506 397
507 for (cnt = 0; cnt < 32; cnt++) { 398 for (cnt = 0; cnt < 32; cnt++) {
508 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); 399 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
509 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); 400 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
510 } 401 }
511} 402}
512 403
513/********************************************************************** 404/**********************************************************************
514 * SBMAC_MII_SENDDATA(s,data,bitcnt) 405 * SBMAC_MII_SENDDATA(sbm_mdio, data, bitcnt)
515 * 406 *
516 * Send some bits to the MII. The bits to be sent are right- 407 * Send some bits to the MII. The bits to be sent are right-
517 * justified in the 'data' parameter. 408 * justified in the 'data' parameter.
518 * 409 *
519 * Input parameters: 410 * Input parameters:
520 * s - sbmac structure 411 * sbm_mdio - address of the MAC's MDIO register
521 * data - data to send 412 * data - data to send
522 * bitcnt - number of bits to send 413 * bitcnt - number of bits to send
523 ********************************************************************* */ 414 ********************************************************************* */
524 415
525static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt) 416static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,
417 int bitcnt)
526{ 418{
527 int i; 419 int i;
528 uint64_t bits; 420 uint64_t bits;
529 unsigned int curmask; 421 unsigned int curmask;
530 int mac_mdio_genc; 422 int mac_mdio_genc;
531 423
532 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC; 424 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
533 425
534 bits = M_MAC_MDIO_DIR_OUTPUT; 426 bits = M_MAC_MDIO_DIR_OUTPUT;
535 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); 427 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
536 428
537 curmask = 1 << (bitcnt - 1); 429 curmask = 1 << (bitcnt - 1);
538 430
@@ -540,9 +432,9 @@ static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitc
540 if (data & curmask) 432 if (data & curmask)
541 bits |= M_MAC_MDIO_OUT; 433 bits |= M_MAC_MDIO_OUT;
542 else bits &= ~M_MAC_MDIO_OUT; 434 else bits &= ~M_MAC_MDIO_OUT;
543 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); 435 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
544 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); 436 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
545 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); 437 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
546 curmask >>= 1; 438 curmask >>= 1;
547 } 439 }
548} 440}
@@ -550,21 +442,22 @@ static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitc
550 442
551 443
552/********************************************************************** 444/**********************************************************************
553 * SBMAC_MII_READ(s,phyaddr,regidx) 445 * SBMAC_MII_READ(bus, phyaddr, regidx)
554 *
555 * Read a PHY register. 446 * Read a PHY register.
556 * 447 *
557 * Input parameters: 448 * Input parameters:
558 * s - sbmac structure 449 * bus - MDIO bus handle
559 * phyaddr - PHY's address 450 * phyaddr - PHY's address
560 * regidx = index of register to read 451 * regnum - index of register to read
561 * 452 *
562 * Return value: 453 * Return value:
563 * value read, or 0 if an error occurred. 454 * value read, or 0xffff if an error occurred.
564 ********************************************************************* */ 455 ********************************************************************* */
565 456
566static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx) 457static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
567{ 458{
459 struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv;
460 void __iomem *sbm_mdio = sc->sbm_mdio;
568 int idx; 461 int idx;
569 int error; 462 int error;
570 int regval; 463 int regval;
@@ -574,8 +467,7 @@ static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
574 * Synchronize ourselves so that the PHY knows the next 467 * Synchronize ourselves so that the PHY knows the next
575 * thing coming down is a command 468 * thing coming down is a command
576 */ 469 */
577 470 sbmac_mii_sync(sbm_mdio);
578 sbmac_mii_sync(s);
579 471
580 /* 472 /*
581 * Send the data to the PHY. The sequence is 473 * Send the data to the PHY. The sequence is
@@ -584,37 +476,37 @@ static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
584 * the PHY addr (5 bits) 476 * the PHY addr (5 bits)
585 * the register index (5 bits) 477 * the register index (5 bits)
586 */ 478 */
479 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
480 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_READ, 2);
481 sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
482 sbmac_mii_senddata(sbm_mdio, regidx, 5);
587 483
588 sbmac_mii_senddata(s,MII_COMMAND_START, 2); 484 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
589 sbmac_mii_senddata(s,MII_COMMAND_READ, 2);
590 sbmac_mii_senddata(s,phyaddr, 5);
591 sbmac_mii_senddata(s,regidx, 5);
592
593 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
594 485
595 /* 486 /*
596 * Switch the port around without a clock transition. 487 * Switch the port around without a clock transition.
597 */ 488 */
598 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio); 489 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
599 490
600 /* 491 /*
601 * Send out a clock pulse to signal we want the status 492 * Send out a clock pulse to signal we want the status
602 */ 493 */
603 494 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
604 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); 495 sbm_mdio);
605 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio); 496 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
606 497
607 /* 498 /*
608 * If an error occurred, the PHY will signal '1' back 499 * If an error occurred, the PHY will signal '1' back
609 */ 500 */
610 error = __raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN; 501 error = __raw_readq(sbm_mdio) & M_MAC_MDIO_IN;
611 502
612 /* 503 /*
613 * Issue an 'idle' clock pulse, but keep the direction 504 * Issue an 'idle' clock pulse, but keep the direction
614 * the same. 505 * the same.
615 */ 506 */
616 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); 507 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
617 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio); 508 sbm_mdio);
509 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
618 510
619 regval = 0; 511 regval = 0;
620 512
@@ -622,55 +514,60 @@ static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
622 regval <<= 1; 514 regval <<= 1;
623 515
624 if (error == 0) { 516 if (error == 0) {
625 if (__raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN) 517 if (__raw_readq(sbm_mdio) & M_MAC_MDIO_IN)
626 regval |= 1; 518 regval |= 1;
627 } 519 }
628 520
629 __raw_writeq(M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); 521 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
630 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio); 522 sbm_mdio);
523 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
631 } 524 }
632 525
633 /* Switch back to output */ 526 /* Switch back to output */
634 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio); 527 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio);
635 528
636 if (error == 0) 529 if (error == 0)
637 return regval; 530 return regval;
638 return 0; 531 return 0xffff;
639} 532}
640 533
641 534
642/********************************************************************** 535/**********************************************************************
643 * SBMAC_MII_WRITE(s,phyaddr,regidx,regval) 536 * SBMAC_MII_WRITE(bus, phyaddr, regidx, regval)
644 * 537 *
645 * Write a value to a PHY register. 538 * Write a value to a PHY register.
646 * 539 *
647 * Input parameters: 540 * Input parameters:
648 * s - sbmac structure 541 * bus - MDIO bus handle
649 * phyaddr - PHY to use 542 * phyaddr - PHY to use
650 * regidx - register within the PHY 543 * regidx - register within the PHY
651 * regval - data to write to register 544 * regval - data to write to register
652 * 545 *
653 * Return value: 546 * Return value:
654 * nothing 547 * 0 for success
655 ********************************************************************* */ 548 ********************************************************************* */
656 549
657static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx, 550static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
658 unsigned int regval) 551 u16 regval)
659{ 552{
553 struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv;
554 void __iomem *sbm_mdio = sc->sbm_mdio;
660 int mac_mdio_genc; 555 int mac_mdio_genc;
661 556
662 sbmac_mii_sync(s); 557 sbmac_mii_sync(sbm_mdio);
663 558
664 sbmac_mii_senddata(s,MII_COMMAND_START,2); 559 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
665 sbmac_mii_senddata(s,MII_COMMAND_WRITE,2); 560 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_WRITE, 2);
666 sbmac_mii_senddata(s,phyaddr, 5); 561 sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
667 sbmac_mii_senddata(s,regidx, 5); 562 sbmac_mii_senddata(sbm_mdio, regidx, 5);
668 sbmac_mii_senddata(s,MII_COMMAND_ACK,2); 563 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_ACK, 2);
669 sbmac_mii_senddata(s,regval,16); 564 sbmac_mii_senddata(sbm_mdio, regval, 16);
670 565
671 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC; 566 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
672 567
673 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio); 568 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio);
569
570 return 0;
674} 571}
675 572
676 573
@@ -713,27 +610,27 @@ static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan,
713 s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING; 610 s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
714#endif 611#endif
715 612
716 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES))); 613 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BYTES);
717 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS))); 614 __raw_writeq(0, s->sbm_base + R_MAC_RMON_COLLISIONS);
718 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL))); 615 __raw_writeq(0, s->sbm_base + R_MAC_RMON_LATE_COL);
719 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL))); 616 __raw_writeq(0, s->sbm_base + R_MAC_RMON_EX_COL);
720 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR))); 617 __raw_writeq(0, s->sbm_base + R_MAC_RMON_FCS_ERROR);
721 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT))); 618 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_ABORT);
722 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD))); 619 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BAD);
723 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD))); 620 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_GOOD);
724 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT))); 621 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_RUNT);
725 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE))); 622 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_OVERSIZE);
726 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES))); 623 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BYTES);
727 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST))); 624 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_MCAST);
728 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST))); 625 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BCAST);
729 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD))); 626 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BAD);
730 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD))); 627 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_GOOD);
731 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT))); 628 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_RUNT);
732 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE))); 629 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_OVERSIZE);
733 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR))); 630 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_FCS_ERROR);
734 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR))); 631 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_LENGTH_ERROR);
735 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR))); 632 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_CODE_ERROR);
736 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR))); 633 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_ALIGN_ERROR);
737 634
738 /* 635 /*
739 * initialize register pointers 636 * initialize register pointers
@@ -953,7 +850,7 @@ static int sbdma_add_rcvbuffer(struct sbmacdma *d, struct sk_buff *sb)
953 if (sb == NULL) { 850 if (sb == NULL) {
954 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN); 851 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN);
955 if (sb_new == NULL) { 852 if (sb_new == NULL) {
956 printk(KERN_INFO "%s: sk_buff allocation failed\n", 853 pr_info("%s: sk_buff allocation failed\n",
957 d->sbdma_eth->sbm_dev->name); 854 d->sbdma_eth->sbm_dev->name);
958 return -ENOBUFS; 855 return -ENOBUFS;
959 } 856 }
@@ -1472,14 +1369,6 @@ static int sbmac_initctx(struct sbmac_softc *s)
1472 s->sbm_imr = s->sbm_base + R_MAC_INT_MASK; 1369 s->sbm_imr = s->sbm_base + R_MAC_INT_MASK;
1473 s->sbm_mdio = s->sbm_base + R_MAC_MDIO; 1370 s->sbm_mdio = s->sbm_base + R_MAC_MDIO;
1474 1371
1475 s->sbm_phys[0] = 1;
1476 s->sbm_phys[1] = 0;
1477
1478 s->sbm_phy_oldbmsr = 0;
1479 s->sbm_phy_oldanlpar = 0;
1480 s->sbm_phy_oldk1stsr = 0;
1481 s->sbm_phy_oldlinkstat = 0;
1482
1483 /* 1372 /*
1484 * Initialize the DMA channels. Right now, only one per MAC is used 1373 * Initialize the DMA channels. Right now, only one per MAC is used
1485 * Note: Only do this _once_, as it allocates memory from the kernel! 1374 * Note: Only do this _once_, as it allocates memory from the kernel!
@@ -1494,14 +1383,6 @@ static int sbmac_initctx(struct sbmac_softc *s)
1494 1383
1495 s->sbm_state = sbmac_state_off; 1384 s->sbm_state = sbmac_state_off;
1496 1385
1497 /*
1498 * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
1499 */
1500
1501 s->sbm_speed = sbmac_speed_10;
1502 s->sbm_duplex = sbmac_duplex_half;
1503 s->sbm_fc = sbmac_fc_disabled;
1504
1505 return 0; 1386 return 0;
1506} 1387}
1507 1388
@@ -2008,8 +1889,6 @@ static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed)
2008 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN; 1889 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
2009 break; 1890 break;
2010 1891
2011 case sbmac_speed_auto: /* XXX not implemented */
2012 /* fall through */
2013 default: 1892 default:
2014 return 0; 1893 return 0;
2015 } 1894 }
@@ -2083,8 +1962,6 @@ static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
2083 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR; 1962 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
2084 break; 1963 break;
2085 1964
2086 case sbmac_fc_auto: /* XXX not implemented */
2087 /* fall through */
2088 case sbmac_fc_frame: /* not valid in half duplex */ 1965 case sbmac_fc_frame: /* not valid in half duplex */
2089 default: /* invalid selection */ 1966 default: /* invalid selection */
2090 return 0; 1967 return 0;
@@ -2103,15 +1980,12 @@ static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
2103 1980
2104 case sbmac_fc_collision: /* not valid in full duplex */ 1981 case sbmac_fc_collision: /* not valid in full duplex */
2105 case sbmac_fc_carrier: /* not valid in full duplex */ 1982 case sbmac_fc_carrier: /* not valid in full duplex */
2106 case sbmac_fc_auto: /* XXX not implemented */
2107 /* fall through */
2108 default: 1983 default:
2109 return 0; 1984 return 0;
2110 } 1985 }
2111 break; 1986 break;
2112 case sbmac_duplex_auto: 1987 default:
2113 /* XXX not implemented */ 1988 return 0;
2114 break;
2115 } 1989 }
2116 1990
2117 /* 1991 /*
@@ -2390,7 +2264,7 @@ static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2390 if (new_mtu > ENET_PACKET_SIZE) 2264 if (new_mtu > ENET_PACKET_SIZE)
2391 return -EINVAL; 2265 return -EINVAL;
2392 _dev->mtu = new_mtu; 2266 _dev->mtu = new_mtu;
2393 printk(KERN_INFO "changing the mtu to %d\n", new_mtu); 2267 pr_info("changing the mtu to %d\n", new_mtu);
2394 return 0; 2268 return 0;
2395} 2269}
2396 2270
@@ -2406,20 +2280,17 @@ static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2406 * status 2280 * status
2407 ********************************************************************* */ 2281 ********************************************************************* */
2408 2282
2409static int sbmac_init(struct net_device *dev, int idx) 2283static int sbmac_init(struct platform_device *pldev, long long base)
2410{ 2284{
2411 struct sbmac_softc *sc; 2285 struct net_device *dev = pldev->dev.driver_data;
2286 int idx = pldev->id;
2287 struct sbmac_softc *sc = netdev_priv(dev);
2412 unsigned char *eaddr; 2288 unsigned char *eaddr;
2413 uint64_t ea_reg; 2289 uint64_t ea_reg;
2414 int i; 2290 int i;
2415 int err; 2291 int err;
2416 DECLARE_MAC_BUF(mac); 2292 DECLARE_MAC_BUF(mac);
2417 2293
2418 sc = netdev_priv(dev);
2419
2420 /* Determine controller base address */
2421
2422 sc->sbm_base = IOADDR(dev->base_addr);
2423 sc->sbm_dev = dev; 2294 sc->sbm_dev = dev;
2424 sc->sbe_idx = idx; 2295 sc->sbe_idx = idx;
2425 2296
@@ -2476,43 +2347,55 @@ static int sbmac_init(struct net_device *dev, int idx)
2476 dev->poll_controller = sbmac_netpoll; 2347 dev->poll_controller = sbmac_netpoll;
2477#endif 2348#endif
2478 2349
2350 dev->irq = UNIT_INT(idx);
2351
2479 /* This is needed for PASS2 for Rx H/W checksum feature */ 2352 /* This is needed for PASS2 for Rx H/W checksum feature */
2480 sbmac_set_iphdr_offset(sc); 2353 sbmac_set_iphdr_offset(sc);
2481 2354
2482 err = register_netdev(dev); 2355 err = register_netdev(dev);
2483 if (err) 2356 if (err) {
2484 goto out_uninit; 2357 printk(KERN_ERR "%s.%d: unable to register netdev\n",
2485 2358 sbmac_string, idx);
2486 if (sc->rx_hw_checksum == ENABLE) { 2359 sbmac_uninitctx(sc);
2487 printk(KERN_INFO "%s: enabling TCP rcv checksum\n", 2360 return err;
2488 sc->sbm_dev->name);
2489 } 2361 }
2490 2362
2363 pr_info("%s.%d: registered as %s\n", sbmac_string, idx, dev->name);
2364
2365 if (sc->rx_hw_checksum == ENABLE)
2366 pr_info("%s: enabling TCP rcv checksum\n", dev->name);
2367
2491 /* 2368 /*
2492 * Display Ethernet address (this is called during the config 2369 * Display Ethernet address (this is called during the config
2493 * process so we need to finish off the config message that 2370 * process so we need to finish off the config message that
2494 * was being displayed) 2371 * was being displayed)
2495 */ 2372 */
2496 printk(KERN_INFO 2373 pr_info("%s: SiByte Ethernet at 0x%08Lx, address: %s\n",
2497 "%s: SiByte Ethernet at 0x%08lX, address: %s\n", 2374 dev->name, base, print_mac(mac, eaddr));
2498 dev->name, dev->base_addr, print_mac(mac, eaddr));
2499 2375
2500 return 0; 2376 sc->mii_bus.name = sbmac_mdio_string;
2377 sc->mii_bus.id = idx;
2378 sc->mii_bus.priv = sc;
2379 sc->mii_bus.read = sbmac_mii_read;
2380 sc->mii_bus.write = sbmac_mii_write;
2381 sc->mii_bus.irq = sc->phy_irq;
2382 for (i = 0; i < PHY_MAX_ADDR; ++i)
2383 sc->mii_bus.irq[i] = SBMAC_PHY_INT;
2501 2384
2502out_uninit: 2385 sc->mii_bus.dev = &pldev->dev;
2503 sbmac_uninitctx(sc); 2386 dev_set_drvdata(&pldev->dev, &sc->mii_bus);
2504 2387
2505 return err; 2388 return 0;
2506} 2389}
2507 2390
2508 2391
2509static int sbmac_open(struct net_device *dev) 2392static int sbmac_open(struct net_device *dev)
2510{ 2393{
2511 struct sbmac_softc *sc = netdev_priv(dev); 2394 struct sbmac_softc *sc = netdev_priv(dev);
2395 int err;
2512 2396
2513 if (debug > 1) { 2397 if (debug > 1)
2514 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq); 2398 pr_debug("%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2515 }
2516 2399
2517 /* 2400 /*
2518 * map/route interrupt (clear status first, in case something 2401 * map/route interrupt (clear status first, in case something
@@ -2521,25 +2404,35 @@ static int sbmac_open(struct net_device *dev)
2521 */ 2404 */
2522 2405
2523 __raw_readq(sc->sbm_isr); 2406 __raw_readq(sc->sbm_isr);
2524 if (request_irq(dev->irq, &sbmac_intr, IRQF_SHARED, dev->name, dev)) 2407 err = request_irq(dev->irq, &sbmac_intr, IRQF_SHARED, dev->name, dev);
2525 return -EBUSY; 2408 if (err) {
2409 printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name,
2410 dev->irq);
2411 goto out_err;
2412 }
2526 2413
2527 /* 2414 /*
2528 * Probe phy address 2415 * Probe PHY address
2529 */ 2416 */
2530 2417 err = mdiobus_register(&sc->mii_bus);
2531 if(sbmac_mii_probe(dev) == -1) { 2418 if (err) {
2532 printk("%s: failed to probe PHY.\n", dev->name); 2419 printk(KERN_ERR "%s: unable to register MDIO bus\n",
2533 return -EINVAL; 2420 dev->name);
2421 goto out_unirq;
2534 } 2422 }
2535 2423
2536 napi_enable(&sc->napi); 2424 sc->sbm_speed = sbmac_speed_none;
2425 sc->sbm_duplex = sbmac_duplex_none;
2426 sc->sbm_fc = sbmac_fc_none;
2427 sc->sbm_pause = -1;
2428 sc->sbm_link = 0;
2537 2429
2538 /* 2430 /*
2539 * Configure default speed 2431 * Attach to the PHY
2540 */ 2432 */
2541 2433 err = sbmac_mii_probe(dev);
2542 sbmac_mii_poll(sc,noisy_mii); 2434 if (err)
2435 goto out_unregister;
2543 2436
2544 /* 2437 /*
2545 * Turn on the channel 2438 * Turn on the channel
@@ -2547,200 +2440,133 @@ static int sbmac_open(struct net_device *dev)
2547 2440
2548 sbmac_set_channel_state(sc,sbmac_state_on); 2441 sbmac_set_channel_state(sc,sbmac_state_on);
2549 2442
2550 /*
2551 * XXX Station address is in dev->dev_addr
2552 */
2553
2554 if (dev->if_port == 0)
2555 dev->if_port = 0;
2556
2557 netif_start_queue(dev); 2443 netif_start_queue(dev);
2558 2444
2559 sbmac_set_rx_mode(dev); 2445 sbmac_set_rx_mode(dev);
2560 2446
2561 /* Set the timer to check for link beat. */ 2447 phy_start(sc->phy_dev);
2562 init_timer(&sc->sbm_timer); 2448
2563 sc->sbm_timer.expires = jiffies + 2 * HZ/100; 2449 napi_enable(&sc->napi);
2564 sc->sbm_timer.data = (unsigned long)dev;
2565 sc->sbm_timer.function = &sbmac_timer;
2566 add_timer(&sc->sbm_timer);
2567 2450
2568 return 0; 2451 return 0;
2452
2453out_unregister:
2454 mdiobus_unregister(&sc->mii_bus);
2455
2456out_unirq:
2457 free_irq(dev->irq, dev);
2458
2459out_err:
2460 return err;
2569} 2461}
2570 2462
2571static int sbmac_mii_probe(struct net_device *dev) 2463static int sbmac_mii_probe(struct net_device *dev)
2572{ 2464{
2465 struct sbmac_softc *sc = netdev_priv(dev);
2466 struct phy_device *phy_dev;
2573 int i; 2467 int i;
2574 struct sbmac_softc *s = netdev_priv(dev);
2575 u16 bmsr, id1, id2;
2576 u32 vendor, device;
2577
2578 for (i=1; i<31; i++) {
2579 bmsr = sbmac_mii_read(s, i, MII_BMSR);
2580 if (bmsr != 0) {
2581 s->sbm_phys[0] = i;
2582 id1 = sbmac_mii_read(s, i, MII_PHYIDR1);
2583 id2 = sbmac_mii_read(s, i, MII_PHYIDR2);
2584 vendor = ((u32)id1 << 6) | ((id2 >> 10) & 0x3f);
2585 device = (id2 >> 4) & 0x3f;
2586
2587 printk(KERN_INFO "%s: found phy %d, vendor %06x part %02x\n",
2588 dev->name, i, vendor, device);
2589 return i;
2590 }
2591 }
2592 return -1;
2593}
2594
2595
2596static int sbmac_mii_poll(struct sbmac_softc *s,int noisy)
2597{
2598 int bmsr,bmcr,k1stsr,anlpar;
2599 int chg;
2600 char buffer[100];
2601 char *p = buffer;
2602
2603 /* Read the mode status and mode control registers. */
2604 bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR);
2605 bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR);
2606
2607 /* get the link partner status */
2608 anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR);
2609 2468
2610 /* if supported, read the 1000baseT register */ 2469 for (i = 0; i < PHY_MAX_ADDR; i++) {
2611 if (bmsr & BMSR_1000BT_XSR) { 2470 phy_dev = sc->mii_bus.phy_map[i];
2612 k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR); 2471 if (phy_dev)
2613 } 2472 break;
2614 else {
2615 k1stsr = 0;
2616 }
2617
2618 chg = 0;
2619
2620 if ((bmsr & BMSR_LINKSTAT) == 0) {
2621 /*
2622 * If link status is down, clear out old info so that when
2623 * it comes back up it will force us to reconfigure speed
2624 */
2625 s->sbm_phy_oldbmsr = 0;
2626 s->sbm_phy_oldanlpar = 0;
2627 s->sbm_phy_oldk1stsr = 0;
2628 return 0;
2629 } 2473 }
2630 2474 if (!phy_dev) {
2631 if ((s->sbm_phy_oldbmsr != bmsr) || 2475 printk(KERN_ERR "%s: no PHY found\n", dev->name);
2632 (s->sbm_phy_oldanlpar != anlpar) || 2476 return -ENXIO;
2633 (s->sbm_phy_oldk1stsr != k1stsr)) {
2634 if (debug > 1) {
2635 printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x k1stsr:%x/%x\n",
2636 s->sbm_dev->name,
2637 s->sbm_phy_oldbmsr,bmsr,
2638 s->sbm_phy_oldanlpar,anlpar,
2639 s->sbm_phy_oldk1stsr,k1stsr);
2640 }
2641 s->sbm_phy_oldbmsr = bmsr;
2642 s->sbm_phy_oldanlpar = anlpar;
2643 s->sbm_phy_oldk1stsr = k1stsr;
2644 chg = 1;
2645 } 2477 }
2646 2478
2647 if (chg == 0) 2479 phy_dev = phy_connect(dev, phy_dev->dev.bus_id, &sbmac_mii_poll, 0,
2648 return 0; 2480 PHY_INTERFACE_MODE_GMII);
2649 2481 if (IS_ERR(phy_dev)) {
2650 p += sprintf(p,"Link speed: "); 2482 printk(KERN_ERR "%s: could not attach to PHY\n", dev->name);
2651 2483 return PTR_ERR(phy_dev);
2652 if (k1stsr & K1STSR_LP1KFD) {
2653 s->sbm_speed = sbmac_speed_1000;
2654 s->sbm_duplex = sbmac_duplex_full;
2655 s->sbm_fc = sbmac_fc_frame;
2656 p += sprintf(p,"1000BaseT FDX");
2657 }
2658 else if (k1stsr & K1STSR_LP1KHD) {
2659 s->sbm_speed = sbmac_speed_1000;
2660 s->sbm_duplex = sbmac_duplex_half;
2661 s->sbm_fc = sbmac_fc_disabled;
2662 p += sprintf(p,"1000BaseT HDX");
2663 }
2664 else if (anlpar & ANLPAR_TXFD) {
2665 s->sbm_speed = sbmac_speed_100;
2666 s->sbm_duplex = sbmac_duplex_full;
2667 s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled;
2668 p += sprintf(p,"100BaseT FDX");
2669 }
2670 else if (anlpar & ANLPAR_TXHD) {
2671 s->sbm_speed = sbmac_speed_100;
2672 s->sbm_duplex = sbmac_duplex_half;
2673 s->sbm_fc = sbmac_fc_disabled;
2674 p += sprintf(p,"100BaseT HDX");
2675 }
2676 else if (anlpar & ANLPAR_10FD) {
2677 s->sbm_speed = sbmac_speed_10;
2678 s->sbm_duplex = sbmac_duplex_full;
2679 s->sbm_fc = sbmac_fc_frame;
2680 p += sprintf(p,"10BaseT FDX");
2681 }
2682 else if (anlpar & ANLPAR_10HD) {
2683 s->sbm_speed = sbmac_speed_10;
2684 s->sbm_duplex = sbmac_duplex_half;
2685 s->sbm_fc = sbmac_fc_collision;
2686 p += sprintf(p,"10BaseT HDX");
2687 }
2688 else {
2689 p += sprintf(p,"Unknown");
2690 } 2484 }
2691 2485
2692 if (noisy) { 2486 /* Remove any features not supported by the controller */
2693 printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer); 2487 phy_dev->supported &= SUPPORTED_10baseT_Half |
2694 } 2488 SUPPORTED_10baseT_Full |
2489 SUPPORTED_100baseT_Half |
2490 SUPPORTED_100baseT_Full |
2491 SUPPORTED_1000baseT_Half |
2492 SUPPORTED_1000baseT_Full |
2493 SUPPORTED_Autoneg |
2494 SUPPORTED_MII |
2495 SUPPORTED_Pause |
2496 SUPPORTED_Asym_Pause;
2497 phy_dev->advertising = phy_dev->supported;
2498
2499 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2500 dev->name, phy_dev->drv->name,
2501 phy_dev->dev.bus_id, phy_dev->irq);
2502
2503 sc->phy_dev = phy_dev;
2695 2504
2696 return 1; 2505 return 0;
2697} 2506}
2698 2507
2699 2508
2700static void sbmac_timer(unsigned long data) 2509static void sbmac_mii_poll(struct net_device *dev)
2701{ 2510{
2702 struct net_device *dev = (struct net_device *)data;
2703 struct sbmac_softc *sc = netdev_priv(dev); 2511 struct sbmac_softc *sc = netdev_priv(dev);
2704 int next_tick = HZ; 2512 struct phy_device *phy_dev = sc->phy_dev;
2705 int mii_status; 2513 unsigned long flags;
2514 enum sbmac_fc fc;
2515 int link_chg, speed_chg, duplex_chg, pause_chg, fc_chg;
2516
2517 link_chg = (sc->sbm_link != phy_dev->link);
2518 speed_chg = (sc->sbm_speed != phy_dev->speed);
2519 duplex_chg = (sc->sbm_duplex != phy_dev->duplex);
2520 pause_chg = (sc->sbm_pause != phy_dev->pause);
2521
2522 if (!link_chg && !speed_chg && !duplex_chg && !pause_chg)
2523 return; /* Hmmm... */
2524
2525 if (!phy_dev->link) {
2526 if (link_chg) {
2527 sc->sbm_link = phy_dev->link;
2528 sc->sbm_speed = sbmac_speed_none;
2529 sc->sbm_duplex = sbmac_duplex_none;
2530 sc->sbm_fc = sbmac_fc_disabled;
2531 sc->sbm_pause = -1;
2532 pr_info("%s: link unavailable\n", dev->name);
2533 }
2534 return;
2535 }
2706 2536
2707 spin_lock_irq (&sc->sbm_lock); 2537 if (phy_dev->duplex == DUPLEX_FULL) {
2538 if (phy_dev->pause)
2539 fc = sbmac_fc_frame;
2540 else
2541 fc = sbmac_fc_disabled;
2542 } else
2543 fc = sbmac_fc_collision;
2544 fc_chg = (sc->sbm_fc != fc);
2708 2545
2709 /* make IFF_RUNNING follow the MII status bit "Link established" */ 2546 pr_info("%s: link available: %dbase-%cD\n", dev->name, phy_dev->speed,
2710 mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR); 2547 phy_dev->duplex == DUPLEX_FULL ? 'F' : 'H');
2711 2548
2712 if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) { 2549 spin_lock_irqsave(&sc->sbm_lock, flags);
2713 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT;
2714 if (mii_status & BMSR_LINKSTAT) {
2715 netif_carrier_on(dev);
2716 }
2717 else {
2718 netif_carrier_off(dev);
2719 }
2720 }
2721 2550
2722 /* 2551 sc->sbm_speed = phy_dev->speed;
2723 * Poll the PHY to see what speed we should be running at 2552 sc->sbm_duplex = phy_dev->duplex;
2724 */ 2553 sc->sbm_fc = fc;
2554 sc->sbm_pause = phy_dev->pause;
2555 sc->sbm_link = phy_dev->link;
2725 2556
2726 if (sbmac_mii_poll(sc,noisy_mii)) { 2557 if ((speed_chg || duplex_chg || fc_chg) &&
2727 if (sc->sbm_state != sbmac_state_off) { 2558 sc->sbm_state != sbmac_state_off) {
2728 /* 2559 /*
2729 * something changed, restart the channel 2560 * something changed, restart the channel
2730 */ 2561 */
2731 if (debug > 1) { 2562 if (debug > 1)
2732 printk("%s: restarting channel because speed changed\n", 2563 pr_debug("%s: restarting channel "
2733 sc->sbm_dev->name); 2564 "because PHY state changed\n", dev->name);
2734 } 2565 sbmac_channel_stop(sc);
2735 sbmac_channel_stop(sc); 2566 sbmac_channel_start(sc);
2736 sbmac_channel_start(sc);
2737 }
2738 } 2567 }
2739 2568
2740 spin_unlock_irq (&sc->sbm_lock); 2569 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2741
2742 sc->sbm_timer.expires = jiffies + next_tick;
2743 add_timer(&sc->sbm_timer);
2744} 2570}
2745 2571
2746 2572
@@ -2793,64 +2619,34 @@ static void sbmac_set_rx_mode(struct net_device *dev)
2793static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2619static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2794{ 2620{
2795 struct sbmac_softc *sc = netdev_priv(dev); 2621 struct sbmac_softc *sc = netdev_priv(dev);
2796 u16 *data = (u16 *)&rq->ifr_ifru;
2797 unsigned long flags;
2798 int retval;
2799 2622
2800 spin_lock_irqsave(&sc->sbm_lock, flags); 2623 if (!netif_running(dev) || !sc->phy_dev)
2801 retval = 0; 2624 return -EINVAL;
2802
2803 switch(cmd) {
2804 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
2805 data[0] = sc->sbm_phys[0] & 0x1f;
2806 /* Fall Through */
2807 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
2808 data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f);
2809 break;
2810 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
2811 if (!capable(CAP_NET_ADMIN)) {
2812 retval = -EPERM;
2813 break;
2814 }
2815 if (debug > 1) {
2816 printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name,
2817 data[0],data[1],data[2]);
2818 }
2819 sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]);
2820 break;
2821 default:
2822 retval = -EOPNOTSUPP;
2823 }
2824 2625
2825 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2626 return phy_mii_ioctl(sc->phy_dev, if_mii(rq), cmd);
2826 return retval;
2827} 2627}
2828 2628
2829static int sbmac_close(struct net_device *dev) 2629static int sbmac_close(struct net_device *dev)
2830{ 2630{
2831 struct sbmac_softc *sc = netdev_priv(dev); 2631 struct sbmac_softc *sc = netdev_priv(dev);
2832 unsigned long flags;
2833 int irq;
2834 2632
2835 napi_disable(&sc->napi); 2633 napi_disable(&sc->napi);
2836 2634
2837 sbmac_set_channel_state(sc,sbmac_state_off); 2635 phy_stop(sc->phy_dev);
2838
2839 del_timer_sync(&sc->sbm_timer);
2840 2636
2841 spin_lock_irqsave(&sc->sbm_lock, flags); 2637 sbmac_set_channel_state(sc, sbmac_state_off);
2842 2638
2843 netif_stop_queue(dev); 2639 netif_stop_queue(dev);
2844 2640
2845 if (debug > 1) { 2641 if (debug > 1)
2846 printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name); 2642 pr_debug("%s: Shutting down ethercard\n", dev->name);
2847 }
2848 2643
2849 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2644 phy_disconnect(sc->phy_dev);
2645 sc->phy_dev = NULL;
2646
2647 mdiobus_unregister(&sc->mii_bus);
2850 2648
2851 irq = dev->irq; 2649 free_irq(dev->irq, dev);
2852 synchronize_irq(irq);
2853 free_irq(irq, dev);
2854 2650
2855 sbdma_emptyring(&(sc->sbm_txdma)); 2651 sbdma_emptyring(&(sc->sbm_txdma));
2856 sbdma_emptyring(&(sc->sbm_rxdma)); 2652 sbdma_emptyring(&(sc->sbm_rxdma));
@@ -2883,54 +2679,195 @@ static int sbmac_poll(struct napi_struct *napi, int budget)
2883 return work_done; 2679 return work_done;
2884} 2680}
2885 2681
2682
2683static int __init sbmac_probe(struct platform_device *pldev)
2684{
2685 struct net_device *dev;
2686 struct sbmac_softc *sc;
2687 void __iomem *sbm_base;
2688 struct resource *res;
2689 u64 sbmac_orig_hwaddr;
2690 int err;
2691
2692 res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
2693 BUG_ON(!res);
2694 sbm_base = ioremap_nocache(res->start, res->end - res->start + 1);
2695 if (!sbm_base) {
2696 printk(KERN_ERR "%s: unable to map device registers\n",
2697 pldev->dev.bus_id);
2698 err = -ENOMEM;
2699 goto out_out;
2700 }
2701
2702 /*
2703 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2704 * value for us by the firmware if we're going to use this MAC.
2705 * If we find a zero, skip this MAC.
2706 */
2707 sbmac_orig_hwaddr = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR);
2708 pr_debug("%s: %sconfiguring MAC at 0x%08Lx\n", pldev->dev.bus_id,
2709 sbmac_orig_hwaddr ? "" : "not ", (long long)res->start);
2710 if (sbmac_orig_hwaddr == 0) {
2711 err = 0;
2712 goto out_unmap;
2713 }
2714
2715 /*
2716 * Okay, cool. Initialize this MAC.
2717 */
2718 dev = alloc_etherdev(sizeof(struct sbmac_softc));
2719 if (!dev) {
2720 printk(KERN_ERR "%s: unable to allocate etherdev\n",
2721 pldev->dev.bus_id);
2722 err = -ENOMEM;
2723 goto out_unmap;
2724 }
2725
2726 pldev->dev.driver_data = dev;
2727 SET_NETDEV_DEV(dev, &pldev->dev);
2728
2729 sc = netdev_priv(dev);
2730 sc->sbm_base = sbm_base;
2731
2732 err = sbmac_init(pldev, res->start);
2733 if (err)
2734 goto out_kfree;
2735
2736 return 0;
2737
2738out_kfree:
2739 free_netdev(dev);
2740 __raw_writeq(sbmac_orig_hwaddr, sbm_base + R_MAC_ETHERNET_ADDR);
2741
2742out_unmap:
2743 iounmap(sbm_base);
2744
2745out_out:
2746 return err;
2747}
2748
2749static int __exit sbmac_remove(struct platform_device *pldev)
2750{
2751 struct net_device *dev = pldev->dev.driver_data;
2752 struct sbmac_softc *sc = netdev_priv(dev);
2753
2754 unregister_netdev(dev);
2755 sbmac_uninitctx(sc);
2756 iounmap(sc->sbm_base);
2757 free_netdev(dev);
2758
2759 return 0;
2760}
2761
2762
2763static struct platform_device **sbmac_pldev;
2764static int sbmac_max_units;
2765
2886#if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR) 2766#if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2887static void 2767static void __init sbmac_setup_hwaddr(int idx, char *addr)
2888sbmac_setup_hwaddr(int chan,char *addr)
2889{ 2768{
2769 void __iomem *sbm_base;
2770 unsigned long start, end;
2890 uint8_t eaddr[6]; 2771 uint8_t eaddr[6];
2891 uint64_t val; 2772 uint64_t val;
2892 unsigned long port;
2893 2773
2894 port = A_MAC_CHANNEL_BASE(chan); 2774 if (idx >= sbmac_max_units)
2895 sbmac_parse_hwaddr(addr,eaddr); 2775 return;
2776
2777 start = A_MAC_CHANNEL_BASE(idx);
2778 end = A_MAC_CHANNEL_BASE(idx + 1) - 1;
2779
2780 sbm_base = ioremap_nocache(start, end - start + 1);
2781 if (!sbm_base) {
2782 printk(KERN_ERR "%s: unable to map device registers\n",
2783 sbmac_string);
2784 return;
2785 }
2786
2787 sbmac_parse_hwaddr(addr, eaddr);
2896 val = sbmac_addr2reg(eaddr); 2788 val = sbmac_addr2reg(eaddr);
2897 __raw_writeq(val, IOADDR(port+R_MAC_ETHERNET_ADDR)); 2789 __raw_writeq(val, sbm_base + R_MAC_ETHERNET_ADDR);
2898 val = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR)); 2790 val = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR);
2791
2792 iounmap(sbm_base);
2899} 2793}
2900#endif 2794#endif
2901 2795
2902static struct net_device *dev_sbmac[MAX_UNITS]; 2796static int __init sbmac_platform_probe_one(int idx)
2797{
2798 struct platform_device *pldev;
2799 struct {
2800 struct resource r;
2801 char name[strlen(sbmac_pretty) + 4];
2802 } *res;
2803 int err;
2804
2805 res = kzalloc(sizeof(*res), GFP_KERNEL);
2806 if (!res) {
2807 printk(KERN_ERR "%s.%d: unable to allocate memory\n",
2808 sbmac_string, idx);
2809 err = -ENOMEM;
2810 goto out_err;
2811 }
2812
2813 /*
2814 * This is the base address of the MAC.
2815 */
2816 snprintf(res->name, sizeof(res->name), "%s %d", sbmac_pretty, idx);
2817 res->r.name = res->name;
2818 res->r.flags = IORESOURCE_MEM;
2819 res->r.start = A_MAC_CHANNEL_BASE(idx);
2820 res->r.end = A_MAC_CHANNEL_BASE(idx + 1) - 1;
2821
2822 pldev = platform_device_register_simple(sbmac_string, idx, &res->r, 1);
2823 if (IS_ERR(pldev)) {
2824 printk(KERN_ERR "%s.%d: unable to register platform device\n",
2825 sbmac_string, idx);
2826 err = PTR_ERR(pldev);
2827 goto out_kfree;
2828 }
2829
2830 if (!pldev->dev.driver) {
2831 err = 0; /* No hardware at this address. */
2832 goto out_unregister;
2833 }
2834
2835 sbmac_pldev[idx] = pldev;
2836 return 0;
2837
2838out_unregister:
2839 platform_device_unregister(pldev);
2903 2840
2904static int __init 2841out_kfree:
2905sbmac_init_module(void) 2842 kfree(res);
2843
2844out_err:
2845 return err;
2846}
2847
2848static void __init sbmac_platform_probe(void)
2906{ 2849{
2907 int idx; 2850 int i;
2908 struct net_device *dev;
2909 unsigned long port;
2910 int chip_max_units;
2911 2851
2912 /* Set the number of available units based on the SOC type. */ 2852 /* Set the number of available units based on the SOC type. */
2913 switch (soc_type) { 2853 switch (soc_type) {
2914 case K_SYS_SOC_TYPE_BCM1250: 2854 case K_SYS_SOC_TYPE_BCM1250:
2915 case K_SYS_SOC_TYPE_BCM1250_ALT: 2855 case K_SYS_SOC_TYPE_BCM1250_ALT:
2916 chip_max_units = 3; 2856 sbmac_max_units = 3;
2917 break; 2857 break;
2918 case K_SYS_SOC_TYPE_BCM1120: 2858 case K_SYS_SOC_TYPE_BCM1120:
2919 case K_SYS_SOC_TYPE_BCM1125: 2859 case K_SYS_SOC_TYPE_BCM1125:
2920 case K_SYS_SOC_TYPE_BCM1125H: 2860 case K_SYS_SOC_TYPE_BCM1125H:
2921 case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */ 2861 case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
2922 chip_max_units = 2; 2862 sbmac_max_units = 2;
2923 break; 2863 break;
2924 case K_SYS_SOC_TYPE_BCM1x55: 2864 case K_SYS_SOC_TYPE_BCM1x55:
2925 case K_SYS_SOC_TYPE_BCM1x80: 2865 case K_SYS_SOC_TYPE_BCM1x80:
2926 chip_max_units = 4; 2866 sbmac_max_units = 4;
2927 break; 2867 break;
2928 default: 2868 default:
2929 chip_max_units = 0; 2869 return; /* none */
2930 break;
2931 } 2870 }
2932 if (chip_max_units > MAX_UNITS)
2933 chip_max_units = MAX_UNITS;
2934 2871
2935 /* 2872 /*
2936 * For bringup when not using the firmware, we can pre-fill 2873 * For bringup when not using the firmware, we can pre-fill
@@ -2938,89 +2875,71 @@ sbmac_init_module(void)
2938 * specified in this file (or maybe from the config file?) 2875 * specified in this file (or maybe from the config file?)
2939 */ 2876 */
2940#ifdef SBMAC_ETH0_HWADDR 2877#ifdef SBMAC_ETH0_HWADDR
2941 if (chip_max_units > 0) 2878 sbmac_setup_hwaddr(0, SBMAC_ETH0_HWADDR);
2942 sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR);
2943#endif 2879#endif
2944#ifdef SBMAC_ETH1_HWADDR 2880#ifdef SBMAC_ETH1_HWADDR
2945 if (chip_max_units > 1) 2881 sbmac_setup_hwaddr(1, SBMAC_ETH1_HWADDR);
2946 sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR);
2947#endif 2882#endif
2948#ifdef SBMAC_ETH2_HWADDR 2883#ifdef SBMAC_ETH2_HWADDR
2949 if (chip_max_units > 2) 2884 sbmac_setup_hwaddr(2, SBMAC_ETH2_HWADDR);
2950 sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR);
2951#endif 2885#endif
2952#ifdef SBMAC_ETH3_HWADDR 2886#ifdef SBMAC_ETH3_HWADDR
2953 if (chip_max_units > 3) 2887 sbmac_setup_hwaddr(3, SBMAC_ETH3_HWADDR);
2954 sbmac_setup_hwaddr(3,SBMAC_ETH3_HWADDR);
2955#endif 2888#endif
2956 2889
2890 sbmac_pldev = kcalloc(sbmac_max_units, sizeof(*sbmac_pldev),
2891 GFP_KERNEL);
2892 if (!sbmac_pldev) {
2893 printk(KERN_ERR "%s: unable to allocate memory\n",
2894 sbmac_string);
2895 return;
2896 }
2897
2957 /* 2898 /*
2958 * Walk through the Ethernet controllers and find 2899 * Walk through the Ethernet controllers and find
2959 * those who have their MAC addresses set. 2900 * those who have their MAC addresses set.
2960 */ 2901 */
2961 for (idx = 0; idx < chip_max_units; idx++) { 2902 for (i = 0; i < sbmac_max_units; i++)
2903 if (sbmac_platform_probe_one(i))
2904 break;
2905}
2962 2906
2963 /*
2964 * This is the base address of the MAC.
2965 */
2966 2907
2967 port = A_MAC_CHANNEL_BASE(idx); 2908static void __exit sbmac_platform_cleanup(void)
2909{
2910 int i;
2968 2911
2969 /* 2912 for (i = 0; i < sbmac_max_units; i++)
2970 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero 2913 platform_device_unregister(sbmac_pldev[i]);
2971 * value for us by the firmware if we are going to use this MAC. 2914 kfree(sbmac_pldev);
2972 * If we find a zero, skip this MAC. 2915}
2973 */
2974 2916
2975 sbmac_orig_hwaddr[idx] = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2976 if (sbmac_orig_hwaddr[idx] == 0) {
2977 printk(KERN_DEBUG "sbmac: not configuring MAC at "
2978 "%lx\n", port);
2979 continue;
2980 }
2981 2917
2982 /* 2918static struct platform_driver sbmac_driver = {
2983 * Okay, cool. Initialize this MAC. 2919 .probe = sbmac_probe,
2984 */ 2920 .remove = __exit_p(sbmac_remove),
2921 .driver = {
2922 .name = sbmac_string,
2923 },
2924};
2985 2925
2986 dev = alloc_etherdev(sizeof(struct sbmac_softc)); 2926static int __init sbmac_init_module(void)
2987 if (!dev) 2927{
2988 return -ENOMEM; 2928 int err;
2989 2929
2990 printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port); 2930 err = platform_driver_register(&sbmac_driver);
2931 if (err)
2932 return err;
2991 2933
2992 dev->irq = UNIT_INT(idx); 2934 sbmac_platform_probe();
2993 dev->base_addr = port;
2994 dev->mem_end = 0;
2995 if (sbmac_init(dev, idx)) {
2996 port = A_MAC_CHANNEL_BASE(idx);
2997 __raw_writeq(sbmac_orig_hwaddr[idx], IOADDR(port+R_MAC_ETHERNET_ADDR));
2998 free_netdev(dev);
2999 continue;
3000 }
3001 dev_sbmac[idx] = dev;
3002 }
3003 return 0;
3004}
3005 2935
2936 return err;
2937}
3006 2938
3007static void __exit 2939static void __exit sbmac_cleanup_module(void)
3008sbmac_cleanup_module(void)
3009{ 2940{
3010 struct net_device *dev; 2941 sbmac_platform_cleanup();
3011 int idx; 2942 platform_driver_unregister(&sbmac_driver);
3012
3013 for (idx = 0; idx < MAX_UNITS; idx++) {
3014 struct sbmac_softc *sc;
3015 dev = dev_sbmac[idx];
3016 if (!dev)
3017 continue;
3018
3019 sc = netdev_priv(dev);
3020 unregister_netdev(dev);
3021 sbmac_uninitctx(sc);
3022 free_netdev(dev);
3023 }
3024} 2943}
3025 2944
3026module_init(sbmac_init_module); 2945module_init(sbmac_init_module);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 05:04:21 -0500