1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/net/saa9730.h b/drivers/net/saa9730.h
index a7e9d29a86a7..f656f2f40bb8 100644
--- a/drivers/net/saa9730.h
+++ b/drivers/net/saa9730.h
@@ -34,9 +34,9 @@
 /* TX and RX packet size: fixed to 2048 bytes, according to HW requirements. */
 #define LAN_SAA9730_PACKET_SIZE                       2048
-/* 
+/*
- * Number of TX buffers = number of RX buffers = 2, which is fixed according 
+ * Number of TX buffers = number of RX buffers = 2, which is fixed according
- * to HW requirements. 
+ * to HW requirements.
 */
 #define LAN_SAA9730_BUFFERS                           2
@@ -47,10 +47,10 @@
 #define LAN_SAA9730_TXM_Q_SIZE                        15
 /*
- * We get an interrupt for each LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD 
+ * We get an interrupt for each LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD
- * packets received. 
+ * packets received.
 * If however we receive less than  LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD
- * packets, the hardware can timeout after a certain time and still tell 
+ * packets, the hardware can timeout after a certain time and still tell
 * us packets have arrived.
 * The timeout value in unit of 32 PCI clocks (33Mhz).
 * The value 200 approximates 0.0002 seconds.
@@ -79,8 +79,8 @@
 #define MACCM_10MB                      1
 #define MACCM_MII                       2
-/* 
+/*
- * PHY definitions for Basic registers of QS6612 (used on MIPS ATLAS board) 
+ * PHY definitions for Basic registers of QS6612 (used on MIPS ATLAS board)
 */
 #define PHY_CONTROL                     0x0
 #define PHY_STATUS                      0x1

diff --git a/drivers/net/saa9730.h b/drivers/net/saa9730.h index a7e9d29a86a7..f656f2f40bb8 100644 --- a/drivers/net/saa9730.h +++ b/drivers/net/saa9730.h
@@ -34,9 +34,9 @@
34	/* TX and RX packet size: fixed to 2048 bytes, according to HW requirements. */	34	/* TX and RX packet size: fixed to 2048 bytes, according to HW requirements. */
35	#define LAN_SAA9730_PACKET_SIZE 2048	35	#define LAN_SAA9730_PACKET_SIZE 2048
36		36
37	/*	37	/*
38	* Number of TX buffers = number of RX buffers = 2, which is fixed according	38	* Number of TX buffers = number of RX buffers = 2, which is fixed according
39	* to HW requirements.	39	* to HW requirements.
40	*/	40	*/
41	#define LAN_SAA9730_BUFFERS 2	41	#define LAN_SAA9730_BUFFERS 2
42		42
@@ -47,10 +47,10 @@
47	#define LAN_SAA9730_TXM_Q_SIZE 15	47	#define LAN_SAA9730_TXM_Q_SIZE 15
48		48
49	/*	49	/*
50	* We get an interrupt for each LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD	50	* We get an interrupt for each LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD
51	* packets received.	51	* packets received.
52	* If however we receive less than LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD	52	* If however we receive less than LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD
53	* packets, the hardware can timeout after a certain time and still tell	53	* packets, the hardware can timeout after a certain time and still tell
54	* us packets have arrived.	54	* us packets have arrived.
55	* The timeout value in unit of 32 PCI clocks (33Mhz).	55	* The timeout value in unit of 32 PCI clocks (33Mhz).
56	* The value 200 approximates 0.0002 seconds.	56	* The value 200 approximates 0.0002 seconds.
@@ -79,8 +79,8 @@
79	#define MACCM_10MB 1	79	#define MACCM_10MB 1
80	#define MACCM_MII 2	80	#define MACCM_MII 2
81		81
82	/*	82	/*
83	* PHY definitions for Basic registers of QS6612 (used on MIPS ATLAS board)	83	* PHY definitions for Basic registers of QS6612 (used on MIPS ATLAS board)
84	*/	84	*/
85	#define PHY_CONTROL 0x0	85	#define PHY_CONTROL 0x0
86	#define PHY_STATUS 0x1	86	#define PHY_STATUS 0x1