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-rw-r--r--drivers/net/s2io.h360
1 files changed, 247 insertions, 113 deletions
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h
index 1711c8c3dc99..bc64d967f080 100644
--- a/drivers/net/s2io.h
+++ b/drivers/net/s2io.h
@@ -31,6 +31,9 @@
31#define SUCCESS 0 31#define SUCCESS 0
32#define FAILURE -1 32#define FAILURE -1
33 33
34/* Maximum time to flicker LED when asked to identify NIC using ethtool */
35#define MAX_FLICKER_TIME 60000 /* 60 Secs */
36
34/* Maximum outstanding splits to be configured into xena. */ 37/* Maximum outstanding splits to be configured into xena. */
35typedef enum xena_max_outstanding_splits { 38typedef enum xena_max_outstanding_splits {
36 XENA_ONE_SPLIT_TRANSACTION = 0, 39 XENA_ONE_SPLIT_TRANSACTION = 0,
@@ -45,10 +48,10 @@ typedef enum xena_max_outstanding_splits {
45#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4) 48#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
46 49
47/* OS concerned variables and constants */ 50/* OS concerned variables and constants */
48#define WATCH_DOG_TIMEOUT 5*HZ 51#define WATCH_DOG_TIMEOUT 15*HZ
49#define EFILL 0x1234 52#define EFILL 0x1234
50#define ALIGN_SIZE 127 53#define ALIGN_SIZE 127
51#define PCIX_COMMAND_REGISTER 0x62 54#define PCIX_COMMAND_REGISTER 0x62
52 55
53/* 56/*
54 * Debug related variables. 57 * Debug related variables.
@@ -61,7 +64,7 @@ typedef enum xena_max_outstanding_splits {
61#define INTR_DBG 4 64#define INTR_DBG 4
62 65
63/* Global variable that defines the present debug level of the driver. */ 66/* Global variable that defines the present debug level of the driver. */
64static int debug_level = ERR_DBG; /* Default level. */ 67int debug_level = ERR_DBG; /* Default level. */
65 68
66/* DEBUG message print. */ 69/* DEBUG message print. */
67#define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args) 70#define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
@@ -71,6 +74,12 @@ static int debug_level = ERR_DBG; /* Default level. */
71#define L4_CKSUM_OK 0xFFFF 74#define L4_CKSUM_OK 0xFFFF
72#define S2IO_JUMBO_SIZE 9600 75#define S2IO_JUMBO_SIZE 9600
73 76
77/* Driver statistics maintained by driver */
78typedef struct {
79 unsigned long long single_ecc_errs;
80 unsigned long long double_ecc_errs;
81} swStat_t;
82
74/* The statistics block of Xena */ 83/* The statistics block of Xena */
75typedef struct stat_block { 84typedef struct stat_block {
76/* Tx MAC statistics counters. */ 85/* Tx MAC statistics counters. */
@@ -186,12 +195,90 @@ typedef struct stat_block {
186 u32 rxd_rd_cnt; 195 u32 rxd_rd_cnt;
187 u32 rxf_wr_cnt; 196 u32 rxf_wr_cnt;
188 u32 txf_rd_cnt; 197 u32 txf_rd_cnt;
198
199/* Tx MAC statistics overflow counters. */
200 u32 tmac_data_octets_oflow;
201 u32 tmac_frms_oflow;
202 u32 tmac_bcst_frms_oflow;
203 u32 tmac_mcst_frms_oflow;
204 u32 tmac_ucst_frms_oflow;
205 u32 tmac_ttl_octets_oflow;
206 u32 tmac_any_err_frms_oflow;
207 u32 tmac_nucst_frms_oflow;
208 u64 tmac_vlan_frms;
209 u32 tmac_drop_ip_oflow;
210 u32 tmac_vld_ip_oflow;
211 u32 tmac_rst_tcp_oflow;
212 u32 tmac_icmp_oflow;
213 u32 tpa_unknown_protocol;
214 u32 tmac_udp_oflow;
215 u32 reserved_10;
216 u32 tpa_parse_failure;
217
218/* Rx MAC Statistics overflow counters. */
219 u32 rmac_data_octets_oflow;
220 u32 rmac_vld_frms_oflow;
221 u32 rmac_vld_bcst_frms_oflow;
222 u32 rmac_vld_mcst_frms_oflow;
223 u32 rmac_accepted_ucst_frms_oflow;
224 u32 rmac_ttl_octets_oflow;
225 u32 rmac_discarded_frms_oflow;
226 u32 rmac_accepted_nucst_frms_oflow;
227 u32 rmac_usized_frms_oflow;
228 u32 rmac_drop_events_oflow;
229 u32 rmac_frag_frms_oflow;
230 u32 rmac_osized_frms_oflow;
231 u32 rmac_ip_oflow;
232 u32 rmac_jabber_frms_oflow;
233 u32 rmac_icmp_oflow;
234 u32 rmac_drop_ip_oflow;
235 u32 rmac_err_drp_udp_oflow;
236 u32 rmac_udp_oflow;
237 u32 reserved_11;
238 u32 rmac_pause_cnt_oflow;
239 u64 rmac_ttl_1519_4095_frms;
240 u64 rmac_ttl_4096_8191_frms;
241 u64 rmac_ttl_8192_max_frms;
242 u64 rmac_ttl_gt_max_frms;
243 u64 rmac_osized_alt_frms;
244 u64 rmac_jabber_alt_frms;
245 u64 rmac_gt_max_alt_frms;
246 u64 rmac_vlan_frms;
247 u32 rmac_len_discard;
248 u32 rmac_fcs_discard;
249 u32 rmac_pf_discard;
250 u32 rmac_da_discard;
251 u32 rmac_red_discard;
252 u32 rmac_rts_discard;
253 u32 reserved_12;
254 u32 rmac_ingm_full_discard;
255 u32 reserved_13;
256 u32 rmac_accepted_ip_oflow;
257 u32 reserved_14;
258 u32 link_fault_cnt;
259 swStat_t sw_stat;
189} StatInfo_t; 260} StatInfo_t;
190 261
191/* Structures representing different init time configuration 262/*
263 * Structures representing different init time configuration
192 * parameters of the NIC. 264 * parameters of the NIC.
193 */ 265 */
194 266
267#define MAX_TX_FIFOS 8
268#define MAX_RX_RINGS 8
269
270/* FIFO mappings for all possible number of fifos configured */
271int fifo_map[][MAX_TX_FIFOS] = {
272 {0, 0, 0, 0, 0, 0, 0, 0},
273 {0, 0, 0, 0, 1, 1, 1, 1},
274 {0, 0, 0, 1, 1, 1, 2, 2},
275 {0, 0, 1, 1, 2, 2, 3, 3},
276 {0, 0, 1, 1, 2, 2, 3, 4},
277 {0, 0, 1, 1, 2, 3, 4, 5},
278 {0, 0, 1, 2, 3, 4, 5, 6},
279 {0, 1, 2, 3, 4, 5, 6, 7},
280};
281
195/* Maintains Per FIFO related information. */ 282/* Maintains Per FIFO related information. */
196typedef struct tx_fifo_config { 283typedef struct tx_fifo_config {
197#define MAX_AVAILABLE_TXDS 8192 284#define MAX_AVAILABLE_TXDS 8192
@@ -237,14 +324,14 @@ typedef struct rx_ring_config {
237#define NO_SNOOP_RXD_BUFFER 0x02 324#define NO_SNOOP_RXD_BUFFER 0x02
238} rx_ring_config_t; 325} rx_ring_config_t;
239 326
240/* This structure provides contains values of the tunable parameters 327/* This structure provides contains values of the tunable parameters
241 * of the H/W 328 * of the H/W
242 */ 329 */
243struct config_param { 330struct config_param {
244/* Tx Side */ 331/* Tx Side */
245 u32 tx_fifo_num; /*Number of Tx FIFOs */ 332 u32 tx_fifo_num; /*Number of Tx FIFOs */
246#define MAX_TX_FIFOS 8
247 333
334 u8 fifo_mapping[MAX_TX_FIFOS];
248 tx_fifo_config_t tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */ 335 tx_fifo_config_t tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
249 u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */ 336 u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
250 u64 tx_intr_type; 337 u64 tx_intr_type;
@@ -252,10 +339,10 @@ struct config_param {
252 339
253/* Rx Side */ 340/* Rx Side */
254 u32 rx_ring_num; /*Number of receive rings */ 341 u32 rx_ring_num; /*Number of receive rings */
255#define MAX_RX_RINGS 8
256#define MAX_RX_BLOCKS_PER_RING 150 342#define MAX_RX_BLOCKS_PER_RING 150
257 343
258 rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */ 344 rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
345 u8 bimodal; /*Flag for setting bimodal interrupts*/
259 346
260#define HEADER_ETHERNET_II_802_3_SIZE 14 347#define HEADER_ETHERNET_II_802_3_SIZE 14
261#define HEADER_802_2_SIZE 3 348#define HEADER_802_2_SIZE 3
@@ -269,6 +356,7 @@ struct config_param {
269#define MAX_PYLD_JUMBO 9600 356#define MAX_PYLD_JUMBO 9600
270#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18) 357#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
271#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22) 358#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
359 u16 bus_speed;
272}; 360};
273 361
274/* Structure representing MAC Addrs */ 362/* Structure representing MAC Addrs */
@@ -277,7 +365,7 @@ typedef struct mac_addr {
277} macaddr_t; 365} macaddr_t;
278 366
279/* Structure that represent every FIFO element in the BAR1 367/* Structure that represent every FIFO element in the BAR1
280 * Address location. 368 * Address location.
281 */ 369 */
282typedef struct _TxFIFO_element { 370typedef struct _TxFIFO_element {
283 u64 TxDL_Pointer; 371 u64 TxDL_Pointer;
@@ -339,6 +427,7 @@ typedef struct _RxD_t {
339#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8) 427#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
340#define RXD_FRAME_PROTO_IPV4 BIT(27) 428#define RXD_FRAME_PROTO_IPV4 BIT(27)
341#define RXD_FRAME_PROTO_IPV6 BIT(28) 429#define RXD_FRAME_PROTO_IPV6 BIT(28)
430#define RXD_FRAME_IP_FRAG BIT(29)
342#define RXD_FRAME_PROTO_TCP BIT(30) 431#define RXD_FRAME_PROTO_TCP BIT(30)
343#define RXD_FRAME_PROTO_UDP BIT(31) 432#define RXD_FRAME_PROTO_UDP BIT(31)
344#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP) 433#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
@@ -346,11 +435,15 @@ typedef struct _RxD_t {
346#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF) 435#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
347 436
348 u64 Control_2; 437 u64 Control_2;
438#define THE_RXD_MARK 0x3
439#define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
440#define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
441
349#ifndef CONFIG_2BUFF_MODE 442#ifndef CONFIG_2BUFF_MODE
350#define MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16) 443#define MASK_BUFFER0_SIZE vBIT(0x3FFF,2,14)
351#define SET_BUFFER0_SIZE(val) vBIT(val,0,16) 444#define SET_BUFFER0_SIZE(val) vBIT(val,2,14)
352#else 445#else
353#define MASK_BUFFER0_SIZE vBIT(0xFF,0,16) 446#define MASK_BUFFER0_SIZE vBIT(0xFF,2,14)
354#define MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16) 447#define MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)
355#define MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16) 448#define MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)
356#define SET_BUFFER0_SIZE(val) vBIT(val,8,8) 449#define SET_BUFFER0_SIZE(val) vBIT(val,8,8)
@@ -363,7 +456,7 @@ typedef struct _RxD_t {
363#define SET_NUM_TAG(val) vBIT(val,16,32) 456#define SET_NUM_TAG(val) vBIT(val,16,32)
364 457
365#ifndef CONFIG_2BUFF_MODE 458#ifndef CONFIG_2BUFF_MODE
366#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16))) 459#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0x3FFF,2,14)))
367#else 460#else
368#define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \ 461#define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \
369 >> 48) 462 >> 48)
@@ -382,7 +475,7 @@ typedef struct _RxD_t {
382#endif 475#endif
383} RxD_t; 476} RxD_t;
384 477
385/* Structure that represents the Rx descriptor block which contains 478/* Structure that represents the Rx descriptor block which contains
386 * 128 Rx descriptors. 479 * 128 Rx descriptors.
387 */ 480 */
388#ifndef CONFIG_2BUFF_MODE 481#ifndef CONFIG_2BUFF_MODE
@@ -392,11 +485,11 @@ typedef struct _RxD_block {
392 485
393 u64 reserved_0; 486 u64 reserved_0;
394#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL 487#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
395 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last 488 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
396 * Rxd in this blk */ 489 * Rxd in this blk */
397 u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */ 490 u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
398 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch 491 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
399 * the upper 32 bits should 492 * the upper 32 bits should
400 * be 0 */ 493 * be 0 */
401} RxD_block_t; 494} RxD_block_t;
402#else 495#else
@@ -405,13 +498,13 @@ typedef struct _RxD_block {
405 RxD_t rxd[MAX_RXDS_PER_BLOCK]; 498 RxD_t rxd[MAX_RXDS_PER_BLOCK];
406 499
407#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL 500#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
408 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd 501 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd
409 * in this blk */ 502 * in this blk */
410 u64 pNext_RxD_Blk_physical; /* Phy ponter to next blk. */ 503 u64 pNext_RxD_Blk_physical; /* Phy ponter to next blk. */
411} RxD_block_t; 504} RxD_block_t;
412#define SIZE_OF_BLOCK 4096 505#define SIZE_OF_BLOCK 4096
413 506
414/* Structure to hold virtual addresses of Buf0 and Buf1 in 507/* Structure to hold virtual addresses of Buf0 and Buf1 in
415 * 2buf mode. */ 508 * 2buf mode. */
416typedef struct bufAdd { 509typedef struct bufAdd {
417 void *ba_0_org; 510 void *ba_0_org;
@@ -423,8 +516,8 @@ typedef struct bufAdd {
423 516
424/* Structure which stores all the MAC control parameters */ 517/* Structure which stores all the MAC control parameters */
425 518
426/* This structure stores the offset of the RxD in the ring 519/* This structure stores the offset of the RxD in the ring
427 * from which the Rx Interrupt processor can start picking 520 * from which the Rx Interrupt processor can start picking
428 * up the RxDs for processing. 521 * up the RxDs for processing.
429 */ 522 */
430typedef struct _rx_curr_get_info_t { 523typedef struct _rx_curr_get_info_t {
@@ -436,7 +529,7 @@ typedef struct _rx_curr_get_info_t {
436typedef rx_curr_get_info_t rx_curr_put_info_t; 529typedef rx_curr_get_info_t rx_curr_put_info_t;
437 530
438/* This structure stores the offset of the TxDl in the FIFO 531/* This structure stores the offset of the TxDl in the FIFO
439 * from which the Tx Interrupt processor can start picking 532 * from which the Tx Interrupt processor can start picking
440 * up the TxDLs for send complete interrupt processing. 533 * up the TxDLs for send complete interrupt processing.
441 */ 534 */
442typedef struct { 535typedef struct {
@@ -446,32 +539,96 @@ typedef struct {
446 539
447typedef tx_curr_get_info_t tx_curr_put_info_t; 540typedef tx_curr_get_info_t tx_curr_put_info_t;
448 541
449/* Infomation related to the Tx and Rx FIFOs and Rings of Xena 542/* Structure that holds the Phy and virt addresses of the Blocks */
450 * is maintained in this structure. 543typedef struct rx_block_info {
451 */ 544 RxD_t *block_virt_addr;
452typedef struct mac_info { 545 dma_addr_t block_dma_addr;
453/* rx side stuff */ 546} rx_block_info_t;
454 /* Put pointer info which indictes which RxD has to be replenished 547
548/* pre declaration of the nic structure */
549typedef struct s2io_nic nic_t;
550
551/* Ring specific structure */
552typedef struct ring_info {
553 /* The ring number */
554 int ring_no;
555
556 /*
557 * Place holders for the virtual and physical addresses of
558 * all the Rx Blocks
559 */
560 rx_block_info_t rx_blocks[MAX_RX_BLOCKS_PER_RING];
561 int block_count;
562 int pkt_cnt;
563
564 /*
565 * Put pointer info which indictes which RxD has to be replenished
455 * with a new buffer. 566 * with a new buffer.
456 */ 567 */
457 rx_curr_put_info_t rx_curr_put_info[MAX_RX_RINGS]; 568 rx_curr_put_info_t rx_curr_put_info;
458 569
459 /* Get pointer info which indictes which is the last RxD that was 570 /*
571 * Get pointer info which indictes which is the last RxD that was
460 * processed by the driver. 572 * processed by the driver.
461 */ 573 */
462 rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS]; 574 rx_curr_get_info_t rx_curr_get_info;
463 575
464 u16 rmac_pause_time; 576#ifndef CONFIG_S2IO_NAPI
465 u16 mc_pause_threshold_q0q3; 577 /* Index to the absolute position of the put pointer of Rx ring */
466 u16 mc_pause_threshold_q4q7; 578 int put_pos;
579#endif
580
581#ifdef CONFIG_2BUFF_MODE
582 /* Buffer Address store. */
583 buffAdd_t **ba;
584#endif
585 nic_t *nic;
586} ring_info_t;
467 587
588/* Fifo specific structure */
589typedef struct fifo_info {
590 /* FIFO number */
591 int fifo_no;
592
593 /* Maximum TxDs per TxDL */
594 int max_txds;
595
596 /* Place holder of all the TX List's Phy and Virt addresses. */
597 list_info_hold_t *list_info;
598
599 /*
600 * Current offset within the tx FIFO where driver would write
601 * new Tx frame
602 */
603 tx_curr_put_info_t tx_curr_put_info;
604
605 /*
606 * Current offset within tx FIFO from where the driver would start freeing
607 * the buffers
608 */
609 tx_curr_get_info_t tx_curr_get_info;
610
611 nic_t *nic;
612}fifo_info_t;
613
614/* Infomation related to the Tx and Rx FIFOs and Rings of Xena
615 * is maintained in this structure.
616 */
617typedef struct mac_info {
468/* tx side stuff */ 618/* tx side stuff */
469 /* logical pointer of start of each Tx FIFO */ 619 /* logical pointer of start of each Tx FIFO */
470 TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS]; 620 TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS];
471 621
472/* Current offset within tx_FIFO_start, where driver would write new Tx frame*/ 622 /* Fifo specific structure */
473 tx_curr_put_info_t tx_curr_put_info[MAX_TX_FIFOS]; 623 fifo_info_t fifos[MAX_TX_FIFOS];
474 tx_curr_get_info_t tx_curr_get_info[MAX_TX_FIFOS]; 624
625/* rx side stuff */
626 /* Ring specific structure */
627 ring_info_t rings[MAX_RX_RINGS];
628
629 u16 rmac_pause_time;
630 u16 mc_pause_threshold_q0q3;
631 u16 mc_pause_threshold_q4q7;
475 632
476 void *stats_mem; /* orignal pointer to allocated mem */ 633 void *stats_mem; /* orignal pointer to allocated mem */
477 dma_addr_t stats_mem_phy; /* Physical address of the stat block */ 634 dma_addr_t stats_mem_phy; /* Physical address of the stat block */
@@ -485,12 +642,6 @@ typedef struct {
485 int usage_cnt; 642 int usage_cnt;
486} usr_addr_t; 643} usr_addr_t;
487 644
488/* Structure that holds the Phy and virt addresses of the Blocks */
489typedef struct rx_block_info {
490 RxD_t *block_virt_addr;
491 dma_addr_t block_dma_addr;
492} rx_block_info_t;
493
494/* Default Tunable parameters of the NIC. */ 645/* Default Tunable parameters of the NIC. */
495#define DEFAULT_FIFO_LEN 4096 646#define DEFAULT_FIFO_LEN 4096
496#define SMALL_RXD_CNT 30 * (MAX_RXDS_PER_BLOCK+1) 647#define SMALL_RXD_CNT 30 * (MAX_RXDS_PER_BLOCK+1)
@@ -499,7 +650,20 @@ typedef struct rx_block_info {
499#define LARGE_BLK_CNT 100 650#define LARGE_BLK_CNT 100
500 651
501/* Structure representing one instance of the NIC */ 652/* Structure representing one instance of the NIC */
502typedef struct s2io_nic { 653struct s2io_nic {
654#ifdef CONFIG_S2IO_NAPI
655 /*
656 * Count of packets to be processed in a given iteration, it will be indicated
657 * by the quota field of the device structure when NAPI is enabled.
658 */
659 int pkts_to_process;
660#endif
661 struct net_device *dev;
662 mac_info_t mac_control;
663 struct config_param config;
664 struct pci_dev *pdev;
665 void __iomem *bar0;
666 void __iomem *bar1;
503#define MAX_MAC_SUPPORTED 16 667#define MAX_MAC_SUPPORTED 16
504#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED 668#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
505 669
@@ -507,33 +671,20 @@ typedef struct s2io_nic {
507 macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED]; 671 macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED];
508 672
509 struct net_device_stats stats; 673 struct net_device_stats stats;
510 void __iomem *bar0;
511 void __iomem *bar1;
512 struct config_param config;
513 mac_info_t mac_control;
514 int high_dma_flag; 674 int high_dma_flag;
515 int device_close_flag; 675 int device_close_flag;
516 int device_enabled_once; 676 int device_enabled_once;
517 677
518 char name[32]; 678 char name[50];
519 struct tasklet_struct task; 679 struct tasklet_struct task;
520 volatile unsigned long tasklet_status; 680 volatile unsigned long tasklet_status;
521 struct timer_list timer;
522 struct net_device *dev;
523 struct pci_dev *pdev;
524 681
525 u16 vendor_id; 682 /* Timer that handles I/O errors/exceptions */
526 u16 device_id; 683 struct timer_list alarm_timer;
527 u16 ccmd; 684
528 u32 cbar0_1; 685 /* Space to back up the PCI config space */
529 u32 cbar0_2; 686 u32 config_space[256 / sizeof(u32)];
530 u32 cbar1_1; 687
531 u32 cbar1_2;
532 u32 cirq;
533 u8 cache_line;
534 u32 rom_expansion;
535 u16 pcix_cmd;
536 u32 irq;
537 atomic_t rx_bufs_left[MAX_RX_RINGS]; 688 atomic_t rx_bufs_left[MAX_RX_RINGS];
538 689
539 spinlock_t tx_lock; 690 spinlock_t tx_lock;
@@ -558,27 +709,11 @@ typedef struct s2io_nic {
558 u16 tx_err_count; 709 u16 tx_err_count;
559 u16 rx_err_count; 710 u16 rx_err_count;
560 711
561#ifndef CONFIG_S2IO_NAPI
562 /* Index to the absolute position of the put pointer of Rx ring. */
563 int put_pos[MAX_RX_RINGS];
564#endif
565
566 /*
567 * Place holders for the virtual and physical addresses of
568 * all the Rx Blocks
569 */
570 rx_block_info_t rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING];
571 int block_count[MAX_RX_RINGS];
572 int pkt_cnt[MAX_RX_RINGS];
573
574 /* Place holder of all the TX List's Phy and Virt addresses. */
575 list_info_hold_t *list_info[MAX_TX_FIFOS];
576
577 /* Id timer, used to blink NIC to physically identify NIC. */ 712 /* Id timer, used to blink NIC to physically identify NIC. */
578 struct timer_list id_timer; 713 struct timer_list id_timer;
579 714
580 /* Restart timer, used to restart NIC if the device is stuck and 715 /* Restart timer, used to restart NIC if the device is stuck and
581 * a schedule task that will set the correct Link state once the 716 * a schedule task that will set the correct Link state once the
582 * NIC's PHY has stabilized after a state change. 717 * NIC's PHY has stabilized after a state change.
583 */ 718 */
584#ifdef INIT_TQUEUE 719#ifdef INIT_TQUEUE
@@ -589,12 +724,12 @@ typedef struct s2io_nic {
589 struct work_struct set_link_task; 724 struct work_struct set_link_task;
590#endif 725#endif
591 726
592 /* Flag that can be used to turn on or turn off the Rx checksum 727 /* Flag that can be used to turn on or turn off the Rx checksum
593 * offload feature. 728 * offload feature.
594 */ 729 */
595 int rx_csum; 730 int rx_csum;
596 731
597 /* after blink, the adapter must be restored with original 732 /* after blink, the adapter must be restored with original
598 * values. 733 * values.
599 */ 734 */
600 u64 adapt_ctrl_org; 735 u64 adapt_ctrl_org;
@@ -604,16 +739,19 @@ typedef struct s2io_nic {
604#define LINK_DOWN 1 739#define LINK_DOWN 1
605#define LINK_UP 2 740#define LINK_UP 2
606 741
607#ifdef CONFIG_2BUFF_MODE
608 /* Buffer Address store. */
609 buffAdd_t **ba[MAX_RX_RINGS];
610#endif
611 int task_flag; 742 int task_flag;
612#define CARD_DOWN 1 743#define CARD_DOWN 1
613#define CARD_UP 2 744#define CARD_UP 2
614 atomic_t card_state; 745 atomic_t card_state;
615 volatile unsigned long link_state; 746 volatile unsigned long link_state;
616} nic_t; 747 struct vlan_group *vlgrp;
748#define XFRAME_I_DEVICE 1
749#define XFRAME_II_DEVICE 2
750 u8 device_type;
751
752 spinlock_t rx_lock;
753 atomic_t isr_cnt;
754};
617 755
618#define RESET_ERROR 1; 756#define RESET_ERROR 1;
619#define CMD_ERROR 2; 757#define CMD_ERROR 2;
@@ -622,7 +760,8 @@ typedef struct s2io_nic {
622#ifndef readq 760#ifndef readq
623static inline u64 readq(void __iomem *addr) 761static inline u64 readq(void __iomem *addr)
624{ 762{
625 u64 ret = readl(addr + 4); 763 u64 ret = 0;
764 ret = readl(addr + 4);
626 ret <<= 32; 765 ret <<= 32;
627 ret |= readl(addr); 766 ret |= readl(addr);
628 767
@@ -637,10 +776,10 @@ static inline void writeq(u64 val, void __iomem *addr)
637 writel((u32) (val >> 32), (addr + 4)); 776 writel((u32) (val >> 32), (addr + 4));
638} 777}
639 778
640/* In 32 bit modes, some registers have to be written in a 779/* In 32 bit modes, some registers have to be written in a
641 * particular order to expect correct hardware operation. The 780 * particular order to expect correct hardware operation. The
642 * macro SPECIAL_REG_WRITE is used to perform such ordered 781 * macro SPECIAL_REG_WRITE is used to perform such ordered
643 * writes. Defines UF (Upper First) and LF (Lower First) will 782 * writes. Defines UF (Upper First) and LF (Lower First) will
644 * be used to specify the required write order. 783 * be used to specify the required write order.
645 */ 784 */
646#define UF 1 785#define UF 1
@@ -716,6 +855,7 @@ static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
716#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate 855#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
717 PCC_FB_ECC Error. */ 856 PCC_FB_ECC Error. */
718 857
858#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
719/* 859/*
720 * Prototype declaration. 860 * Prototype declaration.
721 */ 861 */
@@ -725,36 +865,30 @@ static void __devexit s2io_rem_nic(struct pci_dev *pdev);
725static int init_shared_mem(struct s2io_nic *sp); 865static int init_shared_mem(struct s2io_nic *sp);
726static void free_shared_mem(struct s2io_nic *sp); 866static void free_shared_mem(struct s2io_nic *sp);
727static int init_nic(struct s2io_nic *nic); 867static int init_nic(struct s2io_nic *nic);
728#ifndef CONFIG_S2IO_NAPI 868static void rx_intr_handler(ring_info_t *ring_data);
729static void rx_intr_handler(struct s2io_nic *sp); 869static void tx_intr_handler(fifo_info_t *fifo_data);
730#endif
731static void tx_intr_handler(struct s2io_nic *sp);
732static void alarm_intr_handler(struct s2io_nic *sp); 870static void alarm_intr_handler(struct s2io_nic *sp);
733 871
734static int s2io_starter(void); 872static int s2io_starter(void);
735static void s2io_closer(void); 873void s2io_closer(void);
736static void s2io_tx_watchdog(struct net_device *dev); 874static void s2io_tx_watchdog(struct net_device *dev);
737static void s2io_tasklet(unsigned long dev_addr); 875static void s2io_tasklet(unsigned long dev_addr);
738static void s2io_set_multicast(struct net_device *dev); 876static void s2io_set_multicast(struct net_device *dev);
739#ifndef CONFIG_2BUFF_MODE 877static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp);
740static int rx_osm_handler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no); 878void s2io_link(nic_t * sp, int link);
741#else 879void s2io_reset(nic_t * sp);
742static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no, 880#if defined(CONFIG_S2IO_NAPI)
743 buffAdd_t * ba);
744#endif
745static void s2io_link(nic_t * sp, int link);
746static void s2io_reset(nic_t * sp);
747#ifdef CONFIG_S2IO_NAPI
748static int s2io_poll(struct net_device *dev, int *budget); 881static int s2io_poll(struct net_device *dev, int *budget);
749#endif 882#endif
750static void s2io_init_pci(nic_t * sp); 883static void s2io_init_pci(nic_t * sp);
751static int s2io_set_mac_addr(struct net_device *dev, u8 * addr); 884int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
885static void s2io_alarm_handle(unsigned long data);
752static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs); 886static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);
753static int verify_xena_quiescence(u64 val64, int flag); 887static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag);
754static struct ethtool_ops netdev_ethtool_ops; 888static struct ethtool_ops netdev_ethtool_ops;
755static void s2io_set_link(unsigned long data); 889static void s2io_set_link(unsigned long data);
756static int s2io_set_swapper(nic_t * sp); 890int s2io_set_swapper(nic_t * sp);
757static void s2io_card_down(nic_t * nic); 891static void s2io_card_down(nic_t *nic);
758static int s2io_card_up(nic_t * nic); 892static int s2io_card_up(nic_t *nic);
759 893int get_xena_rev_id(struct pci_dev *pdev);
760#endif /* _S2IO_H */ 894#endif /* _S2IO_H */