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-rw-r--r--drivers/net/s2io.c3085
1 files changed, 1895 insertions, 1190 deletions
diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c
index ea638b162d3f..7ca78228b104 100644
--- a/drivers/net/s2io.c
+++ b/drivers/net/s2io.c
@@ -11,29 +11,28 @@
11 * See the file COPYING in this distribution for more information. 11 * See the file COPYING in this distribution for more information.
12 * 12 *
13 * Credits: 13 * Credits:
14 * Jeff Garzik : For pointing out the improper error condition 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some 15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for 16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable 17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues. 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some 19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel. 20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were 21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments. 22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture 23 * Grant Grundler : For helping me get rid of some Architecture
24 * dependent code. 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver. 25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
26 * 26 *
27 * The module loadable parameters that are supported by the driver and a brief 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables. 28 * explaination of all the variables.
29 * rx_ring_num : This can be used to program the number of receive rings used 29 * rx_ring_num : This can be used to program the number of receive rings used
30 * in the driver. 30 * in the driver.
31 * rx_ring_len: This defines the number of descriptors each ring can have. This 31 * rx_ring_len: This defines the number of descriptors each ring can have. This
32 * is also an array of size 8. 32 * is also an array of size 8.
33 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver. 33 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
34 * tx_fifo_len: This too is an array of 8. Each element defines the number of 34 * tx_fifo_len: This too is an array of 8. Each element defines the number of
35 * Tx descriptors that can be associated with each corresponding FIFO. 35 * Tx descriptors that can be associated with each corresponding FIFO.
36 * in PCI Configuration space.
37 ************************************************************************/ 36 ************************************************************************/
38 37
39#include <linux/config.h> 38#include <linux/config.h>
@@ -56,27 +55,39 @@
56#include <linux/ethtool.h> 55#include <linux/ethtool.h>
57#include <linux/version.h> 56#include <linux/version.h>
58#include <linux/workqueue.h> 57#include <linux/workqueue.h>
58#include <linux/if_vlan.h>
59 59
60#include <asm/io.h>
61#include <asm/system.h> 60#include <asm/system.h>
62#include <asm/uaccess.h> 61#include <asm/uaccess.h>
62#include <asm/io.h>
63 63
64/* local include */ 64/* local include */
65#include "s2io.h" 65#include "s2io.h"
66#include "s2io-regs.h" 66#include "s2io-regs.h"
67 67
68/* S2io Driver name & version. */ 68/* S2io Driver name & version. */
69static char s2io_driver_name[] = "s2io"; 69static char s2io_driver_name[] = "Neterion";
70static char s2io_driver_version[] = "Version 1.7.7.1"; 70static char s2io_driver_version[] = "Version 2.0.3.1";
71
72static inline int RXD_IS_UP2DT(RxD_t *rxdp)
73{
74 int ret;
75
76 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
77 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
71 78
72/* 79 return ret;
80}
81
82/*
73 * Cards with following subsystem_id have a link state indication 83 * Cards with following subsystem_id have a link state indication
74 * problem, 600B, 600C, 600D, 640B, 640C and 640D. 84 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
75 * macro below identifies these cards given the subsystem_id. 85 * macro below identifies these cards given the subsystem_id.
76 */ 86 */
77#define CARDS_WITH_FAULTY_LINK_INDICATORS(subid) \ 87#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
78 (((subid >= 0x600B) && (subid <= 0x600D)) || \ 88 (dev_type == XFRAME_I_DEVICE) ? \
79 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0 89 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
90 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
80 91
81#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \ 92#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
82 ADAPTER_STATUS_RMAC_LOCAL_FAULT))) 93 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
@@ -86,9 +97,12 @@ static char s2io_driver_version[] = "Version 1.7.7.1";
86static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring) 97static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
87{ 98{
88 int level = 0; 99 int level = 0;
89 if ((sp->pkt_cnt[ring] - rxb_size) > 16) { 100 mac_info_t *mac_control;
101
102 mac_control = &sp->mac_control;
103 if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16) {
90 level = LOW; 104 level = LOW;
91 if ((sp->pkt_cnt[ring] - rxb_size) < MAX_RXDS_PER_BLOCK) { 105 if (rxb_size <= MAX_RXDS_PER_BLOCK) {
92 level = PANIC; 106 level = PANIC;
93 } 107 }
94 } 108 }
@@ -145,6 +159,9 @@ static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
145 {"rmac_pause_cnt"}, 159 {"rmac_pause_cnt"},
146 {"rmac_accepted_ip"}, 160 {"rmac_accepted_ip"},
147 {"rmac_err_tcp"}, 161 {"rmac_err_tcp"},
162 {"\n DRIVER STATISTICS"},
163 {"single_bit_ecc_errs"},
164 {"double_bit_ecc_errs"},
148}; 165};
149 166
150#define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN 167#define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
@@ -153,8 +170,37 @@ static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
153#define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN 170#define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
154#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN 171#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
155 172
173#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
174 init_timer(&timer); \
175 timer.function = handle; \
176 timer.data = (unsigned long) arg; \
177 mod_timer(&timer, (jiffies + exp)) \
178
179/* Add the vlan */
180static void s2io_vlan_rx_register(struct net_device *dev,
181 struct vlan_group *grp)
182{
183 nic_t *nic = dev->priv;
184 unsigned long flags;
185
186 spin_lock_irqsave(&nic->tx_lock, flags);
187 nic->vlgrp = grp;
188 spin_unlock_irqrestore(&nic->tx_lock, flags);
189}
190
191/* Unregister the vlan */
192static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
193{
194 nic_t *nic = dev->priv;
195 unsigned long flags;
196
197 spin_lock_irqsave(&nic->tx_lock, flags);
198 if (nic->vlgrp)
199 nic->vlgrp->vlan_devices[vid] = NULL;
200 spin_unlock_irqrestore(&nic->tx_lock, flags);
201}
156 202
157/* 203/*
158 * Constants to be programmed into the Xena's registers, to configure 204 * Constants to be programmed into the Xena's registers, to configure
159 * the XAUI. 205 * the XAUI.
160 */ 206 */
@@ -162,7 +208,28 @@ static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
162#define SWITCH_SIGN 0xA5A5A5A5A5A5A5A5ULL 208#define SWITCH_SIGN 0xA5A5A5A5A5A5A5A5ULL
163#define END_SIGN 0x0 209#define END_SIGN 0x0
164 210
165static u64 default_mdio_cfg[] = { 211static u64 herc_act_dtx_cfg[] = {
212 /* Set address */
213 0x8000051536750000ULL, 0x80000515367500E0ULL,
214 /* Write data */
215 0x8000051536750004ULL, 0x80000515367500E4ULL,
216 /* Set address */
217 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
218 /* Write data */
219 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
220 /* Set address */
221 0x801205150D440000ULL, 0x801205150D4400E0ULL,
222 /* Write data */
223 0x801205150D440004ULL, 0x801205150D4400E4ULL,
224 /* Set address */
225 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
226 /* Write data */
227 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
228 /* Done */
229 END_SIGN
230};
231
232static u64 xena_mdio_cfg[] = {
166 /* Reset PMA PLL */ 233 /* Reset PMA PLL */
167 0xC001010000000000ULL, 0xC0010100000000E0ULL, 234 0xC001010000000000ULL, 0xC0010100000000E0ULL,
168 0xC0010100008000E4ULL, 235 0xC0010100008000E4ULL,
@@ -172,7 +239,7 @@ static u64 default_mdio_cfg[] = {
172 END_SIGN 239 END_SIGN
173}; 240};
174 241
175static u64 default_dtx_cfg[] = { 242static u64 xena_dtx_cfg[] = {
176 0x8000051500000000ULL, 0x80000515000000E0ULL, 243 0x8000051500000000ULL, 0x80000515000000E0ULL,
177 0x80000515D93500E4ULL, 0x8001051500000000ULL, 244 0x80000515D93500E4ULL, 0x8001051500000000ULL,
178 0x80010515000000E0ULL, 0x80010515001E00E4ULL, 245 0x80010515000000E0ULL, 0x80010515001E00E4ULL,
@@ -196,8 +263,7 @@ static u64 default_dtx_cfg[] = {
196 END_SIGN 263 END_SIGN
197}; 264};
198 265
199 266/*
200/*
201 * Constants for Fixing the MacAddress problem seen mostly on 267 * Constants for Fixing the MacAddress problem seen mostly on
202 * Alpha machines. 268 * Alpha machines.
203 */ 269 */
@@ -226,20 +292,25 @@ static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
226static unsigned int rx_ring_num = 1; 292static unsigned int rx_ring_num = 1;
227static unsigned int rx_ring_sz[MAX_RX_RINGS] = 293static unsigned int rx_ring_sz[MAX_RX_RINGS] =
228 {[0 ...(MAX_RX_RINGS - 1)] = 0 }; 294 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
229static unsigned int Stats_refresh_time = 4; 295static unsigned int rts_frm_len[MAX_RX_RINGS] =
296 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
297static unsigned int use_continuous_tx_intrs = 1;
230static unsigned int rmac_pause_time = 65535; 298static unsigned int rmac_pause_time = 65535;
231static unsigned int mc_pause_threshold_q0q3 = 187; 299static unsigned int mc_pause_threshold_q0q3 = 187;
232static unsigned int mc_pause_threshold_q4q7 = 187; 300static unsigned int mc_pause_threshold_q4q7 = 187;
233static unsigned int shared_splits; 301static unsigned int shared_splits;
234static unsigned int tmac_util_period = 5; 302static unsigned int tmac_util_period = 5;
235static unsigned int rmac_util_period = 5; 303static unsigned int rmac_util_period = 5;
304static unsigned int bimodal = 0;
236#ifndef CONFIG_S2IO_NAPI 305#ifndef CONFIG_S2IO_NAPI
237static unsigned int indicate_max_pkts; 306static unsigned int indicate_max_pkts;
238#endif 307#endif
308/* Frequency of Rx desc syncs expressed as power of 2 */
309static unsigned int rxsync_frequency = 3;
239 310
240/* 311/*
241 * S2IO device table. 312 * S2IO device table.
242 * This table lists all the devices that this driver supports. 313 * This table lists all the devices that this driver supports.
243 */ 314 */
244static struct pci_device_id s2io_tbl[] __devinitdata = { 315static struct pci_device_id s2io_tbl[] __devinitdata = {
245 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN, 316 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
@@ -247,9 +318,9 @@ static struct pci_device_id s2io_tbl[] __devinitdata = {
247 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI, 318 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
248 PCI_ANY_ID, PCI_ANY_ID}, 319 PCI_ANY_ID, PCI_ANY_ID},
249 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN, 320 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
250 PCI_ANY_ID, PCI_ANY_ID}, 321 PCI_ANY_ID, PCI_ANY_ID},
251 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI, 322 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
252 PCI_ANY_ID, PCI_ANY_ID}, 323 PCI_ANY_ID, PCI_ANY_ID},
253 {0,} 324 {0,}
254}; 325};
255 326
@@ -268,8 +339,8 @@ static struct pci_driver s2io_driver = {
268/** 339/**
269 * init_shared_mem - Allocation and Initialization of Memory 340 * init_shared_mem - Allocation and Initialization of Memory
270 * @nic: Device private variable. 341 * @nic: Device private variable.
271 * Description: The function allocates all the memory areas shared 342 * Description: The function allocates all the memory areas shared
272 * between the NIC and the driver. This includes Tx descriptors, 343 * between the NIC and the driver. This includes Tx descriptors,
273 * Rx descriptors and the statistics block. 344 * Rx descriptors and the statistics block.
274 */ 345 */
275 346
@@ -279,11 +350,11 @@ static int init_shared_mem(struct s2io_nic *nic)
279 void *tmp_v_addr, *tmp_v_addr_next; 350 void *tmp_v_addr, *tmp_v_addr_next;
280 dma_addr_t tmp_p_addr, tmp_p_addr_next; 351 dma_addr_t tmp_p_addr, tmp_p_addr_next;
281 RxD_block_t *pre_rxd_blk = NULL; 352 RxD_block_t *pre_rxd_blk = NULL;
282 int i, j, blk_cnt; 353 int i, j, blk_cnt, rx_sz, tx_sz;
283 int lst_size, lst_per_page; 354 int lst_size, lst_per_page;
284 struct net_device *dev = nic->dev; 355 struct net_device *dev = nic->dev;
285#ifdef CONFIG_2BUFF_MODE 356#ifdef CONFIG_2BUFF_MODE
286 unsigned long tmp; 357 u64 tmp;
287 buffAdd_t *ba; 358 buffAdd_t *ba;
288#endif 359#endif
289 360
@@ -300,36 +371,41 @@ static int init_shared_mem(struct s2io_nic *nic)
300 size += config->tx_cfg[i].fifo_len; 371 size += config->tx_cfg[i].fifo_len;
301 } 372 }
302 if (size > MAX_AVAILABLE_TXDS) { 373 if (size > MAX_AVAILABLE_TXDS) {
303 DBG_PRINT(ERR_DBG, "%s: Total number of Tx FIFOs ", 374 DBG_PRINT(ERR_DBG, "%s: Requested TxDs too high, ",
304 dev->name); 375 __FUNCTION__);
305 DBG_PRINT(ERR_DBG, "exceeds the maximum value "); 376 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
306 DBG_PRINT(ERR_DBG, "that can be used\n");
307 return FAILURE; 377 return FAILURE;
308 } 378 }
309 379
310 lst_size = (sizeof(TxD_t) * config->max_txds); 380 lst_size = (sizeof(TxD_t) * config->max_txds);
381 tx_sz = lst_size * size;
311 lst_per_page = PAGE_SIZE / lst_size; 382 lst_per_page = PAGE_SIZE / lst_size;
312 383
313 for (i = 0; i < config->tx_fifo_num; i++) { 384 for (i = 0; i < config->tx_fifo_num; i++) {
314 int fifo_len = config->tx_cfg[i].fifo_len; 385 int fifo_len = config->tx_cfg[i].fifo_len;
315 int list_holder_size = fifo_len * sizeof(list_info_hold_t); 386 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
316 nic->list_info[i] = kmalloc(list_holder_size, GFP_KERNEL); 387 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
317 if (!nic->list_info[i]) { 388 GFP_KERNEL);
389 if (!mac_control->fifos[i].list_info) {
318 DBG_PRINT(ERR_DBG, 390 DBG_PRINT(ERR_DBG,
319 "Malloc failed for list_info\n"); 391 "Malloc failed for list_info\n");
320 return -ENOMEM; 392 return -ENOMEM;
321 } 393 }
322 memset(nic->list_info[i], 0, list_holder_size); 394 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
323 } 395 }
324 for (i = 0; i < config->tx_fifo_num; i++) { 396 for (i = 0; i < config->tx_fifo_num; i++) {
325 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len, 397 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
326 lst_per_page); 398 lst_per_page);
327 mac_control->tx_curr_put_info[i].offset = 0; 399 mac_control->fifos[i].tx_curr_put_info.offset = 0;
328 mac_control->tx_curr_put_info[i].fifo_len = 400 mac_control->fifos[i].tx_curr_put_info.fifo_len =
329 config->tx_cfg[i].fifo_len - 1; 401 config->tx_cfg[i].fifo_len - 1;
330 mac_control->tx_curr_get_info[i].offset = 0; 402 mac_control->fifos[i].tx_curr_get_info.offset = 0;
331 mac_control->tx_curr_get_info[i].fifo_len = 403 mac_control->fifos[i].tx_curr_get_info.fifo_len =
332 config->tx_cfg[i].fifo_len - 1; 404 config->tx_cfg[i].fifo_len - 1;
405 mac_control->fifos[i].fifo_no = i;
406 mac_control->fifos[i].nic = nic;
407 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS;
408
333 for (j = 0; j < page_num; j++) { 409 for (j = 0; j < page_num; j++) {
334 int k = 0; 410 int k = 0;
335 dma_addr_t tmp_p; 411 dma_addr_t tmp_p;
@@ -345,16 +421,15 @@ static int init_shared_mem(struct s2io_nic *nic)
345 while (k < lst_per_page) { 421 while (k < lst_per_page) {
346 int l = (j * lst_per_page) + k; 422 int l = (j * lst_per_page) + k;
347 if (l == config->tx_cfg[i].fifo_len) 423 if (l == config->tx_cfg[i].fifo_len)
348 goto end_txd_alloc; 424 break;
349 nic->list_info[i][l].list_virt_addr = 425 mac_control->fifos[i].list_info[l].list_virt_addr =
350 tmp_v + (k * lst_size); 426 tmp_v + (k * lst_size);
351 nic->list_info[i][l].list_phy_addr = 427 mac_control->fifos[i].list_info[l].list_phy_addr =
352 tmp_p + (k * lst_size); 428 tmp_p + (k * lst_size);
353 k++; 429 k++;
354 } 430 }
355 } 431 }
356 } 432 }
357 end_txd_alloc:
358 433
359 /* Allocation and initialization of RXDs in Rings */ 434 /* Allocation and initialization of RXDs in Rings */
360 size = 0; 435 size = 0;
@@ -367,21 +442,26 @@ static int init_shared_mem(struct s2io_nic *nic)
367 return FAILURE; 442 return FAILURE;
368 } 443 }
369 size += config->rx_cfg[i].num_rxd; 444 size += config->rx_cfg[i].num_rxd;
370 nic->block_count[i] = 445 mac_control->rings[i].block_count =
371 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1); 446 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
372 nic->pkt_cnt[i] = 447 mac_control->rings[i].pkt_cnt =
373 config->rx_cfg[i].num_rxd - nic->block_count[i]; 448 config->rx_cfg[i].num_rxd - mac_control->rings[i].block_count;
374 } 449 }
450 size = (size * (sizeof(RxD_t)));
451 rx_sz = size;
375 452
376 for (i = 0; i < config->rx_ring_num; i++) { 453 for (i = 0; i < config->rx_ring_num; i++) {
377 mac_control->rx_curr_get_info[i].block_index = 0; 454 mac_control->rings[i].rx_curr_get_info.block_index = 0;
378 mac_control->rx_curr_get_info[i].offset = 0; 455 mac_control->rings[i].rx_curr_get_info.offset = 0;
379 mac_control->rx_curr_get_info[i].ring_len = 456 mac_control->rings[i].rx_curr_get_info.ring_len =
380 config->rx_cfg[i].num_rxd - 1; 457 config->rx_cfg[i].num_rxd - 1;
381 mac_control->rx_curr_put_info[i].block_index = 0; 458 mac_control->rings[i].rx_curr_put_info.block_index = 0;
382 mac_control->rx_curr_put_info[i].offset = 0; 459 mac_control->rings[i].rx_curr_put_info.offset = 0;
383 mac_control->rx_curr_put_info[i].ring_len = 460 mac_control->rings[i].rx_curr_put_info.ring_len =
384 config->rx_cfg[i].num_rxd - 1; 461 config->rx_cfg[i].num_rxd - 1;
462 mac_control->rings[i].nic = nic;
463 mac_control->rings[i].ring_no = i;
464
385 blk_cnt = 465 blk_cnt =
386 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1); 466 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
387 /* Allocating all the Rx blocks */ 467 /* Allocating all the Rx blocks */
@@ -395,32 +475,36 @@ static int init_shared_mem(struct s2io_nic *nic)
395 &tmp_p_addr); 475 &tmp_p_addr);
396 if (tmp_v_addr == NULL) { 476 if (tmp_v_addr == NULL) {
397 /* 477 /*
398 * In case of failure, free_shared_mem() 478 * In case of failure, free_shared_mem()
399 * is called, which should free any 479 * is called, which should free any
400 * memory that was alloced till the 480 * memory that was alloced till the
401 * failure happened. 481 * failure happened.
402 */ 482 */
403 nic->rx_blocks[i][j].block_virt_addr = 483 mac_control->rings[i].rx_blocks[j].block_virt_addr =
404 tmp_v_addr; 484 tmp_v_addr;
405 return -ENOMEM; 485 return -ENOMEM;
406 } 486 }
407 memset(tmp_v_addr, 0, size); 487 memset(tmp_v_addr, 0, size);
408 nic->rx_blocks[i][j].block_virt_addr = tmp_v_addr; 488 mac_control->rings[i].rx_blocks[j].block_virt_addr =
409 nic->rx_blocks[i][j].block_dma_addr = tmp_p_addr; 489 tmp_v_addr;
490 mac_control->rings[i].rx_blocks[j].block_dma_addr =
491 tmp_p_addr;
410 } 492 }
411 /* Interlinking all Rx Blocks */ 493 /* Interlinking all Rx Blocks */
412 for (j = 0; j < blk_cnt; j++) { 494 for (j = 0; j < blk_cnt; j++) {
413 tmp_v_addr = nic->rx_blocks[i][j].block_virt_addr; 495 tmp_v_addr =
496 mac_control->rings[i].rx_blocks[j].block_virt_addr;
414 tmp_v_addr_next = 497 tmp_v_addr_next =
415 nic->rx_blocks[i][(j + 1) % 498 mac_control->rings[i].rx_blocks[(j + 1) %
416 blk_cnt].block_virt_addr; 499 blk_cnt].block_virt_addr;
417 tmp_p_addr = nic->rx_blocks[i][j].block_dma_addr; 500 tmp_p_addr =
501 mac_control->rings[i].rx_blocks[j].block_dma_addr;
418 tmp_p_addr_next = 502 tmp_p_addr_next =
419 nic->rx_blocks[i][(j + 1) % 503 mac_control->rings[i].rx_blocks[(j + 1) %
420 blk_cnt].block_dma_addr; 504 blk_cnt].block_dma_addr;
421 505
422 pre_rxd_blk = (RxD_block_t *) tmp_v_addr; 506 pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
423 pre_rxd_blk->reserved_1 = END_OF_BLOCK; /* last RxD 507 pre_rxd_blk->reserved_1 = END_OF_BLOCK; /* last RxD
424 * marker. 508 * marker.
425 */ 509 */
426#ifndef CONFIG_2BUFF_MODE 510#ifndef CONFIG_2BUFF_MODE
@@ -433,43 +517,43 @@ static int init_shared_mem(struct s2io_nic *nic)
433 } 517 }
434 518
435#ifdef CONFIG_2BUFF_MODE 519#ifdef CONFIG_2BUFF_MODE
436 /* 520 /*
437 * Allocation of Storages for buffer addresses in 2BUFF mode 521 * Allocation of Storages for buffer addresses in 2BUFF mode
438 * and the buffers as well. 522 * and the buffers as well.
439 */ 523 */
440 for (i = 0; i < config->rx_ring_num; i++) { 524 for (i = 0; i < config->rx_ring_num; i++) {
441 blk_cnt = 525 blk_cnt =
442 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1); 526 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
443 nic->ba[i] = kmalloc((sizeof(buffAdd_t *) * blk_cnt), 527 mac_control->rings[i].ba = kmalloc((sizeof(buffAdd_t *) * blk_cnt),
444 GFP_KERNEL); 528 GFP_KERNEL);
445 if (!nic->ba[i]) 529 if (!mac_control->rings[i].ba)
446 return -ENOMEM; 530 return -ENOMEM;
447 for (j = 0; j < blk_cnt; j++) { 531 for (j = 0; j < blk_cnt; j++) {
448 int k = 0; 532 int k = 0;
449 nic->ba[i][j] = kmalloc((sizeof(buffAdd_t) * 533 mac_control->rings[i].ba[j] = kmalloc((sizeof(buffAdd_t) *
450 (MAX_RXDS_PER_BLOCK + 1)), 534 (MAX_RXDS_PER_BLOCK + 1)),
451 GFP_KERNEL); 535 GFP_KERNEL);
452 if (!nic->ba[i][j]) 536 if (!mac_control->rings[i].ba[j])
453 return -ENOMEM; 537 return -ENOMEM;
454 while (k != MAX_RXDS_PER_BLOCK) { 538 while (k != MAX_RXDS_PER_BLOCK) {
455 ba = &nic->ba[i][j][k]; 539 ba = &mac_control->rings[i].ba[j][k];
456 540
457 ba->ba_0_org = kmalloc 541 ba->ba_0_org = (void *) kmalloc
458 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL); 542 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
459 if (!ba->ba_0_org) 543 if (!ba->ba_0_org)
460 return -ENOMEM; 544 return -ENOMEM;
461 tmp = (unsigned long) ba->ba_0_org; 545 tmp = (u64) ba->ba_0_org;
462 tmp += ALIGN_SIZE; 546 tmp += ALIGN_SIZE;
463 tmp &= ~((unsigned long) ALIGN_SIZE); 547 tmp &= ~((u64) ALIGN_SIZE);
464 ba->ba_0 = (void *) tmp; 548 ba->ba_0 = (void *) tmp;
465 549
466 ba->ba_1_org = kmalloc 550 ba->ba_1_org = (void *) kmalloc
467 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL); 551 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
468 if (!ba->ba_1_org) 552 if (!ba->ba_1_org)
469 return -ENOMEM; 553 return -ENOMEM;
470 tmp = (unsigned long) ba->ba_1_org; 554 tmp = (u64) ba->ba_1_org;
471 tmp += ALIGN_SIZE; 555 tmp += ALIGN_SIZE;
472 tmp &= ~((unsigned long) ALIGN_SIZE); 556 tmp &= ~((u64) ALIGN_SIZE);
473 ba->ba_1 = (void *) tmp; 557 ba->ba_1 = (void *) tmp;
474 k++; 558 k++;
475 } 559 }
@@ -483,9 +567,9 @@ static int init_shared_mem(struct s2io_nic *nic)
483 (nic->pdev, size, &mac_control->stats_mem_phy); 567 (nic->pdev, size, &mac_control->stats_mem_phy);
484 568
485 if (!mac_control->stats_mem) { 569 if (!mac_control->stats_mem) {
486 /* 570 /*
487 * In case of failure, free_shared_mem() is called, which 571 * In case of failure, free_shared_mem() is called, which
488 * should free any memory that was alloced till the 572 * should free any memory that was alloced till the
489 * failure happened. 573 * failure happened.
490 */ 574 */
491 return -ENOMEM; 575 return -ENOMEM;
@@ -495,15 +579,14 @@ static int init_shared_mem(struct s2io_nic *nic)
495 tmp_v_addr = mac_control->stats_mem; 579 tmp_v_addr = mac_control->stats_mem;
496 mac_control->stats_info = (StatInfo_t *) tmp_v_addr; 580 mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
497 memset(tmp_v_addr, 0, size); 581 memset(tmp_v_addr, 0, size);
498
499 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name, 582 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
500 (unsigned long long) tmp_p_addr); 583 (unsigned long long) tmp_p_addr);
501 584
502 return SUCCESS; 585 return SUCCESS;
503} 586}
504 587
505/** 588/**
506 * free_shared_mem - Free the allocated Memory 589 * free_shared_mem - Free the allocated Memory
507 * @nic: Device private variable. 590 * @nic: Device private variable.
508 * Description: This function is to free all memory locations allocated by 591 * Description: This function is to free all memory locations allocated by
509 * the init_shared_mem() function and return it to the kernel. 592 * the init_shared_mem() function and return it to the kernel.
@@ -533,15 +616,19 @@ static void free_shared_mem(struct s2io_nic *nic)
533 lst_per_page); 616 lst_per_page);
534 for (j = 0; j < page_num; j++) { 617 for (j = 0; j < page_num; j++) {
535 int mem_blks = (j * lst_per_page); 618 int mem_blks = (j * lst_per_page);
536 if (!nic->list_info[i][mem_blks].list_virt_addr) 619 if ((!mac_control->fifos[i].list_info) ||
620 (!mac_control->fifos[i].list_info[mem_blks].
621 list_virt_addr))
537 break; 622 break;
538 pci_free_consistent(nic->pdev, PAGE_SIZE, 623 pci_free_consistent(nic->pdev, PAGE_SIZE,
539 nic->list_info[i][mem_blks]. 624 mac_control->fifos[i].
625 list_info[mem_blks].
540 list_virt_addr, 626 list_virt_addr,
541 nic->list_info[i][mem_blks]. 627 mac_control->fifos[i].
628 list_info[mem_blks].
542 list_phy_addr); 629 list_phy_addr);
543 } 630 }
544 kfree(nic->list_info[i]); 631 kfree(mac_control->fifos[i].list_info);
545 } 632 }
546 633
547#ifndef CONFIG_2BUFF_MODE 634#ifndef CONFIG_2BUFF_MODE
@@ -550,10 +637,12 @@ static void free_shared_mem(struct s2io_nic *nic)
550 size = SIZE_OF_BLOCK; 637 size = SIZE_OF_BLOCK;
551#endif 638#endif
552 for (i = 0; i < config->rx_ring_num; i++) { 639 for (i = 0; i < config->rx_ring_num; i++) {
553 blk_cnt = nic->block_count[i]; 640 blk_cnt = mac_control->rings[i].block_count;
554 for (j = 0; j < blk_cnt; j++) { 641 for (j = 0; j < blk_cnt; j++) {
555 tmp_v_addr = nic->rx_blocks[i][j].block_virt_addr; 642 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
556 tmp_p_addr = nic->rx_blocks[i][j].block_dma_addr; 643 block_virt_addr;
644 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
645 block_dma_addr;
557 if (tmp_v_addr == NULL) 646 if (tmp_v_addr == NULL)
558 break; 647 break;
559 pci_free_consistent(nic->pdev, size, 648 pci_free_consistent(nic->pdev, size,
@@ -566,35 +655,21 @@ static void free_shared_mem(struct s2io_nic *nic)
566 for (i = 0; i < config->rx_ring_num; i++) { 655 for (i = 0; i < config->rx_ring_num; i++) {
567 blk_cnt = 656 blk_cnt =
568 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1); 657 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
569 if (!nic->ba[i])
570 goto end_free;
571 for (j = 0; j < blk_cnt; j++) { 658 for (j = 0; j < blk_cnt; j++) {
572 int k = 0; 659 int k = 0;
573 if (!nic->ba[i][j]) { 660 if (!mac_control->rings[i].ba[j])
574 kfree(nic->ba[i]); 661 continue;
575 goto end_free;
576 }
577 while (k != MAX_RXDS_PER_BLOCK) { 662 while (k != MAX_RXDS_PER_BLOCK) {
578 buffAdd_t *ba = &nic->ba[i][j][k]; 663 buffAdd_t *ba = &mac_control->rings[i].ba[j][k];
579 if (!ba || !ba->ba_0_org || !ba->ba_1_org)
580 {
581 kfree(nic->ba[i]);
582 kfree(nic->ba[i][j]);
583 if(ba->ba_0_org)
584 kfree(ba->ba_0_org);
585 if(ba->ba_1_org)
586 kfree(ba->ba_1_org);
587 goto end_free;
588 }
589 kfree(ba->ba_0_org); 664 kfree(ba->ba_0_org);
590 kfree(ba->ba_1_org); 665 kfree(ba->ba_1_org);
591 k++; 666 k++;
592 } 667 }
593 kfree(nic->ba[i][j]); 668 kfree(mac_control->rings[i].ba[j]);
594 } 669 }
595 kfree(nic->ba[i]); 670 if (mac_control->rings[i].ba)
671 kfree(mac_control->rings[i].ba);
596 } 672 }
597end_free:
598#endif 673#endif
599 674
600 if (mac_control->stats_mem) { 675 if (mac_control->stats_mem) {
@@ -605,12 +680,93 @@ end_free:
605 } 680 }
606} 681}
607 682
608/** 683/**
609 * init_nic - Initialization of hardware 684 * s2io_verify_pci_mode -
685 */
686
687static int s2io_verify_pci_mode(nic_t *nic)
688{
689 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
690 register u64 val64 = 0;
691 int mode;
692
693 val64 = readq(&bar0->pci_mode);
694 mode = (u8)GET_PCI_MODE(val64);
695
696 if ( val64 & PCI_MODE_UNKNOWN_MODE)
697 return -1; /* Unknown PCI mode */
698 return mode;
699}
700
701
702/**
703 * s2io_print_pci_mode -
704 */
705static int s2io_print_pci_mode(nic_t *nic)
706{
707 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
708 register u64 val64 = 0;
709 int mode;
710 struct config_param *config = &nic->config;
711
712 val64 = readq(&bar0->pci_mode);
713 mode = (u8)GET_PCI_MODE(val64);
714
715 if ( val64 & PCI_MODE_UNKNOWN_MODE)
716 return -1; /* Unknown PCI mode */
717
718 if (val64 & PCI_MODE_32_BITS) {
719 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
720 } else {
721 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
722 }
723
724 switch(mode) {
725 case PCI_MODE_PCI_33:
726 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
727 config->bus_speed = 33;
728 break;
729 case PCI_MODE_PCI_66:
730 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
731 config->bus_speed = 133;
732 break;
733 case PCI_MODE_PCIX_M1_66:
734 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
735 config->bus_speed = 133; /* Herc doubles the clock rate */
736 break;
737 case PCI_MODE_PCIX_M1_100:
738 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
739 config->bus_speed = 200;
740 break;
741 case PCI_MODE_PCIX_M1_133:
742 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
743 config->bus_speed = 266;
744 break;
745 case PCI_MODE_PCIX_M2_66:
746 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
747 config->bus_speed = 133;
748 break;
749 case PCI_MODE_PCIX_M2_100:
750 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
751 config->bus_speed = 200;
752 break;
753 case PCI_MODE_PCIX_M2_133:
754 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
755 config->bus_speed = 266;
756 break;
757 default:
758 return -1; /* Unsupported bus speed */
759 }
760
761 return mode;
762}
763
764/**
765 * init_nic - Initialization of hardware
610 * @nic: device peivate variable 766 * @nic: device peivate variable
611 * Description: The function sequentially configures every block 767 * Description: The function sequentially configures every block
612 * of the H/W from their reset values. 768 * of the H/W from their reset values.
613 * Return Value: SUCCESS on success and 769 * Return Value: SUCCESS on success and
614 * '-1' on failure (endian settings incorrect). 770 * '-1' on failure (endian settings incorrect).
615 */ 771 */
616 772
@@ -626,21 +782,32 @@ static int init_nic(struct s2io_nic *nic)
626 struct config_param *config; 782 struct config_param *config;
627 int mdio_cnt = 0, dtx_cnt = 0; 783 int mdio_cnt = 0, dtx_cnt = 0;
628 unsigned long long mem_share; 784 unsigned long long mem_share;
785 int mem_size;
629 786
630 mac_control = &nic->mac_control; 787 mac_control = &nic->mac_control;
631 config = &nic->config; 788 config = &nic->config;
632 789
633 /* Initialize swapper control register */ 790 /* to set the swapper controle on the card */
634 if (s2io_set_swapper(nic)) { 791 if(s2io_set_swapper(nic)) {
635 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n"); 792 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
636 return -1; 793 return -1;
637 } 794 }
638 795
796 /*
797 * Herc requires EOI to be removed from reset before XGXS, so..
798 */
799 if (nic->device_type & XFRAME_II_DEVICE) {
800 val64 = 0xA500000000ULL;
801 writeq(val64, &bar0->sw_reset);
802 msleep(500);
803 val64 = readq(&bar0->sw_reset);
804 }
805
639 /* Remove XGXS from reset state */ 806 /* Remove XGXS from reset state */
640 val64 = 0; 807 val64 = 0;
641 writeq(val64, &bar0->sw_reset); 808 writeq(val64, &bar0->sw_reset);
642 val64 = readq(&bar0->sw_reset);
643 msleep(500); 809 msleep(500);
810 val64 = readq(&bar0->sw_reset);
644 811
645 /* Enable Receiving broadcasts */ 812 /* Enable Receiving broadcasts */
646 add = &bar0->mac_cfg; 813 add = &bar0->mac_cfg;
@@ -660,48 +827,58 @@ static int init_nic(struct s2io_nic *nic)
660 val64 = dev->mtu; 827 val64 = dev->mtu;
661 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); 828 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
662 829
663 /* 830 /*
664 * Configuring the XAUI Interface of Xena. 831 * Configuring the XAUI Interface of Xena.
665 * *************************************** 832 * ***************************************
666 * To Configure the Xena's XAUI, one has to write a series 833 * To Configure the Xena's XAUI, one has to write a series
667 * of 64 bit values into two registers in a particular 834 * of 64 bit values into two registers in a particular
668 * sequence. Hence a macro 'SWITCH_SIGN' has been defined 835 * sequence. Hence a macro 'SWITCH_SIGN' has been defined
669 * which will be defined in the array of configuration values 836 * which will be defined in the array of configuration values
670 * (default_dtx_cfg & default_mdio_cfg) at appropriate places 837 * (xena_dtx_cfg & xena_mdio_cfg) at appropriate places
671 * to switch writing from one regsiter to another. We continue 838 * to switch writing from one regsiter to another. We continue
672 * writing these values until we encounter the 'END_SIGN' macro. 839 * writing these values until we encounter the 'END_SIGN' macro.
673 * For example, After making a series of 21 writes into 840 * For example, After making a series of 21 writes into
674 * dtx_control register the 'SWITCH_SIGN' appears and hence we 841 * dtx_control register the 'SWITCH_SIGN' appears and hence we
675 * start writing into mdio_control until we encounter END_SIGN. 842 * start writing into mdio_control until we encounter END_SIGN.
676 */ 843 */
677 while (1) { 844 if (nic->device_type & XFRAME_II_DEVICE) {
678 dtx_cfg: 845 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
679 while (default_dtx_cfg[dtx_cnt] != END_SIGN) { 846 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
680 if (default_dtx_cfg[dtx_cnt] == SWITCH_SIGN) {
681 dtx_cnt++;
682 goto mdio_cfg;
683 }
684 SPECIAL_REG_WRITE(default_dtx_cfg[dtx_cnt],
685 &bar0->dtx_control, UF); 847 &bar0->dtx_control, UF);
686 val64 = readq(&bar0->dtx_control); 848 if (dtx_cnt & 0x1)
849 msleep(1); /* Necessary!! */
687 dtx_cnt++; 850 dtx_cnt++;
688 } 851 }
689 mdio_cfg: 852 } else {
690 while (default_mdio_cfg[mdio_cnt] != END_SIGN) { 853 while (1) {
691 if (default_mdio_cfg[mdio_cnt] == SWITCH_SIGN) { 854 dtx_cfg:
855 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
856 if (xena_dtx_cfg[dtx_cnt] == SWITCH_SIGN) {
857 dtx_cnt++;
858 goto mdio_cfg;
859 }
860 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
861 &bar0->dtx_control, UF);
862 val64 = readq(&bar0->dtx_control);
863 dtx_cnt++;
864 }
865 mdio_cfg:
866 while (xena_mdio_cfg[mdio_cnt] != END_SIGN) {
867 if (xena_mdio_cfg[mdio_cnt] == SWITCH_SIGN) {
868 mdio_cnt++;
869 goto dtx_cfg;
870 }
871 SPECIAL_REG_WRITE(xena_mdio_cfg[mdio_cnt],
872 &bar0->mdio_control, UF);
873 val64 = readq(&bar0->mdio_control);
692 mdio_cnt++; 874 mdio_cnt++;
875 }
876 if ((xena_dtx_cfg[dtx_cnt] == END_SIGN) &&
877 (xena_mdio_cfg[mdio_cnt] == END_SIGN)) {
878 break;
879 } else {
693 goto dtx_cfg; 880 goto dtx_cfg;
694 } 881 }
695 SPECIAL_REG_WRITE(default_mdio_cfg[mdio_cnt],
696 &bar0->mdio_control, UF);
697 val64 = readq(&bar0->mdio_control);
698 mdio_cnt++;
699 }
700 if ((default_dtx_cfg[dtx_cnt] == END_SIGN) &&
701 (default_mdio_cfg[mdio_cnt] == END_SIGN)) {
702 break;
703 } else {
704 goto dtx_cfg;
705 } 882 }
706 } 883 }
707 884
@@ -748,12 +925,20 @@ static int init_nic(struct s2io_nic *nic)
748 val64 |= BIT(0); /* To enable the FIFO partition. */ 925 val64 |= BIT(0); /* To enable the FIFO partition. */
749 writeq(val64, &bar0->tx_fifo_partition_0); 926 writeq(val64, &bar0->tx_fifo_partition_0);
750 927
928 /*
929 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
930 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
931 */
932 if ((nic->device_type == XFRAME_I_DEVICE) &&
933 (get_xena_rev_id(nic->pdev) < 4))
934 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
935
751 val64 = readq(&bar0->tx_fifo_partition_0); 936 val64 = readq(&bar0->tx_fifo_partition_0);
752 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n", 937 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
753 &bar0->tx_fifo_partition_0, (unsigned long long) val64); 938 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
754 939
755 /* 940 /*
756 * Initialization of Tx_PA_CONFIG register to ignore packet 941 * Initialization of Tx_PA_CONFIG register to ignore packet
757 * integrity checking. 942 * integrity checking.
758 */ 943 */
759 val64 = readq(&bar0->tx_pa_cfg); 944 val64 = readq(&bar0->tx_pa_cfg);
@@ -770,85 +955,304 @@ static int init_nic(struct s2io_nic *nic)
770 } 955 }
771 writeq(val64, &bar0->rx_queue_priority); 956 writeq(val64, &bar0->rx_queue_priority);
772 957
773 /* 958 /*
774 * Allocating equal share of memory to all the 959 * Allocating equal share of memory to all the
775 * configured Rings. 960 * configured Rings.
776 */ 961 */
777 val64 = 0; 962 val64 = 0;
963 if (nic->device_type & XFRAME_II_DEVICE)
964 mem_size = 32;
965 else
966 mem_size = 64;
967
778 for (i = 0; i < config->rx_ring_num; i++) { 968 for (i = 0; i < config->rx_ring_num; i++) {
779 switch (i) { 969 switch (i) {
780 case 0: 970 case 0:
781 mem_share = (64 / config->rx_ring_num + 971 mem_share = (mem_size / config->rx_ring_num +
782 64 % config->rx_ring_num); 972 mem_size % config->rx_ring_num);
783 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share); 973 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
784 continue; 974 continue;
785 case 1: 975 case 1:
786 mem_share = (64 / config->rx_ring_num); 976 mem_share = (mem_size / config->rx_ring_num);
787 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share); 977 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
788 continue; 978 continue;
789 case 2: 979 case 2:
790 mem_share = (64 / config->rx_ring_num); 980 mem_share = (mem_size / config->rx_ring_num);
791 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share); 981 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
792 continue; 982 continue;
793 case 3: 983 case 3:
794 mem_share = (64 / config->rx_ring_num); 984 mem_share = (mem_size / config->rx_ring_num);
795 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share); 985 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
796 continue; 986 continue;
797 case 4: 987 case 4:
798 mem_share = (64 / config->rx_ring_num); 988 mem_share = (mem_size / config->rx_ring_num);
799 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share); 989 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
800 continue; 990 continue;
801 case 5: 991 case 5:
802 mem_share = (64 / config->rx_ring_num); 992 mem_share = (mem_size / config->rx_ring_num);
803 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share); 993 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
804 continue; 994 continue;
805 case 6: 995 case 6:
806 mem_share = (64 / config->rx_ring_num); 996 mem_share = (mem_size / config->rx_ring_num);
807 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share); 997 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
808 continue; 998 continue;
809 case 7: 999 case 7:
810 mem_share = (64 / config->rx_ring_num); 1000 mem_share = (mem_size / config->rx_ring_num);
811 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share); 1001 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
812 continue; 1002 continue;
813 } 1003 }
814 } 1004 }
815 writeq(val64, &bar0->rx_queue_cfg); 1005 writeq(val64, &bar0->rx_queue_cfg);
816 1006
817 /* 1007 /*
818 * Initializing the Tx round robin registers to 0. 1008 * Filling Tx round robin registers
819 * Filling Tx and Rx round robin registers as per the 1009 * as per the number of FIFOs
820 * number of FIFOs and Rings is still TODO.
821 */
822 writeq(0, &bar0->tx_w_round_robin_0);
823 writeq(0, &bar0->tx_w_round_robin_1);
824 writeq(0, &bar0->tx_w_round_robin_2);
825 writeq(0, &bar0->tx_w_round_robin_3);
826 writeq(0, &bar0->tx_w_round_robin_4);
827
828 /*
829 * TODO
830 * Disable Rx steering. Hard coding all packets be steered to
831 * Queue 0 for now.
832 */ 1010 */
833 val64 = 0x8080808080808080ULL; 1011 switch (config->tx_fifo_num) {
834 writeq(val64, &bar0->rts_qos_steering); 1012 case 1:
1013 val64 = 0x0000000000000000ULL;
1014 writeq(val64, &bar0->tx_w_round_robin_0);
1015 writeq(val64, &bar0->tx_w_round_robin_1);
1016 writeq(val64, &bar0->tx_w_round_robin_2);
1017 writeq(val64, &bar0->tx_w_round_robin_3);
1018 writeq(val64, &bar0->tx_w_round_robin_4);
1019 break;
1020 case 2:
1021 val64 = 0x0000010000010000ULL;
1022 writeq(val64, &bar0->tx_w_round_robin_0);
1023 val64 = 0x0100000100000100ULL;
1024 writeq(val64, &bar0->tx_w_round_robin_1);
1025 val64 = 0x0001000001000001ULL;
1026 writeq(val64, &bar0->tx_w_round_robin_2);
1027 val64 = 0x0000010000010000ULL;
1028 writeq(val64, &bar0->tx_w_round_robin_3);
1029 val64 = 0x0100000000000000ULL;
1030 writeq(val64, &bar0->tx_w_round_robin_4);
1031 break;
1032 case 3:
1033 val64 = 0x0001000102000001ULL;
1034 writeq(val64, &bar0->tx_w_round_robin_0);
1035 val64 = 0x0001020000010001ULL;
1036 writeq(val64, &bar0->tx_w_round_robin_1);
1037 val64 = 0x0200000100010200ULL;
1038 writeq(val64, &bar0->tx_w_round_robin_2);
1039 val64 = 0x0001000102000001ULL;
1040 writeq(val64, &bar0->tx_w_round_robin_3);
1041 val64 = 0x0001020000000000ULL;
1042 writeq(val64, &bar0->tx_w_round_robin_4);
1043 break;
1044 case 4:
1045 val64 = 0x0001020300010200ULL;
1046 writeq(val64, &bar0->tx_w_round_robin_0);
1047 val64 = 0x0100000102030001ULL;
1048 writeq(val64, &bar0->tx_w_round_robin_1);
1049 val64 = 0x0200010000010203ULL;
1050 writeq(val64, &bar0->tx_w_round_robin_2);
1051 val64 = 0x0001020001000001ULL;
1052 writeq(val64, &bar0->tx_w_round_robin_3);
1053 val64 = 0x0203000100000000ULL;
1054 writeq(val64, &bar0->tx_w_round_robin_4);
1055 break;
1056 case 5:
1057 val64 = 0x0001000203000102ULL;
1058 writeq(val64, &bar0->tx_w_round_robin_0);
1059 val64 = 0x0001020001030004ULL;
1060 writeq(val64, &bar0->tx_w_round_robin_1);
1061 val64 = 0x0001000203000102ULL;
1062 writeq(val64, &bar0->tx_w_round_robin_2);
1063 val64 = 0x0001020001030004ULL;
1064 writeq(val64, &bar0->tx_w_round_robin_3);
1065 val64 = 0x0001000000000000ULL;
1066 writeq(val64, &bar0->tx_w_round_robin_4);
1067 break;
1068 case 6:
1069 val64 = 0x0001020304000102ULL;
1070 writeq(val64, &bar0->tx_w_round_robin_0);
1071 val64 = 0x0304050001020001ULL;
1072 writeq(val64, &bar0->tx_w_round_robin_1);
1073 val64 = 0x0203000100000102ULL;
1074 writeq(val64, &bar0->tx_w_round_robin_2);
1075 val64 = 0x0304000102030405ULL;
1076 writeq(val64, &bar0->tx_w_round_robin_3);
1077 val64 = 0x0001000200000000ULL;
1078 writeq(val64, &bar0->tx_w_round_robin_4);
1079 break;
1080 case 7:
1081 val64 = 0x0001020001020300ULL;
1082 writeq(val64, &bar0->tx_w_round_robin_0);
1083 val64 = 0x0102030400010203ULL;
1084 writeq(val64, &bar0->tx_w_round_robin_1);
1085 val64 = 0x0405060001020001ULL;
1086 writeq(val64, &bar0->tx_w_round_robin_2);
1087 val64 = 0x0304050000010200ULL;
1088 writeq(val64, &bar0->tx_w_round_robin_3);
1089 val64 = 0x0102030000000000ULL;
1090 writeq(val64, &bar0->tx_w_round_robin_4);
1091 break;
1092 case 8:
1093 val64 = 0x0001020300040105ULL;
1094 writeq(val64, &bar0->tx_w_round_robin_0);
1095 val64 = 0x0200030106000204ULL;
1096 writeq(val64, &bar0->tx_w_round_robin_1);
1097 val64 = 0x0103000502010007ULL;
1098 writeq(val64, &bar0->tx_w_round_robin_2);
1099 val64 = 0x0304010002060500ULL;
1100 writeq(val64, &bar0->tx_w_round_robin_3);
1101 val64 = 0x0103020400000000ULL;
1102 writeq(val64, &bar0->tx_w_round_robin_4);
1103 break;
1104 }
1105
1106 /* Filling the Rx round robin registers as per the
1107 * number of Rings and steering based on QoS.
1108 */
1109 switch (config->rx_ring_num) {
1110 case 1:
1111 val64 = 0x8080808080808080ULL;
1112 writeq(val64, &bar0->rts_qos_steering);
1113 break;
1114 case 2:
1115 val64 = 0x0000010000010000ULL;
1116 writeq(val64, &bar0->rx_w_round_robin_0);
1117 val64 = 0x0100000100000100ULL;
1118 writeq(val64, &bar0->rx_w_round_robin_1);
1119 val64 = 0x0001000001000001ULL;
1120 writeq(val64, &bar0->rx_w_round_robin_2);
1121 val64 = 0x0000010000010000ULL;
1122 writeq(val64, &bar0->rx_w_round_robin_3);
1123 val64 = 0x0100000000000000ULL;
1124 writeq(val64, &bar0->rx_w_round_robin_4);
1125
1126 val64 = 0x8080808040404040ULL;
1127 writeq(val64, &bar0->rts_qos_steering);
1128 break;
1129 case 3:
1130 val64 = 0x0001000102000001ULL;
1131 writeq(val64, &bar0->rx_w_round_robin_0);
1132 val64 = 0x0001020000010001ULL;
1133 writeq(val64, &bar0->rx_w_round_robin_1);
1134 val64 = 0x0200000100010200ULL;
1135 writeq(val64, &bar0->rx_w_round_robin_2);
1136 val64 = 0x0001000102000001ULL;
1137 writeq(val64, &bar0->rx_w_round_robin_3);
1138 val64 = 0x0001020000000000ULL;
1139 writeq(val64, &bar0->rx_w_round_robin_4);
1140
1141 val64 = 0x8080804040402020ULL;
1142 writeq(val64, &bar0->rts_qos_steering);
1143 break;
1144 case 4:
1145 val64 = 0x0001020300010200ULL;
1146 writeq(val64, &bar0->rx_w_round_robin_0);
1147 val64 = 0x0100000102030001ULL;
1148 writeq(val64, &bar0->rx_w_round_robin_1);
1149 val64 = 0x0200010000010203ULL;
1150 writeq(val64, &bar0->rx_w_round_robin_2);
1151 val64 = 0x0001020001000001ULL;
1152 writeq(val64, &bar0->rx_w_round_robin_3);
1153 val64 = 0x0203000100000000ULL;
1154 writeq(val64, &bar0->rx_w_round_robin_4);
1155
1156 val64 = 0x8080404020201010ULL;
1157 writeq(val64, &bar0->rts_qos_steering);
1158 break;
1159 case 5:
1160 val64 = 0x0001000203000102ULL;
1161 writeq(val64, &bar0->rx_w_round_robin_0);
1162 val64 = 0x0001020001030004ULL;
1163 writeq(val64, &bar0->rx_w_round_robin_1);
1164 val64 = 0x0001000203000102ULL;
1165 writeq(val64, &bar0->rx_w_round_robin_2);
1166 val64 = 0x0001020001030004ULL;
1167 writeq(val64, &bar0->rx_w_round_robin_3);
1168 val64 = 0x0001000000000000ULL;
1169 writeq(val64, &bar0->rx_w_round_robin_4);
1170
1171 val64 = 0x8080404020201008ULL;
1172 writeq(val64, &bar0->rts_qos_steering);
1173 break;
1174 case 6:
1175 val64 = 0x0001020304000102ULL;
1176 writeq(val64, &bar0->rx_w_round_robin_0);
1177 val64 = 0x0304050001020001ULL;
1178 writeq(val64, &bar0->rx_w_round_robin_1);
1179 val64 = 0x0203000100000102ULL;
1180 writeq(val64, &bar0->rx_w_round_robin_2);
1181 val64 = 0x0304000102030405ULL;
1182 writeq(val64, &bar0->rx_w_round_robin_3);
1183 val64 = 0x0001000200000000ULL;
1184 writeq(val64, &bar0->rx_w_round_robin_4);
1185
1186 val64 = 0x8080404020100804ULL;
1187 writeq(val64, &bar0->rts_qos_steering);
1188 break;
1189 case 7:
1190 val64 = 0x0001020001020300ULL;
1191 writeq(val64, &bar0->rx_w_round_robin_0);
1192 val64 = 0x0102030400010203ULL;
1193 writeq(val64, &bar0->rx_w_round_robin_1);
1194 val64 = 0x0405060001020001ULL;
1195 writeq(val64, &bar0->rx_w_round_robin_2);
1196 val64 = 0x0304050000010200ULL;
1197 writeq(val64, &bar0->rx_w_round_robin_3);
1198 val64 = 0x0102030000000000ULL;
1199 writeq(val64, &bar0->rx_w_round_robin_4);
1200
1201 val64 = 0x8080402010080402ULL;
1202 writeq(val64, &bar0->rts_qos_steering);
1203 break;
1204 case 8:
1205 val64 = 0x0001020300040105ULL;
1206 writeq(val64, &bar0->rx_w_round_robin_0);
1207 val64 = 0x0200030106000204ULL;
1208 writeq(val64, &bar0->rx_w_round_robin_1);
1209 val64 = 0x0103000502010007ULL;
1210 writeq(val64, &bar0->rx_w_round_robin_2);
1211 val64 = 0x0304010002060500ULL;
1212 writeq(val64, &bar0->rx_w_round_robin_3);
1213 val64 = 0x0103020400000000ULL;
1214 writeq(val64, &bar0->rx_w_round_robin_4);
1215
1216 val64 = 0x8040201008040201ULL;
1217 writeq(val64, &bar0->rts_qos_steering);
1218 break;
1219 }
835 1220
836 /* UDP Fix */ 1221 /* UDP Fix */
837 val64 = 0; 1222 val64 = 0;
838 for (i = 1; i < 8; i++) 1223 for (i = 0; i < 8; i++)
1224 writeq(val64, &bar0->rts_frm_len_n[i]);
1225
1226 /* Set the default rts frame length for the rings configured */
1227 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1228 for (i = 0 ; i < config->rx_ring_num ; i++)
839 writeq(val64, &bar0->rts_frm_len_n[i]); 1229 writeq(val64, &bar0->rts_frm_len_n[i]);
840 1230
841 /* Set rts_frm_len register for fifo 0 */ 1231 /* Set the frame length for the configured rings
842 writeq(MAC_RTS_FRM_LEN_SET(dev->mtu + 22), 1232 * desired by the user
843 &bar0->rts_frm_len_n[0]); 1233 */
1234 for (i = 0; i < config->rx_ring_num; i++) {
1235 /* If rts_frm_len[i] == 0 then it is assumed that user not
1236 * specified frame length steering.
1237 * If the user provides the frame length then program
1238 * the rts_frm_len register for those values or else
1239 * leave it as it is.
1240 */
1241 if (rts_frm_len[i] != 0) {
1242 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1243 &bar0->rts_frm_len_n[i]);
1244 }
1245 }
844 1246
845 /* Enable statistics */ 1247 /* Program statistics memory */
846 writeq(mac_control->stats_mem_phy, &bar0->stat_addr); 1248 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
847 val64 = SET_UPDT_PERIOD(Stats_refresh_time) |
848 STAT_CFG_STAT_RO | STAT_CFG_STAT_EN;
849 writeq(val64, &bar0->stat_cfg);
850 1249
851 /* 1250 if (nic->device_type == XFRAME_II_DEVICE) {
1251 val64 = STAT_BC(0x320);
1252 writeq(val64, &bar0->stat_byte_cnt);
1253 }
1254
1255 /*
852 * Initializing the sampling rate for the device to calculate the 1256 * Initializing the sampling rate for the device to calculate the
853 * bandwidth utilization. 1257 * bandwidth utilization.
854 */ 1258 */
@@ -857,30 +1261,38 @@ static int init_nic(struct s2io_nic *nic)
857 writeq(val64, &bar0->mac_link_util); 1261 writeq(val64, &bar0->mac_link_util);
858 1262
859 1263
860 /* 1264 /*
861 * Initializing the Transmit and Receive Traffic Interrupt 1265 * Initializing the Transmit and Receive Traffic Interrupt
862 * Scheme. 1266 * Scheme.
863 */ 1267 */
864 /* TTI Initialization. Default Tx timer gets us about 1268 /*
1269 * TTI Initialization. Default Tx timer gets us about
865 * 250 interrupts per sec. Continuous interrupts are enabled 1270 * 250 interrupts per sec. Continuous interrupts are enabled
866 * by default. 1271 * by default.
867 */ 1272 */
868 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078) | 1273 if (nic->device_type == XFRAME_II_DEVICE) {
869 TTI_DATA1_MEM_TX_URNG_A(0xA) | 1274 int count = (nic->config.bus_speed * 125)/2;
1275 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1276 } else {
1277
1278 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1279 }
1280 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
870 TTI_DATA1_MEM_TX_URNG_B(0x10) | 1281 TTI_DATA1_MEM_TX_URNG_B(0x10) |
871 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN | 1282 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
872 TTI_DATA1_MEM_TX_TIMER_CI_EN; 1283 if (use_continuous_tx_intrs)
1284 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
873 writeq(val64, &bar0->tti_data1_mem); 1285 writeq(val64, &bar0->tti_data1_mem);
874 1286
875 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | 1287 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
876 TTI_DATA2_MEM_TX_UFC_B(0x20) | 1288 TTI_DATA2_MEM_TX_UFC_B(0x20) |
877 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80); 1289 TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
878 writeq(val64, &bar0->tti_data2_mem); 1290 writeq(val64, &bar0->tti_data2_mem);
879 1291
880 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD; 1292 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
881 writeq(val64, &bar0->tti_command_mem); 1293 writeq(val64, &bar0->tti_command_mem);
882 1294
883 /* 1295 /*
884 * Once the operation completes, the Strobe bit of the command 1296 * Once the operation completes, the Strobe bit of the command
885 * register will be reset. We poll for this particular condition 1297 * register will be reset. We poll for this particular condition
886 * We wait for a maximum of 500ms for the operation to complete, 1298 * We wait for a maximum of 500ms for the operation to complete,
@@ -901,52 +1313,97 @@ static int init_nic(struct s2io_nic *nic)
901 time++; 1313 time++;
902 } 1314 }
903 1315
904 /* RTI Initialization */ 1316 if (nic->config.bimodal) {
905 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF) | 1317 int k = 0;
906 RTI_DATA1_MEM_RX_URNG_A(0xA) | 1318 for (k = 0; k < config->rx_ring_num; k++) {
907 RTI_DATA1_MEM_RX_URNG_B(0x10) | 1319 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
908 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN; 1320 val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1321 writeq(val64, &bar0->tti_command_mem);
1322
1323 /*
1324 * Once the operation completes, the Strobe bit of the command
1325 * register will be reset. We poll for this particular condition
1326 * We wait for a maximum of 500ms for the operation to complete,
1327 * if it's not complete by then we return error.
1328 */
1329 time = 0;
1330 while (TRUE) {
1331 val64 = readq(&bar0->tti_command_mem);
1332 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1333 break;
1334 }
1335 if (time > 10) {
1336 DBG_PRINT(ERR_DBG,
1337 "%s: TTI init Failed\n",
1338 dev->name);
1339 return -1;
1340 }
1341 time++;
1342 msleep(50);
1343 }
1344 }
1345 } else {
909 1346
910 writeq(val64, &bar0->rti_data1_mem); 1347 /* RTI Initialization */
1348 if (nic->device_type == XFRAME_II_DEVICE) {
1349 /*
1350 * Programmed to generate Apprx 500 Intrs per
1351 * second
1352 */
1353 int count = (nic->config.bus_speed * 125)/4;
1354 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1355 } else {
1356 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1357 }
1358 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1359 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1360 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
911 1361
912 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) | 1362 writeq(val64, &bar0->rti_data1_mem);
913 RTI_DATA2_MEM_RX_UFC_B(0x2) |
914 RTI_DATA2_MEM_RX_UFC_C(0x40) | RTI_DATA2_MEM_RX_UFC_D(0x80);
915 writeq(val64, &bar0->rti_data2_mem);
916 1363
917 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD; 1364 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
918 writeq(val64, &bar0->rti_command_mem); 1365 RTI_DATA2_MEM_RX_UFC_B(0x2) |
1366 RTI_DATA2_MEM_RX_UFC_C(0x40) | RTI_DATA2_MEM_RX_UFC_D(0x80);
1367 writeq(val64, &bar0->rti_data2_mem);
919 1368
920 /* 1369 for (i = 0; i < config->rx_ring_num; i++) {
921 * Once the operation completes, the Strobe bit of the command 1370 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
922 * register will be reset. We poll for this particular condition 1371 | RTI_CMD_MEM_OFFSET(i);
923 * We wait for a maximum of 500ms for the operation to complete, 1372 writeq(val64, &bar0->rti_command_mem);
924 * if it's not complete by then we return error. 1373
925 */ 1374 /*
926 time = 0; 1375 * Once the operation completes, the Strobe bit of the
927 while (TRUE) { 1376 * command register will be reset. We poll for this
928 val64 = readq(&bar0->rti_command_mem); 1377 * particular condition. We wait for a maximum of 500ms
929 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) { 1378 * for the operation to complete, if it's not complete
930 break; 1379 * by then we return error.
931 } 1380 */
932 if (time > 10) { 1381 time = 0;
933 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n", 1382 while (TRUE) {
934 dev->name); 1383 val64 = readq(&bar0->rti_command_mem);
935 return -1; 1384 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1385 break;
1386 }
1387 if (time > 10) {
1388 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1389 dev->name);
1390 return -1;
1391 }
1392 time++;
1393 msleep(50);
1394 }
936 } 1395 }
937 time++;
938 msleep(50);
939 } 1396 }
940 1397
941 /* 1398 /*
942 * Initializing proper values as Pause threshold into all 1399 * Initializing proper values as Pause threshold into all
943 * the 8 Queues on Rx side. 1400 * the 8 Queues on Rx side.
944 */ 1401 */
945 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3); 1402 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
946 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7); 1403 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
947 1404
948 /* Disable RMAC PAD STRIPPING */ 1405 /* Disable RMAC PAD STRIPPING */
949 add = &bar0->mac_cfg; 1406 add = (void *) &bar0->mac_cfg;
950 val64 = readq(&bar0->mac_cfg); 1407 val64 = readq(&bar0->mac_cfg);
951 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD); 1408 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
952 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); 1409 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
@@ -955,8 +1412,8 @@ static int init_nic(struct s2io_nic *nic)
955 writel((u32) (val64 >> 32), (add + 4)); 1412 writel((u32) (val64 >> 32), (add + 4));
956 val64 = readq(&bar0->mac_cfg); 1413 val64 = readq(&bar0->mac_cfg);
957 1414
958 /* 1415 /*
959 * Set the time value to be inserted in the pause frame 1416 * Set the time value to be inserted in the pause frame
960 * generated by xena. 1417 * generated by xena.
961 */ 1418 */
962 val64 = readq(&bar0->rmac_pause_cfg); 1419 val64 = readq(&bar0->rmac_pause_cfg);
@@ -964,7 +1421,7 @@ static int init_nic(struct s2io_nic *nic)
964 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time); 1421 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
965 writeq(val64, &bar0->rmac_pause_cfg); 1422 writeq(val64, &bar0->rmac_pause_cfg);
966 1423
967 /* 1424 /*
968 * Set the Threshold Limit for Generating the pause frame 1425 * Set the Threshold Limit for Generating the pause frame
969 * If the amount of data in any Queue exceeds ratio of 1426 * If the amount of data in any Queue exceeds ratio of
970 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256 1427 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
@@ -988,25 +1445,54 @@ static int init_nic(struct s2io_nic *nic)
988 } 1445 }
989 writeq(val64, &bar0->mc_pause_thresh_q4q7); 1446 writeq(val64, &bar0->mc_pause_thresh_q4q7);
990 1447
991 /* 1448 /*
992 * TxDMA will stop Read request if the number of read split has 1449 * TxDMA will stop Read request if the number of read split has
993 * exceeded the limit pointed by shared_splits 1450 * exceeded the limit pointed by shared_splits
994 */ 1451 */
995 val64 = readq(&bar0->pic_control); 1452 val64 = readq(&bar0->pic_control);
996 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits); 1453 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
997 writeq(val64, &bar0->pic_control); 1454 writeq(val64, &bar0->pic_control);
998 1455
1456 /*
1457 * Programming the Herc to split every write transaction
1458 * that does not start on an ADB to reduce disconnects.
1459 */
1460 if (nic->device_type == XFRAME_II_DEVICE) {
1461 val64 = WREQ_SPLIT_MASK_SET_MASK(255);
1462 writeq(val64, &bar0->wreq_split_mask);
1463 }
1464
1465 /* Setting Link stability period to 64 ms */
1466 if (nic->device_type == XFRAME_II_DEVICE) {
1467 val64 = MISC_LINK_STABILITY_PRD(3);
1468 writeq(val64, &bar0->misc_control);
1469 }
1470
999 return SUCCESS; 1471 return SUCCESS;
1000} 1472}
1473#define LINK_UP_DOWN_INTERRUPT 1
1474#define MAC_RMAC_ERR_TIMER 2
1001 1475
1002/** 1476#if defined(CONFIG_MSI_MODE) || defined(CONFIG_MSIX_MODE)
1003 * en_dis_able_nic_intrs - Enable or Disable the interrupts 1477#define s2io_link_fault_indication(x) MAC_RMAC_ERR_TIMER
1478#else
1479int s2io_link_fault_indication(nic_t *nic)
1480{
1481 if (nic->device_type == XFRAME_II_DEVICE)
1482 return LINK_UP_DOWN_INTERRUPT;
1483 else
1484 return MAC_RMAC_ERR_TIMER;
1485}
1486#endif
1487
1488/**
1489 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1004 * @nic: device private variable, 1490 * @nic: device private variable,
1005 * @mask: A mask indicating which Intr block must be modified and, 1491 * @mask: A mask indicating which Intr block must be modified and,
1006 * @flag: A flag indicating whether to enable or disable the Intrs. 1492 * @flag: A flag indicating whether to enable or disable the Intrs.
1007 * Description: This function will either disable or enable the interrupts 1493 * Description: This function will either disable or enable the interrupts
1008 * depending on the flag argument. The mask argument can be used to 1494 * depending on the flag argument. The mask argument can be used to
1009 * enable/disable any Intr block. 1495 * enable/disable any Intr block.
1010 * Return Value: NONE. 1496 * Return Value: NONE.
1011 */ 1497 */
1012 1498
@@ -1024,20 +1510,31 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1024 temp64 = readq(&bar0->general_int_mask); 1510 temp64 = readq(&bar0->general_int_mask);
1025 temp64 &= ~((u64) val64); 1511 temp64 &= ~((u64) val64);
1026 writeq(temp64, &bar0->general_int_mask); 1512 writeq(temp64, &bar0->general_int_mask);
1027 /* 1513 /*
1028 * Disabled all PCIX, Flash, MDIO, IIC and GPIO 1514 * If Hercules adapter enable GPIO otherwise
1029 * interrupts for now. 1515 * disabled all PCIX, Flash, MDIO, IIC and GPIO
1030 * TODO 1516 * interrupts for now.
1517 * TODO
1031 */ 1518 */
1032 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); 1519 if (s2io_link_fault_indication(nic) ==
1033 /* 1520 LINK_UP_DOWN_INTERRUPT ) {
1521 temp64 = readq(&bar0->pic_int_mask);
1522 temp64 &= ~((u64) PIC_INT_GPIO);
1523 writeq(temp64, &bar0->pic_int_mask);
1524 temp64 = readq(&bar0->gpio_int_mask);
1525 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1526 writeq(temp64, &bar0->gpio_int_mask);
1527 } else {
1528 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1529 }
1530 /*
1034 * No MSI Support is available presently, so TTI and 1531 * No MSI Support is available presently, so TTI and
1035 * RTI interrupts are also disabled. 1532 * RTI interrupts are also disabled.
1036 */ 1533 */
1037 } else if (flag == DISABLE_INTRS) { 1534 } else if (flag == DISABLE_INTRS) {
1038 /* 1535 /*
1039 * Disable PIC Intrs in the general 1536 * Disable PIC Intrs in the general
1040 * intr mask register 1537 * intr mask register
1041 */ 1538 */
1042 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); 1539 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1043 temp64 = readq(&bar0->general_int_mask); 1540 temp64 = readq(&bar0->general_int_mask);
@@ -1055,27 +1552,27 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1055 temp64 = readq(&bar0->general_int_mask); 1552 temp64 = readq(&bar0->general_int_mask);
1056 temp64 &= ~((u64) val64); 1553 temp64 &= ~((u64) val64);
1057 writeq(temp64, &bar0->general_int_mask); 1554 writeq(temp64, &bar0->general_int_mask);
1058 /* 1555 /*
1059 * Keep all interrupts other than PFC interrupt 1556 * Keep all interrupts other than PFC interrupt
1060 * and PCC interrupt disabled in DMA level. 1557 * and PCC interrupt disabled in DMA level.
1061 */ 1558 */
1062 val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M | 1559 val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1063 TXDMA_PCC_INT_M); 1560 TXDMA_PCC_INT_M);
1064 writeq(val64, &bar0->txdma_int_mask); 1561 writeq(val64, &bar0->txdma_int_mask);
1065 /* 1562 /*
1066 * Enable only the MISC error 1 interrupt in PFC block 1563 * Enable only the MISC error 1 interrupt in PFC block
1067 */ 1564 */
1068 val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1); 1565 val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1069 writeq(val64, &bar0->pfc_err_mask); 1566 writeq(val64, &bar0->pfc_err_mask);
1070 /* 1567 /*
1071 * Enable only the FB_ECC error interrupt in PCC block 1568 * Enable only the FB_ECC error interrupt in PCC block
1072 */ 1569 */
1073 val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR); 1570 val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1074 writeq(val64, &bar0->pcc_err_mask); 1571 writeq(val64, &bar0->pcc_err_mask);
1075 } else if (flag == DISABLE_INTRS) { 1572 } else if (flag == DISABLE_INTRS) {
1076 /* 1573 /*
1077 * Disable TxDMA Intrs in the general intr mask 1574 * Disable TxDMA Intrs in the general intr mask
1078 * register 1575 * register
1079 */ 1576 */
1080 writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask); 1577 writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1081 writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask); 1578 writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
@@ -1093,15 +1590,15 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1093 temp64 = readq(&bar0->general_int_mask); 1590 temp64 = readq(&bar0->general_int_mask);
1094 temp64 &= ~((u64) val64); 1591 temp64 &= ~((u64) val64);
1095 writeq(temp64, &bar0->general_int_mask); 1592 writeq(temp64, &bar0->general_int_mask);
1096 /* 1593 /*
1097 * All RxDMA block interrupts are disabled for now 1594 * All RxDMA block interrupts are disabled for now
1098 * TODO 1595 * TODO
1099 */ 1596 */
1100 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask); 1597 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1101 } else if (flag == DISABLE_INTRS) { 1598 } else if (flag == DISABLE_INTRS) {
1102 /* 1599 /*
1103 * Disable RxDMA Intrs in the general intr mask 1600 * Disable RxDMA Intrs in the general intr mask
1104 * register 1601 * register
1105 */ 1602 */
1106 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask); 1603 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1107 temp64 = readq(&bar0->general_int_mask); 1604 temp64 = readq(&bar0->general_int_mask);
@@ -1118,22 +1615,13 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1118 temp64 = readq(&bar0->general_int_mask); 1615 temp64 = readq(&bar0->general_int_mask);
1119 temp64 &= ~((u64) val64); 1616 temp64 &= ~((u64) val64);
1120 writeq(temp64, &bar0->general_int_mask); 1617 writeq(temp64, &bar0->general_int_mask);
1121 /* 1618 /*
1122 * All MAC block error interrupts are disabled for now 1619 * All MAC block error interrupts are disabled for now
1123 * except the link status change interrupt.
1124 * TODO 1620 * TODO
1125 */ 1621 */
1126 val64 = MAC_INT_STATUS_RMAC_INT;
1127 temp64 = readq(&bar0->mac_int_mask);
1128 temp64 &= ~((u64) val64);
1129 writeq(temp64, &bar0->mac_int_mask);
1130
1131 val64 = readq(&bar0->mac_rmac_err_mask);
1132 val64 &= ~((u64) RMAC_LINK_STATE_CHANGE_INT);
1133 writeq(val64, &bar0->mac_rmac_err_mask);
1134 } else if (flag == DISABLE_INTRS) { 1622 } else if (flag == DISABLE_INTRS) {
1135 /* 1623 /*
1136 * Disable MAC Intrs in the general intr mask register 1624 * Disable MAC Intrs in the general intr mask register
1137 */ 1625 */
1138 writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask); 1626 writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1139 writeq(DISABLE_ALL_INTRS, 1627 writeq(DISABLE_ALL_INTRS,
@@ -1152,14 +1640,14 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1152 temp64 = readq(&bar0->general_int_mask); 1640 temp64 = readq(&bar0->general_int_mask);
1153 temp64 &= ~((u64) val64); 1641 temp64 &= ~((u64) val64);
1154 writeq(temp64, &bar0->general_int_mask); 1642 writeq(temp64, &bar0->general_int_mask);
1155 /* 1643 /*
1156 * All XGXS block error interrupts are disabled for now 1644 * All XGXS block error interrupts are disabled for now
1157 * TODO 1645 * TODO
1158 */ 1646 */
1159 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask); 1647 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1160 } else if (flag == DISABLE_INTRS) { 1648 } else if (flag == DISABLE_INTRS) {
1161 /* 1649 /*
1162 * Disable MC Intrs in the general intr mask register 1650 * Disable MC Intrs in the general intr mask register
1163 */ 1651 */
1164 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask); 1652 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1165 temp64 = readq(&bar0->general_int_mask); 1653 temp64 = readq(&bar0->general_int_mask);
@@ -1175,11 +1663,11 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1175 temp64 = readq(&bar0->general_int_mask); 1663 temp64 = readq(&bar0->general_int_mask);
1176 temp64 &= ~((u64) val64); 1664 temp64 &= ~((u64) val64);
1177 writeq(temp64, &bar0->general_int_mask); 1665 writeq(temp64, &bar0->general_int_mask);
1178 /* 1666 /*
1179 * All MC block error interrupts are disabled for now 1667 * Enable all MC Intrs.
1180 * TODO
1181 */ 1668 */
1182 writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask); 1669 writeq(0x0, &bar0->mc_int_mask);
1670 writeq(0x0, &bar0->mc_err_mask);
1183 } else if (flag == DISABLE_INTRS) { 1671 } else if (flag == DISABLE_INTRS) {
1184 /* 1672 /*
1185 * Disable MC Intrs in the general intr mask register 1673 * Disable MC Intrs in the general intr mask register
@@ -1199,14 +1687,14 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1199 temp64 = readq(&bar0->general_int_mask); 1687 temp64 = readq(&bar0->general_int_mask);
1200 temp64 &= ~((u64) val64); 1688 temp64 &= ~((u64) val64);
1201 writeq(temp64, &bar0->general_int_mask); 1689 writeq(temp64, &bar0->general_int_mask);
1202 /* 1690 /*
1203 * Enable all the Tx side interrupts 1691 * Enable all the Tx side interrupts
1204 * writing 0 Enables all 64 TX interrupt levels 1692 * writing 0 Enables all 64 TX interrupt levels
1205 */ 1693 */
1206 writeq(0x0, &bar0->tx_traffic_mask); 1694 writeq(0x0, &bar0->tx_traffic_mask);
1207 } else if (flag == DISABLE_INTRS) { 1695 } else if (flag == DISABLE_INTRS) {
1208 /* 1696 /*
1209 * Disable Tx Traffic Intrs in the general intr mask 1697 * Disable Tx Traffic Intrs in the general intr mask
1210 * register. 1698 * register.
1211 */ 1699 */
1212 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask); 1700 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
@@ -1226,8 +1714,8 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1226 /* writing 0 Enables all 8 RX interrupt levels */ 1714 /* writing 0 Enables all 8 RX interrupt levels */
1227 writeq(0x0, &bar0->rx_traffic_mask); 1715 writeq(0x0, &bar0->rx_traffic_mask);
1228 } else if (flag == DISABLE_INTRS) { 1716 } else if (flag == DISABLE_INTRS) {
1229 /* 1717 /*
1230 * Disable Rx Traffic Intrs in the general intr mask 1718 * Disable Rx Traffic Intrs in the general intr mask
1231 * register. 1719 * register.
1232 */ 1720 */
1233 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask); 1721 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
@@ -1238,24 +1726,66 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1238 } 1726 }
1239} 1727}
1240 1728
1241/** 1729static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
1242 * verify_xena_quiescence - Checks whether the H/W is ready 1730{
1731 int ret = 0;
1732
1733 if (flag == FALSE) {
1734 if ((!herc && (rev_id >= 4)) || herc) {
1735 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1736 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1737 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1738 ret = 1;
1739 }
1740 }else {
1741 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1742 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1743 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1744 ret = 1;
1745 }
1746 }
1747 } else {
1748 if ((!herc && (rev_id >= 4)) || herc) {
1749 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1750 ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1751 (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1752 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1753 ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1754 ret = 1;
1755 }
1756 } else {
1757 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1758 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1759 (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1760 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1761 ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1762 ret = 1;
1763 }
1764 }
1765 }
1766
1767 return ret;
1768}
1769/**
1770 * verify_xena_quiescence - Checks whether the H/W is ready
1243 * @val64 : Value read from adapter status register. 1771 * @val64 : Value read from adapter status register.
1244 * @flag : indicates if the adapter enable bit was ever written once 1772 * @flag : indicates if the adapter enable bit was ever written once
1245 * before. 1773 * before.
1246 * Description: Returns whether the H/W is ready to go or not. Depending 1774 * Description: Returns whether the H/W is ready to go or not. Depending
1247 * on whether adapter enable bit was written or not the comparison 1775 * on whether adapter enable bit was written or not the comparison
1248 * differs and the calling function passes the input argument flag to 1776 * differs and the calling function passes the input argument flag to
1249 * indicate this. 1777 * indicate this.
1250 * Return: 1 If xena is quiescence 1778 * Return: 1 If xena is quiescence
1251 * 0 If Xena is not quiescence 1779 * 0 If Xena is not quiescence
1252 */ 1780 */
1253 1781
1254static int verify_xena_quiescence(u64 val64, int flag) 1782static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
1255{ 1783{
1256 int ret = 0; 1784 int ret = 0, herc;
1257 u64 tmp64 = ~((u64) val64); 1785 u64 tmp64 = ~((u64) val64);
1786 int rev_id = get_xena_rev_id(sp->pdev);
1258 1787
1788 herc = (sp->device_type == XFRAME_II_DEVICE);
1259 if (! 1789 if (!
1260 (tmp64 & 1790 (tmp64 &
1261 (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY | 1791 (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
@@ -1263,25 +1793,7 @@ static int verify_xena_quiescence(u64 val64, int flag)
1263 ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY | 1793 ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1264 ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK | 1794 ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1265 ADAPTER_STATUS_P_PLL_LOCK))) { 1795 ADAPTER_STATUS_P_PLL_LOCK))) {
1266 if (flag == FALSE) { 1796 ret = check_prc_pcc_state(val64, flag, rev_id, herc);
1267 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1268 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1269 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1270
1271 ret = 1;
1272
1273 }
1274 } else {
1275 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1276 ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1277 (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1278 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1279 ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1280
1281 ret = 1;
1282
1283 }
1284 }
1285 } 1797 }
1286 1798
1287 return ret; 1799 return ret;
@@ -1290,12 +1802,12 @@ static int verify_xena_quiescence(u64 val64, int flag)
1290/** 1802/**
1291 * fix_mac_address - Fix for Mac addr problem on Alpha platforms 1803 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
1292 * @sp: Pointer to device specifc structure 1804 * @sp: Pointer to device specifc structure
1293 * Description : 1805 * Description :
1294 * New procedure to clear mac address reading problems on Alpha platforms 1806 * New procedure to clear mac address reading problems on Alpha platforms
1295 * 1807 *
1296 */ 1808 */
1297 1809
1298static void fix_mac_address(nic_t * sp) 1810void fix_mac_address(nic_t * sp)
1299{ 1811{
1300 XENA_dev_config_t __iomem *bar0 = sp->bar0; 1812 XENA_dev_config_t __iomem *bar0 = sp->bar0;
1301 u64 val64; 1813 u64 val64;
@@ -1303,20 +1815,21 @@ static void fix_mac_address(nic_t * sp)
1303 1815
1304 while (fix_mac[i] != END_SIGN) { 1816 while (fix_mac[i] != END_SIGN) {
1305 writeq(fix_mac[i++], &bar0->gpio_control); 1817 writeq(fix_mac[i++], &bar0->gpio_control);
1818 udelay(10);
1306 val64 = readq(&bar0->gpio_control); 1819 val64 = readq(&bar0->gpio_control);
1307 } 1820 }
1308} 1821}
1309 1822
1310/** 1823/**
1311 * start_nic - Turns the device on 1824 * start_nic - Turns the device on
1312 * @nic : device private variable. 1825 * @nic : device private variable.
1313 * Description: 1826 * Description:
1314 * This function actually turns the device on. Before this function is 1827 * This function actually turns the device on. Before this function is
1315 * called,all Registers are configured from their reset states 1828 * called,all Registers are configured from their reset states
1316 * and shared memory is allocated but the NIC is still quiescent. On 1829 * and shared memory is allocated but the NIC is still quiescent. On
1317 * calling this function, the device interrupts are cleared and the NIC is 1830 * calling this function, the device interrupts are cleared and the NIC is
1318 * literally switched on by writing into the adapter control register. 1831 * literally switched on by writing into the adapter control register.
1319 * Return Value: 1832 * Return Value:
1320 * SUCCESS on success and -1 on failure. 1833 * SUCCESS on success and -1 on failure.
1321 */ 1834 */
1322 1835
@@ -1325,8 +1838,8 @@ static int start_nic(struct s2io_nic *nic)
1325 XENA_dev_config_t __iomem *bar0 = nic->bar0; 1838 XENA_dev_config_t __iomem *bar0 = nic->bar0;
1326 struct net_device *dev = nic->dev; 1839 struct net_device *dev = nic->dev;
1327 register u64 val64 = 0; 1840 register u64 val64 = 0;
1328 u16 interruptible, i; 1841 u16 interruptible;
1329 u16 subid; 1842 u16 subid, i;
1330 mac_info_t *mac_control; 1843 mac_info_t *mac_control;
1331 struct config_param *config; 1844 struct config_param *config;
1332 1845
@@ -1335,10 +1848,12 @@ static int start_nic(struct s2io_nic *nic)
1335 1848
1336 /* PRC Initialization and configuration */ 1849 /* PRC Initialization and configuration */
1337 for (i = 0; i < config->rx_ring_num; i++) { 1850 for (i = 0; i < config->rx_ring_num; i++) {
1338 writeq((u64) nic->rx_blocks[i][0].block_dma_addr, 1851 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1339 &bar0->prc_rxd0_n[i]); 1852 &bar0->prc_rxd0_n[i]);
1340 1853
1341 val64 = readq(&bar0->prc_ctrl_n[i]); 1854 val64 = readq(&bar0->prc_ctrl_n[i]);
1855 if (nic->config.bimodal)
1856 val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
1342#ifndef CONFIG_2BUFF_MODE 1857#ifndef CONFIG_2BUFF_MODE
1343 val64 |= PRC_CTRL_RC_ENABLED; 1858 val64 |= PRC_CTRL_RC_ENABLED;
1344#else 1859#else
@@ -1354,7 +1869,7 @@ static int start_nic(struct s2io_nic *nic)
1354 writeq(val64, &bar0->rx_pa_cfg); 1869 writeq(val64, &bar0->rx_pa_cfg);
1355#endif 1870#endif
1356 1871
1357 /* 1872 /*
1358 * Enabling MC-RLDRAM. After enabling the device, we timeout 1873 * Enabling MC-RLDRAM. After enabling the device, we timeout
1359 * for around 100ms, which is approximately the time required 1874 * for around 100ms, which is approximately the time required
1360 * for the device to be ready for operation. 1875 * for the device to be ready for operation.
@@ -1364,27 +1879,27 @@ static int start_nic(struct s2io_nic *nic)
1364 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); 1879 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
1365 val64 = readq(&bar0->mc_rldram_mrs); 1880 val64 = readq(&bar0->mc_rldram_mrs);
1366 1881
1367 msleep(100); /* Delay by around 100 ms. */ 1882 msleep(100); /* Delay by around 100 ms. */
1368 1883
1369 /* Enabling ECC Protection. */ 1884 /* Enabling ECC Protection. */
1370 val64 = readq(&bar0->adapter_control); 1885 val64 = readq(&bar0->adapter_control);
1371 val64 &= ~ADAPTER_ECC_EN; 1886 val64 &= ~ADAPTER_ECC_EN;
1372 writeq(val64, &bar0->adapter_control); 1887 writeq(val64, &bar0->adapter_control);
1373 1888
1374 /* 1889 /*
1375 * Clearing any possible Link state change interrupts that 1890 * Clearing any possible Link state change interrupts that
1376 * could have popped up just before Enabling the card. 1891 * could have popped up just before Enabling the card.
1377 */ 1892 */
1378 val64 = readq(&bar0->mac_rmac_err_reg); 1893 val64 = readq(&bar0->mac_rmac_err_reg);
1379 if (val64) 1894 if (val64)
1380 writeq(val64, &bar0->mac_rmac_err_reg); 1895 writeq(val64, &bar0->mac_rmac_err_reg);
1381 1896
1382 /* 1897 /*
1383 * Verify if the device is ready to be enabled, if so enable 1898 * Verify if the device is ready to be enabled, if so enable
1384 * it. 1899 * it.
1385 */ 1900 */
1386 val64 = readq(&bar0->adapter_status); 1901 val64 = readq(&bar0->adapter_status);
1387 if (!verify_xena_quiescence(val64, nic->device_enabled_once)) { 1902 if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
1388 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name); 1903 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
1389 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n", 1904 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
1390 (unsigned long long) val64); 1905 (unsigned long long) val64);
@@ -1392,16 +1907,18 @@ static int start_nic(struct s2io_nic *nic)
1392 } 1907 }
1393 1908
1394 /* Enable select interrupts */ 1909 /* Enable select interrupts */
1395 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR | 1910 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
1396 RX_MAC_INTR; 1911 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
1912 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
1913
1397 en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS); 1914 en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);
1398 1915
1399 /* 1916 /*
1400 * With some switches, link might be already up at this point. 1917 * With some switches, link might be already up at this point.
1401 * Because of this weird behavior, when we enable laser, 1918 * Because of this weird behavior, when we enable laser,
1402 * we may not get link. We need to handle this. We cannot 1919 * we may not get link. We need to handle this. We cannot
1403 * figure out which switch is misbehaving. So we are forced to 1920 * figure out which switch is misbehaving. So we are forced to
1404 * make a global change. 1921 * make a global change.
1405 */ 1922 */
1406 1923
1407 /* Enabling Laser. */ 1924 /* Enabling Laser. */
@@ -1411,44 +1928,30 @@ static int start_nic(struct s2io_nic *nic)
1411 1928
1412 /* SXE-002: Initialize link and activity LED */ 1929 /* SXE-002: Initialize link and activity LED */
1413 subid = nic->pdev->subsystem_device; 1930 subid = nic->pdev->subsystem_device;
1414 if ((subid & 0xFF) >= 0x07) { 1931 if (((subid & 0xFF) >= 0x07) &&
1932 (nic->device_type == XFRAME_I_DEVICE)) {
1415 val64 = readq(&bar0->gpio_control); 1933 val64 = readq(&bar0->gpio_control);
1416 val64 |= 0x0000800000000000ULL; 1934 val64 |= 0x0000800000000000ULL;
1417 writeq(val64, &bar0->gpio_control); 1935 writeq(val64, &bar0->gpio_control);
1418 val64 = 0x0411040400000000ULL; 1936 val64 = 0x0411040400000000ULL;
1419 writeq(val64, (void __iomem *) bar0 + 0x2700); 1937 writeq(val64, (void __iomem *) ((u8 *) bar0 + 0x2700));
1420 } 1938 }
1421 1939
1422 /* 1940 /*
1423 * Don't see link state interrupts on certain switches, so 1941 * Don't see link state interrupts on certain switches, so
1424 * directly scheduling a link state task from here. 1942 * directly scheduling a link state task from here.
1425 */ 1943 */
1426 schedule_work(&nic->set_link_task); 1944 schedule_work(&nic->set_link_task);
1427 1945
1428 /*
1429 * Here we are performing soft reset on XGXS to
1430 * force link down. Since link is already up, we will get
1431 * link state change interrupt after this reset
1432 */
1433 SPECIAL_REG_WRITE(0x80010515001E0000ULL, &bar0->dtx_control, UF);
1434 val64 = readq(&bar0->dtx_control);
1435 udelay(50);
1436 SPECIAL_REG_WRITE(0x80010515001E00E0ULL, &bar0->dtx_control, UF);
1437 val64 = readq(&bar0->dtx_control);
1438 udelay(50);
1439 SPECIAL_REG_WRITE(0x80070515001F00E4ULL, &bar0->dtx_control, UF);
1440 val64 = readq(&bar0->dtx_control);
1441 udelay(50);
1442
1443 return SUCCESS; 1946 return SUCCESS;
1444} 1947}
1445 1948
1446/** 1949/**
1447 * free_tx_buffers - Free all queued Tx buffers 1950 * free_tx_buffers - Free all queued Tx buffers
1448 * @nic : device private variable. 1951 * @nic : device private variable.
1449 * Description: 1952 * Description:
1450 * Free all queued Tx buffers. 1953 * Free all queued Tx buffers.
1451 * Return Value: void 1954 * Return Value: void
1452*/ 1955*/
1453 1956
1454static void free_tx_buffers(struct s2io_nic *nic) 1957static void free_tx_buffers(struct s2io_nic *nic)
@@ -1459,39 +1962,61 @@ static void free_tx_buffers(struct s2io_nic *nic)
1459 int i, j; 1962 int i, j;
1460 mac_info_t *mac_control; 1963 mac_info_t *mac_control;
1461 struct config_param *config; 1964 struct config_param *config;
1462 int cnt = 0; 1965 int cnt = 0, frg_cnt;
1463 1966
1464 mac_control = &nic->mac_control; 1967 mac_control = &nic->mac_control;
1465 config = &nic->config; 1968 config = &nic->config;
1466 1969
1467 for (i = 0; i < config->tx_fifo_num; i++) { 1970 for (i = 0; i < config->tx_fifo_num; i++) {
1468 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) { 1971 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
1469 txdp = (TxD_t *) nic->list_info[i][j]. 1972 txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
1470 list_virt_addr; 1973 list_virt_addr;
1471 skb = 1974 skb =
1472 (struct sk_buff *) ((unsigned long) txdp-> 1975 (struct sk_buff *) ((unsigned long) txdp->
1473 Host_Control); 1976 Host_Control);
1474 if (skb == NULL) { 1977 if (skb == NULL) {
1475 memset(txdp, 0, sizeof(TxD_t)); 1978 memset(txdp, 0, sizeof(TxD_t) *
1979 config->max_txds);
1476 continue; 1980 continue;
1477 } 1981 }
1982 frg_cnt = skb_shinfo(skb)->nr_frags;
1983 pci_unmap_single(nic->pdev, (dma_addr_t)
1984 txdp->Buffer_Pointer,
1985 skb->len - skb->data_len,
1986 PCI_DMA_TODEVICE);
1987 if (frg_cnt) {
1988 TxD_t *temp;
1989 temp = txdp;
1990 txdp++;
1991 for (j = 0; j < frg_cnt; j++, txdp++) {
1992 skb_frag_t *frag =
1993 &skb_shinfo(skb)->frags[j];
1994 pci_unmap_page(nic->pdev,
1995 (dma_addr_t)
1996 txdp->
1997 Buffer_Pointer,
1998 frag->size,
1999 PCI_DMA_TODEVICE);
2000 }
2001 txdp = temp;
2002 }
1478 dev_kfree_skb(skb); 2003 dev_kfree_skb(skb);
1479 memset(txdp, 0, sizeof(TxD_t)); 2004 memset(txdp, 0, sizeof(TxD_t) * config->max_txds);
1480 cnt++; 2005 cnt++;
1481 } 2006 }
1482 DBG_PRINT(INTR_DBG, 2007 DBG_PRINT(INTR_DBG,
1483 "%s:forcibly freeing %d skbs on FIFO%d\n", 2008 "%s:forcibly freeing %d skbs on FIFO%d\n",
1484 dev->name, cnt, i); 2009 dev->name, cnt, i);
1485 mac_control->tx_curr_get_info[i].offset = 0; 2010 mac_control->fifos[i].tx_curr_get_info.offset = 0;
1486 mac_control->tx_curr_put_info[i].offset = 0; 2011 mac_control->fifos[i].tx_curr_put_info.offset = 0;
1487 } 2012 }
1488} 2013}
1489 2014
1490/** 2015/**
1491 * stop_nic - To stop the nic 2016 * stop_nic - To stop the nic
1492 * @nic ; device private variable. 2017 * @nic ; device private variable.
1493 * Description: 2018 * Description:
1494 * This function does exactly the opposite of what the start_nic() 2019 * This function does exactly the opposite of what the start_nic()
1495 * function does. This function is called to stop the device. 2020 * function does. This function is called to stop the device.
1496 * Return Value: 2021 * Return Value:
1497 * void. 2022 * void.
@@ -1509,8 +2034,9 @@ static void stop_nic(struct s2io_nic *nic)
1509 config = &nic->config; 2034 config = &nic->config;
1510 2035
1511 /* Disable all interrupts */ 2036 /* Disable all interrupts */
1512 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR | 2037 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
1513 RX_MAC_INTR; 2038 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2039 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
1514 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS); 2040 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
1515 2041
1516 /* Disable PRCs */ 2042 /* Disable PRCs */
@@ -1521,11 +2047,11 @@ static void stop_nic(struct s2io_nic *nic)
1521 } 2047 }
1522} 2048}
1523 2049
1524/** 2050/**
1525 * fill_rx_buffers - Allocates the Rx side skbs 2051 * fill_rx_buffers - Allocates the Rx side skbs
1526 * @nic: device private variable 2052 * @nic: device private variable
1527 * @ring_no: ring number 2053 * @ring_no: ring number
1528 * Description: 2054 * Description:
1529 * The function allocates Rx side skbs and puts the physical 2055 * The function allocates Rx side skbs and puts the physical
1530 * address of these buffers into the RxD buffer pointers, so that the NIC 2056 * address of these buffers into the RxD buffer pointers, so that the NIC
1531 * can DMA the received frame into these locations. 2057 * can DMA the received frame into these locations.
@@ -1533,8 +2059,8 @@ static void stop_nic(struct s2io_nic *nic)
1533 * 1. single buffer, 2059 * 1. single buffer,
1534 * 2. three buffer and 2060 * 2. three buffer and
1535 * 3. Five buffer modes. 2061 * 3. Five buffer modes.
1536 * Each mode defines how many fragments the received frame will be split 2062 * Each mode defines how many fragments the received frame will be split
1537 * up into by the NIC. The frame is split into L3 header, L4 Header, 2063 * up into by the NIC. The frame is split into L3 header, L4 Header,
1538 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself 2064 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
1539 * is split into 3 fragments. As of now only single buffer mode is 2065 * is split into 3 fragments. As of now only single buffer mode is
1540 * supported. 2066 * supported.
@@ -1542,7 +2068,7 @@ static void stop_nic(struct s2io_nic *nic)
1542 * SUCCESS on success or an appropriate -ve value on failure. 2068 * SUCCESS on success or an appropriate -ve value on failure.
1543 */ 2069 */
1544 2070
1545static int fill_rx_buffers(struct s2io_nic *nic, int ring_no) 2071int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1546{ 2072{
1547 struct net_device *dev = nic->dev; 2073 struct net_device *dev = nic->dev;
1548 struct sk_buff *skb; 2074 struct sk_buff *skb;
@@ -1550,34 +2076,35 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1550 int off, off1, size, block_no, block_no1; 2076 int off, off1, size, block_no, block_no1;
1551 int offset, offset1; 2077 int offset, offset1;
1552 u32 alloc_tab = 0; 2078 u32 alloc_tab = 0;
1553 u32 alloc_cnt = nic->pkt_cnt[ring_no] - 2079 u32 alloc_cnt;
1554 atomic_read(&nic->rx_bufs_left[ring_no]);
1555 mac_info_t *mac_control; 2080 mac_info_t *mac_control;
1556 struct config_param *config; 2081 struct config_param *config;
1557#ifdef CONFIG_2BUFF_MODE 2082#ifdef CONFIG_2BUFF_MODE
1558 RxD_t *rxdpnext; 2083 RxD_t *rxdpnext;
1559 int nextblk; 2084 int nextblk;
1560 unsigned long tmp; 2085 u64 tmp;
1561 buffAdd_t *ba; 2086 buffAdd_t *ba;
1562 dma_addr_t rxdpphys; 2087 dma_addr_t rxdpphys;
1563#endif 2088#endif
1564#ifndef CONFIG_S2IO_NAPI 2089#ifndef CONFIG_S2IO_NAPI
1565 unsigned long flags; 2090 unsigned long flags;
1566#endif 2091#endif
2092 RxD_t *first_rxdp = NULL;
1567 2093
1568 mac_control = &nic->mac_control; 2094 mac_control = &nic->mac_control;
1569 config = &nic->config; 2095 config = &nic->config;
1570 2096 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2097 atomic_read(&nic->rx_bufs_left[ring_no]);
1571 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE + 2098 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
1572 HEADER_802_2_SIZE + HEADER_SNAP_SIZE; 2099 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
1573 2100
1574 while (alloc_tab < alloc_cnt) { 2101 while (alloc_tab < alloc_cnt) {
1575 block_no = mac_control->rx_curr_put_info[ring_no]. 2102 block_no = mac_control->rings[ring_no].rx_curr_put_info.
1576 block_index; 2103 block_index;
1577 block_no1 = mac_control->rx_curr_get_info[ring_no]. 2104 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.
1578 block_index; 2105 block_index;
1579 off = mac_control->rx_curr_put_info[ring_no].offset; 2106 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
1580 off1 = mac_control->rx_curr_get_info[ring_no].offset; 2107 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
1581#ifndef CONFIG_2BUFF_MODE 2108#ifndef CONFIG_2BUFF_MODE
1582 offset = block_no * (MAX_RXDS_PER_BLOCK + 1) + off; 2109 offset = block_no * (MAX_RXDS_PER_BLOCK + 1) + off;
1583 offset1 = block_no1 * (MAX_RXDS_PER_BLOCK + 1) + off1; 2110 offset1 = block_no1 * (MAX_RXDS_PER_BLOCK + 1) + off1;
@@ -1586,7 +2113,7 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1586 offset1 = block_no1 * (MAX_RXDS_PER_BLOCK) + off1; 2113 offset1 = block_no1 * (MAX_RXDS_PER_BLOCK) + off1;
1587#endif 2114#endif
1588 2115
1589 rxdp = nic->rx_blocks[ring_no][block_no]. 2116 rxdp = mac_control->rings[ring_no].rx_blocks[block_no].
1590 block_virt_addr + off; 2117 block_virt_addr + off;
1591 if ((offset == offset1) && (rxdp->Host_Control)) { 2118 if ((offset == offset1) && (rxdp->Host_Control)) {
1592 DBG_PRINT(INTR_DBG, "%s: Get and Put", dev->name); 2119 DBG_PRINT(INTR_DBG, "%s: Get and Put", dev->name);
@@ -1595,15 +2122,15 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1595 } 2122 }
1596#ifndef CONFIG_2BUFF_MODE 2123#ifndef CONFIG_2BUFF_MODE
1597 if (rxdp->Control_1 == END_OF_BLOCK) { 2124 if (rxdp->Control_1 == END_OF_BLOCK) {
1598 mac_control->rx_curr_put_info[ring_no]. 2125 mac_control->rings[ring_no].rx_curr_put_info.
1599 block_index++; 2126 block_index++;
1600 mac_control->rx_curr_put_info[ring_no]. 2127 mac_control->rings[ring_no].rx_curr_put_info.
1601 block_index %= nic->block_count[ring_no]; 2128 block_index %= mac_control->rings[ring_no].block_count;
1602 block_no = mac_control->rx_curr_put_info 2129 block_no = mac_control->rings[ring_no].rx_curr_put_info.
1603 [ring_no].block_index; 2130 block_index;
1604 off++; 2131 off++;
1605 off %= (MAX_RXDS_PER_BLOCK + 1); 2132 off %= (MAX_RXDS_PER_BLOCK + 1);
1606 mac_control->rx_curr_put_info[ring_no].offset = 2133 mac_control->rings[ring_no].rx_curr_put_info.offset =
1607 off; 2134 off;
1608 rxdp = (RxD_t *) ((unsigned long) rxdp->Control_2); 2135 rxdp = (RxD_t *) ((unsigned long) rxdp->Control_2);
1609 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n", 2136 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
@@ -1611,30 +2138,30 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1611 } 2138 }
1612#ifndef CONFIG_S2IO_NAPI 2139#ifndef CONFIG_S2IO_NAPI
1613 spin_lock_irqsave(&nic->put_lock, flags); 2140 spin_lock_irqsave(&nic->put_lock, flags);
1614 nic->put_pos[ring_no] = 2141 mac_control->rings[ring_no].put_pos =
1615 (block_no * (MAX_RXDS_PER_BLOCK + 1)) + off; 2142 (block_no * (MAX_RXDS_PER_BLOCK + 1)) + off;
1616 spin_unlock_irqrestore(&nic->put_lock, flags); 2143 spin_unlock_irqrestore(&nic->put_lock, flags);
1617#endif 2144#endif
1618#else 2145#else
1619 if (rxdp->Host_Control == END_OF_BLOCK) { 2146 if (rxdp->Host_Control == END_OF_BLOCK) {
1620 mac_control->rx_curr_put_info[ring_no]. 2147 mac_control->rings[ring_no].rx_curr_put_info.
1621 block_index++; 2148 block_index++;
1622 mac_control->rx_curr_put_info[ring_no]. 2149 mac_control->rings[ring_no].rx_curr_put_info.block_index
1623 block_index %= nic->block_count[ring_no]; 2150 %= mac_control->rings[ring_no].block_count;
1624 block_no = mac_control->rx_curr_put_info 2151 block_no = mac_control->rings[ring_no].rx_curr_put_info
1625 [ring_no].block_index; 2152 .block_index;
1626 off = 0; 2153 off = 0;
1627 DBG_PRINT(INTR_DBG, "%s: block%d at: 0x%llx\n", 2154 DBG_PRINT(INTR_DBG, "%s: block%d at: 0x%llx\n",
1628 dev->name, block_no, 2155 dev->name, block_no,
1629 (unsigned long long) rxdp->Control_1); 2156 (unsigned long long) rxdp->Control_1);
1630 mac_control->rx_curr_put_info[ring_no].offset = 2157 mac_control->rings[ring_no].rx_curr_put_info.offset =
1631 off; 2158 off;
1632 rxdp = nic->rx_blocks[ring_no][block_no]. 2159 rxdp = mac_control->rings[ring_no].rx_blocks[block_no].
1633 block_virt_addr; 2160 block_virt_addr;
1634 } 2161 }
1635#ifndef CONFIG_S2IO_NAPI 2162#ifndef CONFIG_S2IO_NAPI
1636 spin_lock_irqsave(&nic->put_lock, flags); 2163 spin_lock_irqsave(&nic->put_lock, flags);
1637 nic->put_pos[ring_no] = (block_no * 2164 mac_control->rings[ring_no].put_pos = (block_no *
1638 (MAX_RXDS_PER_BLOCK + 1)) + off; 2165 (MAX_RXDS_PER_BLOCK + 1)) + off;
1639 spin_unlock_irqrestore(&nic->put_lock, flags); 2166 spin_unlock_irqrestore(&nic->put_lock, flags);
1640#endif 2167#endif
@@ -1646,27 +2173,27 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1646 if (rxdp->Control_2 & BIT(0)) 2173 if (rxdp->Control_2 & BIT(0))
1647#endif 2174#endif
1648 { 2175 {
1649 mac_control->rx_curr_put_info[ring_no]. 2176 mac_control->rings[ring_no].rx_curr_put_info.
1650 offset = off; 2177 offset = off;
1651 goto end; 2178 goto end;
1652 } 2179 }
1653#ifdef CONFIG_2BUFF_MODE 2180#ifdef CONFIG_2BUFF_MODE
1654 /* 2181 /*
1655 * RxDs Spanning cache lines will be replenished only 2182 * RxDs Spanning cache lines will be replenished only
1656 * if the succeeding RxD is also owned by Host. It 2183 * if the succeeding RxD is also owned by Host. It
1657 * will always be the ((8*i)+3) and ((8*i)+6) 2184 * will always be the ((8*i)+3) and ((8*i)+6)
1658 * descriptors for the 48 byte descriptor. The offending 2185 * descriptors for the 48 byte descriptor. The offending
1659 * decsriptor is of-course the 3rd descriptor. 2186 * decsriptor is of-course the 3rd descriptor.
1660 */ 2187 */
1661 rxdpphys = nic->rx_blocks[ring_no][block_no]. 2188 rxdpphys = mac_control->rings[ring_no].rx_blocks[block_no].
1662 block_dma_addr + (off * sizeof(RxD_t)); 2189 block_dma_addr + (off * sizeof(RxD_t));
1663 if (((u64) (rxdpphys)) % 128 > 80) { 2190 if (((u64) (rxdpphys)) % 128 > 80) {
1664 rxdpnext = nic->rx_blocks[ring_no][block_no]. 2191 rxdpnext = mac_control->rings[ring_no].rx_blocks[block_no].
1665 block_virt_addr + (off + 1); 2192 block_virt_addr + (off + 1);
1666 if (rxdpnext->Host_Control == END_OF_BLOCK) { 2193 if (rxdpnext->Host_Control == END_OF_BLOCK) {
1667 nextblk = (block_no + 1) % 2194 nextblk = (block_no + 1) %
1668 (nic->block_count[ring_no]); 2195 (mac_control->rings[ring_no].block_count);
1669 rxdpnext = nic->rx_blocks[ring_no] 2196 rxdpnext = mac_control->rings[ring_no].rx_blocks
1670 [nextblk].block_virt_addr; 2197 [nextblk].block_virt_addr;
1671 } 2198 }
1672 if (rxdpnext->Control_2 & BIT(0)) 2199 if (rxdpnext->Control_2 & BIT(0))
@@ -1682,6 +2209,10 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1682 if (!skb) { 2209 if (!skb) {
1683 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name); 2210 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
1684 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n"); 2211 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2212 if (first_rxdp) {
2213 wmb();
2214 first_rxdp->Control_1 |= RXD_OWN_XENA;
2215 }
1685 return -ENOMEM; 2216 return -ENOMEM;
1686 } 2217 }
1687#ifndef CONFIG_2BUFF_MODE 2218#ifndef CONFIG_2BUFF_MODE
@@ -1692,12 +2223,13 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1692 rxdp->Control_2 &= (~MASK_BUFFER0_SIZE); 2223 rxdp->Control_2 &= (~MASK_BUFFER0_SIZE);
1693 rxdp->Control_2 |= SET_BUFFER0_SIZE(size); 2224 rxdp->Control_2 |= SET_BUFFER0_SIZE(size);
1694 rxdp->Host_Control = (unsigned long) (skb); 2225 rxdp->Host_Control = (unsigned long) (skb);
1695 rxdp->Control_1 |= RXD_OWN_XENA; 2226 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2227 rxdp->Control_1 |= RXD_OWN_XENA;
1696 off++; 2228 off++;
1697 off %= (MAX_RXDS_PER_BLOCK + 1); 2229 off %= (MAX_RXDS_PER_BLOCK + 1);
1698 mac_control->rx_curr_put_info[ring_no].offset = off; 2230 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
1699#else 2231#else
1700 ba = &nic->ba[ring_no][block_no][off]; 2232 ba = &mac_control->rings[ring_no].ba[block_no][off];
1701 skb_reserve(skb, BUF0_LEN); 2233 skb_reserve(skb, BUF0_LEN);
1702 tmp = ((unsigned long) skb->data & ALIGN_SIZE); 2234 tmp = ((unsigned long) skb->data & ALIGN_SIZE);
1703 if (tmp) 2235 if (tmp)
@@ -1719,22 +2251,41 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1719 rxdp->Control_2 |= SET_BUFFER1_SIZE(1); /* dummy. */ 2251 rxdp->Control_2 |= SET_BUFFER1_SIZE(1); /* dummy. */
1720 rxdp->Control_2 |= BIT(0); /* Set Buffer_Empty bit. */ 2252 rxdp->Control_2 |= BIT(0); /* Set Buffer_Empty bit. */
1721 rxdp->Host_Control = (u64) ((unsigned long) (skb)); 2253 rxdp->Host_Control = (u64) ((unsigned long) (skb));
1722 rxdp->Control_1 |= RXD_OWN_XENA; 2254 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2255 rxdp->Control_1 |= RXD_OWN_XENA;
1723 off++; 2256 off++;
1724 mac_control->rx_curr_put_info[ring_no].offset = off; 2257 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
1725#endif 2258#endif
2259 rxdp->Control_2 |= SET_RXD_MARKER;
2260
2261 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2262 if (first_rxdp) {
2263 wmb();
2264 first_rxdp->Control_1 |= RXD_OWN_XENA;
2265 }
2266 first_rxdp = rxdp;
2267 }
1726 atomic_inc(&nic->rx_bufs_left[ring_no]); 2268 atomic_inc(&nic->rx_bufs_left[ring_no]);
1727 alloc_tab++; 2269 alloc_tab++;
1728 } 2270 }
1729 2271
1730 end: 2272 end:
2273 /* Transfer ownership of first descriptor to adapter just before
2274 * exiting. Before that, use memory barrier so that ownership
2275 * and other fields are seen by adapter correctly.
2276 */
2277 if (first_rxdp) {
2278 wmb();
2279 first_rxdp->Control_1 |= RXD_OWN_XENA;
2280 }
2281
1731 return SUCCESS; 2282 return SUCCESS;
1732} 2283}
1733 2284
1734/** 2285/**
1735 * free_rx_buffers - Frees all Rx buffers 2286 * free_rx_buffers - Frees all Rx buffers
1736 * @sp: device private variable. 2287 * @sp: device private variable.
1737 * Description: 2288 * Description:
1738 * This function will free all Rx buffers allocated by host. 2289 * This function will free all Rx buffers allocated by host.
1739 * Return Value: 2290 * Return Value:
1740 * NONE. 2291 * NONE.
@@ -1758,7 +2309,8 @@ static void free_rx_buffers(struct s2io_nic *sp)
1758 for (i = 0; i < config->rx_ring_num; i++) { 2309 for (i = 0; i < config->rx_ring_num; i++) {
1759 for (j = 0, blk = 0; j < config->rx_cfg[i].num_rxd; j++) { 2310 for (j = 0, blk = 0; j < config->rx_cfg[i].num_rxd; j++) {
1760 off = j % (MAX_RXDS_PER_BLOCK + 1); 2311 off = j % (MAX_RXDS_PER_BLOCK + 1);
1761 rxdp = sp->rx_blocks[i][blk].block_virt_addr + off; 2312 rxdp = mac_control->rings[i].rx_blocks[blk].
2313 block_virt_addr + off;
1762 2314
1763#ifndef CONFIG_2BUFF_MODE 2315#ifndef CONFIG_2BUFF_MODE
1764 if (rxdp->Control_1 == END_OF_BLOCK) { 2316 if (rxdp->Control_1 == END_OF_BLOCK) {
@@ -1793,7 +2345,7 @@ static void free_rx_buffers(struct s2io_nic *sp)
1793 HEADER_SNAP_SIZE, 2345 HEADER_SNAP_SIZE,
1794 PCI_DMA_FROMDEVICE); 2346 PCI_DMA_FROMDEVICE);
1795#else 2347#else
1796 ba = &sp->ba[i][blk][off]; 2348 ba = &mac_control->rings[i].ba[blk][off];
1797 pci_unmap_single(sp->pdev, (dma_addr_t) 2349 pci_unmap_single(sp->pdev, (dma_addr_t)
1798 rxdp->Buffer0_ptr, 2350 rxdp->Buffer0_ptr,
1799 BUF0_LEN, 2351 BUF0_LEN,
@@ -1813,10 +2365,10 @@ static void free_rx_buffers(struct s2io_nic *sp)
1813 } 2365 }
1814 memset(rxdp, 0, sizeof(RxD_t)); 2366 memset(rxdp, 0, sizeof(RxD_t));
1815 } 2367 }
1816 mac_control->rx_curr_put_info[i].block_index = 0; 2368 mac_control->rings[i].rx_curr_put_info.block_index = 0;
1817 mac_control->rx_curr_get_info[i].block_index = 0; 2369 mac_control->rings[i].rx_curr_get_info.block_index = 0;
1818 mac_control->rx_curr_put_info[i].offset = 0; 2370 mac_control->rings[i].rx_curr_put_info.offset = 0;
1819 mac_control->rx_curr_get_info[i].offset = 0; 2371 mac_control->rings[i].rx_curr_get_info.offset = 0;
1820 atomic_set(&sp->rx_bufs_left[i], 0); 2372 atomic_set(&sp->rx_bufs_left[i], 0);
1821 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n", 2373 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
1822 dev->name, buf_cnt, i); 2374 dev->name, buf_cnt, i);
@@ -1826,7 +2378,7 @@ static void free_rx_buffers(struct s2io_nic *sp)
1826/** 2378/**
1827 * s2io_poll - Rx interrupt handler for NAPI support 2379 * s2io_poll - Rx interrupt handler for NAPI support
1828 * @dev : pointer to the device structure. 2380 * @dev : pointer to the device structure.
1829 * @budget : The number of packets that were budgeted to be processed 2381 * @budget : The number of packets that were budgeted to be processed
1830 * during one pass through the 'Poll" function. 2382 * during one pass through the 'Poll" function.
1831 * Description: 2383 * Description:
1832 * Comes into picture only if NAPI support has been incorporated. It does 2384 * Comes into picture only if NAPI support has been incorporated. It does
@@ -1836,160 +2388,36 @@ static void free_rx_buffers(struct s2io_nic *sp)
1836 * 0 on success and 1 if there are No Rx packets to be processed. 2388 * 0 on success and 1 if there are No Rx packets to be processed.
1837 */ 2389 */
1838 2390
1839#ifdef CONFIG_S2IO_NAPI 2391#if defined(CONFIG_S2IO_NAPI)
1840static int s2io_poll(struct net_device *dev, int *budget) 2392static int s2io_poll(struct net_device *dev, int *budget)
1841{ 2393{
1842 nic_t *nic = dev->priv; 2394 nic_t *nic = dev->priv;
1843 XENA_dev_config_t __iomem *bar0 = nic->bar0; 2395 int pkt_cnt = 0, org_pkts_to_process;
1844 int pkts_to_process = *budget, pkt_cnt = 0;
1845 register u64 val64 = 0;
1846 rx_curr_get_info_t get_info, put_info;
1847 int i, get_block, put_block, get_offset, put_offset, ring_bufs;
1848#ifndef CONFIG_2BUFF_MODE
1849 u16 val16, cksum;
1850#endif
1851 struct sk_buff *skb;
1852 RxD_t *rxdp;
1853 mac_info_t *mac_control; 2396 mac_info_t *mac_control;
1854 struct config_param *config; 2397 struct config_param *config;
1855#ifdef CONFIG_2BUFF_MODE 2398 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
1856 buffAdd_t *ba; 2399 u64 val64;
1857#endif 2400 int i;
1858 2401
2402 atomic_inc(&nic->isr_cnt);
1859 mac_control = &nic->mac_control; 2403 mac_control = &nic->mac_control;
1860 config = &nic->config; 2404 config = &nic->config;
1861 2405
1862 if (pkts_to_process > dev->quota) 2406 nic->pkts_to_process = *budget;
1863 pkts_to_process = dev->quota; 2407 if (nic->pkts_to_process > dev->quota)
2408 nic->pkts_to_process = dev->quota;
2409 org_pkts_to_process = nic->pkts_to_process;
1864 2410
1865 val64 = readq(&bar0->rx_traffic_int); 2411 val64 = readq(&bar0->rx_traffic_int);
1866 writeq(val64, &bar0->rx_traffic_int); 2412 writeq(val64, &bar0->rx_traffic_int);
1867 2413
1868 for (i = 0; i < config->rx_ring_num; i++) { 2414 for (i = 0; i < config->rx_ring_num; i++) {
1869 get_info = mac_control->rx_curr_get_info[i]; 2415 rx_intr_handler(&mac_control->rings[i]);
1870 get_block = get_info.block_index; 2416 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
1871 put_info = mac_control->rx_curr_put_info[i]; 2417 if (!nic->pkts_to_process) {
1872 put_block = put_info.block_index; 2418 /* Quota for the current iteration has been met */
1873 ring_bufs = config->rx_cfg[i].num_rxd; 2419 goto no_rx;
1874 rxdp = nic->rx_blocks[i][get_block].block_virt_addr +
1875 get_info.offset;
1876#ifndef CONFIG_2BUFF_MODE
1877 get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
1878 get_info.offset;
1879 put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
1880 put_info.offset;
1881 while ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
1882 (((get_offset + 1) % ring_bufs) != put_offset)) {
1883 if (--pkts_to_process < 0) {
1884 goto no_rx;
1885 }
1886 if (rxdp->Control_1 == END_OF_BLOCK) {
1887 rxdp =
1888 (RxD_t *) ((unsigned long) rxdp->
1889 Control_2);
1890 get_info.offset++;
1891 get_info.offset %=
1892 (MAX_RXDS_PER_BLOCK + 1);
1893 get_block++;
1894 get_block %= nic->block_count[i];
1895 mac_control->rx_curr_get_info[i].
1896 offset = get_info.offset;
1897 mac_control->rx_curr_get_info[i].
1898 block_index = get_block;
1899 continue;
1900 }
1901 get_offset =
1902 (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
1903 get_info.offset;
1904 skb =
1905 (struct sk_buff *) ((unsigned long) rxdp->
1906 Host_Control);
1907 if (skb == NULL) {
1908 DBG_PRINT(ERR_DBG, "%s: The skb is ",
1909 dev->name);
1910 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
1911 goto no_rx;
1912 }
1913 val64 = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
1914 val16 = (u16) (val64 >> 48);
1915 cksum = RXD_GET_L4_CKSUM(rxdp->Control_1);
1916 pci_unmap_single(nic->pdev, (dma_addr_t)
1917 rxdp->Buffer0_ptr,
1918 dev->mtu +
1919 HEADER_ETHERNET_II_802_3_SIZE +
1920 HEADER_802_2_SIZE +
1921 HEADER_SNAP_SIZE,
1922 PCI_DMA_FROMDEVICE);
1923 rx_osm_handler(nic, val16, rxdp, i);
1924 pkt_cnt++;
1925 get_info.offset++;
1926 get_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
1927 rxdp =
1928 nic->rx_blocks[i][get_block].block_virt_addr +
1929 get_info.offset;
1930 mac_control->rx_curr_get_info[i].offset =
1931 get_info.offset;
1932 } 2420 }
1933#else
1934 get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
1935 get_info.offset;
1936 put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
1937 put_info.offset;
1938 while (((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
1939 !(rxdp->Control_2 & BIT(0))) &&
1940 (((get_offset + 1) % ring_bufs) != put_offset)) {
1941 if (--pkts_to_process < 0) {
1942 goto no_rx;
1943 }
1944 skb = (struct sk_buff *) ((unsigned long)
1945 rxdp->Host_Control);
1946 if (skb == NULL) {
1947 DBG_PRINT(ERR_DBG, "%s: The skb is ",
1948 dev->name);
1949 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
1950 goto no_rx;
1951 }
1952
1953 pci_unmap_single(nic->pdev, (dma_addr_t)
1954 rxdp->Buffer0_ptr,
1955 BUF0_LEN, PCI_DMA_FROMDEVICE);
1956 pci_unmap_single(nic->pdev, (dma_addr_t)
1957 rxdp->Buffer1_ptr,
1958 BUF1_LEN, PCI_DMA_FROMDEVICE);
1959 pci_unmap_single(nic->pdev, (dma_addr_t)
1960 rxdp->Buffer2_ptr,
1961 dev->mtu + BUF0_LEN + 4,
1962 PCI_DMA_FROMDEVICE);
1963 ba = &nic->ba[i][get_block][get_info.offset];
1964
1965 rx_osm_handler(nic, rxdp, i, ba);
1966
1967 get_info.offset++;
1968 mac_control->rx_curr_get_info[i].offset =
1969 get_info.offset;
1970 rxdp =
1971 nic->rx_blocks[i][get_block].block_virt_addr +
1972 get_info.offset;
1973
1974 if (get_info.offset &&
1975 (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
1976 get_info.offset = 0;
1977 mac_control->rx_curr_get_info[i].
1978 offset = get_info.offset;
1979 get_block++;
1980 get_block %= nic->block_count[i];
1981 mac_control->rx_curr_get_info[i].
1982 block_index = get_block;
1983 rxdp =
1984 nic->rx_blocks[i][get_block].
1985 block_virt_addr;
1986 }
1987 get_offset =
1988 (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
1989 get_info.offset;
1990 pkt_cnt++;
1991 }
1992#endif
1993 } 2421 }
1994 if (!pkt_cnt) 2422 if (!pkt_cnt)
1995 pkt_cnt = 1; 2423 pkt_cnt = 1;
@@ -2007,9 +2435,10 @@ static int s2io_poll(struct net_device *dev, int *budget)
2007 } 2435 }
2008 /* Re enable the Rx interrupts. */ 2436 /* Re enable the Rx interrupts. */
2009 en_dis_able_nic_intrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS); 2437 en_dis_able_nic_intrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS);
2438 atomic_dec(&nic->isr_cnt);
2010 return 0; 2439 return 0;
2011 2440
2012 no_rx: 2441no_rx:
2013 dev->quota -= pkt_cnt; 2442 dev->quota -= pkt_cnt;
2014 *budget -= pkt_cnt; 2443 *budget -= pkt_cnt;
2015 2444
@@ -2020,279 +2449,204 @@ static int s2io_poll(struct net_device *dev, int *budget)
2020 break; 2449 break;
2021 } 2450 }
2022 } 2451 }
2452 atomic_dec(&nic->isr_cnt);
2023 return 1; 2453 return 1;
2024} 2454}
2025#else 2455#endif
2026/** 2456
2457/**
2027 * rx_intr_handler - Rx interrupt handler 2458 * rx_intr_handler - Rx interrupt handler
2028 * @nic: device private variable. 2459 * @nic: device private variable.
2029 * Description: 2460 * Description:
2030 * If the interrupt is because of a received frame or if the 2461 * If the interrupt is because of a received frame or if the
2031 * receive ring contains fresh as yet un-processed frames,this function is 2462 * receive ring contains fresh as yet un-processed frames,this function is
2032 * called. It picks out the RxD at which place the last Rx processing had 2463 * called. It picks out the RxD at which place the last Rx processing had
2033 * stopped and sends the skb to the OSM's Rx handler and then increments 2464 * stopped and sends the skb to the OSM's Rx handler and then increments
2034 * the offset. 2465 * the offset.
2035 * Return Value: 2466 * Return Value:
2036 * NONE. 2467 * NONE.
2037 */ 2468 */
2038 2469static void rx_intr_handler(ring_info_t *ring_data)
2039static void rx_intr_handler(struct s2io_nic *nic)
2040{ 2470{
2471 nic_t *nic = ring_data->nic;
2041 struct net_device *dev = (struct net_device *) nic->dev; 2472 struct net_device *dev = (struct net_device *) nic->dev;
2042 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; 2473 int get_block, get_offset, put_block, put_offset, ring_bufs;
2043 rx_curr_get_info_t get_info, put_info; 2474 rx_curr_get_info_t get_info, put_info;
2044 RxD_t *rxdp; 2475 RxD_t *rxdp;
2045 struct sk_buff *skb; 2476 struct sk_buff *skb;
2046#ifndef CONFIG_2BUFF_MODE 2477#ifndef CONFIG_S2IO_NAPI
2047 u16 val16, cksum; 2478 int pkt_cnt = 0;
2048#endif
2049 register u64 val64 = 0;
2050 int get_block, get_offset, put_block, put_offset, ring_bufs;
2051 int i, pkt_cnt = 0;
2052 mac_info_t *mac_control;
2053 struct config_param *config;
2054#ifdef CONFIG_2BUFF_MODE
2055 buffAdd_t *ba;
2056#endif 2479#endif
2480 spin_lock(&nic->rx_lock);
2481 if (atomic_read(&nic->card_state) == CARD_DOWN) {
2482 DBG_PRINT(ERR_DBG, "%s: %s going down for reset\n",
2483 __FUNCTION__, dev->name);
2484 spin_unlock(&nic->rx_lock);
2485 }
2057 2486
2058 mac_control = &nic->mac_control; 2487 get_info = ring_data->rx_curr_get_info;
2059 config = &nic->config; 2488 get_block = get_info.block_index;
2060 2489 put_info = ring_data->rx_curr_put_info;
2061 /* 2490 put_block = put_info.block_index;
2062 * rx_traffic_int reg is an R1 register, hence we read and write back 2491 ring_bufs = get_info.ring_len+1;
2063 * the samevalue in the register to clear it. 2492 rxdp = ring_data->rx_blocks[get_block].block_virt_addr +
2064 */
2065 val64 = readq(&bar0->rx_traffic_int);
2066 writeq(val64, &bar0->rx_traffic_int);
2067
2068 for (i = 0; i < config->rx_ring_num; i++) {
2069 get_info = mac_control->rx_curr_get_info[i];
2070 get_block = get_info.block_index;
2071 put_info = mac_control->rx_curr_put_info[i];
2072 put_block = put_info.block_index;
2073 ring_bufs = config->rx_cfg[i].num_rxd;
2074 rxdp = nic->rx_blocks[i][get_block].block_virt_addr +
2075 get_info.offset;
2076#ifndef CONFIG_2BUFF_MODE
2077 get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
2078 get_info.offset; 2493 get_info.offset;
2079 spin_lock(&nic->put_lock); 2494 get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
2080 put_offset = nic->put_pos[i]; 2495 get_info.offset;
2081 spin_unlock(&nic->put_lock); 2496#ifndef CONFIG_S2IO_NAPI
2082 while ((!(rxdp->Control_1 & RXD_OWN_XENA)) && 2497 spin_lock(&nic->put_lock);
2083 (((get_offset + 1) % ring_bufs) != put_offset)) { 2498 put_offset = ring_data->put_pos;
2084 if (rxdp->Control_1 == END_OF_BLOCK) { 2499 spin_unlock(&nic->put_lock);
2085 rxdp = (RxD_t *) ((unsigned long) 2500#else
2086 rxdp->Control_2); 2501 put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
2087 get_info.offset++; 2502 put_info.offset;
2088 get_info.offset %= 2503#endif
2089 (MAX_RXDS_PER_BLOCK + 1); 2504 while (RXD_IS_UP2DT(rxdp) &&
2090 get_block++; 2505 (((get_offset + 1) % ring_bufs) != put_offset)) {
2091 get_block %= nic->block_count[i]; 2506 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2092 mac_control->rx_curr_get_info[i]. 2507 if (skb == NULL) {
2093 offset = get_info.offset; 2508 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2094 mac_control->rx_curr_get_info[i]. 2509 dev->name);
2095 block_index = get_block; 2510 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2096 continue; 2511 spin_unlock(&nic->rx_lock);
2097 } 2512 return;
2098 get_offset =
2099 (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
2100 get_info.offset;
2101 skb = (struct sk_buff *) ((unsigned long)
2102 rxdp->Host_Control);
2103 if (skb == NULL) {
2104 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2105 dev->name);
2106 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2107 return;
2108 }
2109 val64 = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
2110 val16 = (u16) (val64 >> 48);
2111 cksum = RXD_GET_L4_CKSUM(rxdp->Control_1);
2112 pci_unmap_single(nic->pdev, (dma_addr_t)
2113 rxdp->Buffer0_ptr,
2114 dev->mtu +
2115 HEADER_ETHERNET_II_802_3_SIZE +
2116 HEADER_802_2_SIZE +
2117 HEADER_SNAP_SIZE,
2118 PCI_DMA_FROMDEVICE);
2119 rx_osm_handler(nic, val16, rxdp, i);
2120 get_info.offset++;
2121 get_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
2122 rxdp =
2123 nic->rx_blocks[i][get_block].block_virt_addr +
2124 get_info.offset;
2125 mac_control->rx_curr_get_info[i].offset =
2126 get_info.offset;
2127 pkt_cnt++;
2128 if ((indicate_max_pkts)
2129 && (pkt_cnt > indicate_max_pkts))
2130 break;
2131 } 2513 }
2514#ifndef CONFIG_2BUFF_MODE
2515 pci_unmap_single(nic->pdev, (dma_addr_t)
2516 rxdp->Buffer0_ptr,
2517 dev->mtu +
2518 HEADER_ETHERNET_II_802_3_SIZE +
2519 HEADER_802_2_SIZE +
2520 HEADER_SNAP_SIZE,
2521 PCI_DMA_FROMDEVICE);
2132#else 2522#else
2133 get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) + 2523 pci_unmap_single(nic->pdev, (dma_addr_t)
2524 rxdp->Buffer0_ptr,
2525 BUF0_LEN, PCI_DMA_FROMDEVICE);
2526 pci_unmap_single(nic->pdev, (dma_addr_t)
2527 rxdp->Buffer1_ptr,
2528 BUF1_LEN, PCI_DMA_FROMDEVICE);
2529 pci_unmap_single(nic->pdev, (dma_addr_t)
2530 rxdp->Buffer2_ptr,
2531 dev->mtu + BUF0_LEN + 4,
2532 PCI_DMA_FROMDEVICE);
2533#endif
2534 rx_osm_handler(ring_data, rxdp);
2535 get_info.offset++;
2536 ring_data->rx_curr_get_info.offset =
2134 get_info.offset; 2537 get_info.offset;
2135 spin_lock(&nic->put_lock); 2538 rxdp = ring_data->rx_blocks[get_block].block_virt_addr +
2136 put_offset = nic->put_pos[i]; 2539 get_info.offset;
2137 spin_unlock(&nic->put_lock); 2540 if (get_info.offset &&
2138 while (((!(rxdp->Control_1 & RXD_OWN_XENA)) && 2541 (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
2139 !(rxdp->Control_2 & BIT(0))) && 2542 get_info.offset = 0;
2140 (((get_offset + 1) % ring_bufs) != put_offset)) { 2543 ring_data->rx_curr_get_info.offset
2141 skb = (struct sk_buff *) ((unsigned long) 2544 = get_info.offset;
2142 rxdp->Host_Control); 2545 get_block++;
2143 if (skb == NULL) { 2546 get_block %= ring_data->block_count;
2144 DBG_PRINT(ERR_DBG, "%s: The skb is ", 2547 ring_data->rx_curr_get_info.block_index
2145 dev->name); 2548 = get_block;
2146 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n"); 2549 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2147 return; 2550 }
2148 }
2149
2150 pci_unmap_single(nic->pdev, (dma_addr_t)
2151 rxdp->Buffer0_ptr,
2152 BUF0_LEN, PCI_DMA_FROMDEVICE);
2153 pci_unmap_single(nic->pdev, (dma_addr_t)
2154 rxdp->Buffer1_ptr,
2155 BUF1_LEN, PCI_DMA_FROMDEVICE);
2156 pci_unmap_single(nic->pdev, (dma_addr_t)
2157 rxdp->Buffer2_ptr,
2158 dev->mtu + BUF0_LEN + 4,
2159 PCI_DMA_FROMDEVICE);
2160 ba = &nic->ba[i][get_block][get_info.offset];
2161
2162 rx_osm_handler(nic, rxdp, i, ba);
2163
2164 get_info.offset++;
2165 mac_control->rx_curr_get_info[i].offset =
2166 get_info.offset;
2167 rxdp =
2168 nic->rx_blocks[i][get_block].block_virt_addr +
2169 get_info.offset;
2170 2551
2171 if (get_info.offset && 2552 get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
2172 (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
2173 get_info.offset = 0;
2174 mac_control->rx_curr_get_info[i].
2175 offset = get_info.offset;
2176 get_block++;
2177 get_block %= nic->block_count[i];
2178 mac_control->rx_curr_get_info[i].
2179 block_index = get_block;
2180 rxdp =
2181 nic->rx_blocks[i][get_block].
2182 block_virt_addr;
2183 }
2184 get_offset =
2185 (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
2186 get_info.offset; 2553 get_info.offset;
2187 pkt_cnt++; 2554#ifdef CONFIG_S2IO_NAPI
2188 if ((indicate_max_pkts) 2555 nic->pkts_to_process -= 1;
2189 && (pkt_cnt > indicate_max_pkts)) 2556 if (!nic->pkts_to_process)
2190 break; 2557 break;
2191 } 2558#else
2192#endif 2559 pkt_cnt++;
2193 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts)) 2560 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2194 break; 2561 break;
2562#endif
2195 } 2563 }
2564 spin_unlock(&nic->rx_lock);
2196} 2565}
2197#endif 2566
2198/** 2567/**
2199 * tx_intr_handler - Transmit interrupt handler 2568 * tx_intr_handler - Transmit interrupt handler
2200 * @nic : device private variable 2569 * @nic : device private variable
2201 * Description: 2570 * Description:
2202 * If an interrupt was raised to indicate DMA complete of the 2571 * If an interrupt was raised to indicate DMA complete of the
2203 * Tx packet, this function is called. It identifies the last TxD 2572 * Tx packet, this function is called. It identifies the last TxD
2204 * whose buffer was freed and frees all skbs whose data have already 2573 * whose buffer was freed and frees all skbs whose data have already
2205 * DMA'ed into the NICs internal memory. 2574 * DMA'ed into the NICs internal memory.
2206 * Return Value: 2575 * Return Value:
2207 * NONE 2576 * NONE
2208 */ 2577 */
2209 2578
2210static void tx_intr_handler(struct s2io_nic *nic) 2579static void tx_intr_handler(fifo_info_t *fifo_data)
2211{ 2580{
2212 XENA_dev_config_t __iomem *bar0 = nic->bar0; 2581 nic_t *nic = fifo_data->nic;
2213 struct net_device *dev = (struct net_device *) nic->dev; 2582 struct net_device *dev = (struct net_device *) nic->dev;
2214 tx_curr_get_info_t get_info, put_info; 2583 tx_curr_get_info_t get_info, put_info;
2215 struct sk_buff *skb; 2584 struct sk_buff *skb;
2216 TxD_t *txdlp; 2585 TxD_t *txdlp;
2217 register u64 val64 = 0;
2218 int i;
2219 u16 j, frg_cnt; 2586 u16 j, frg_cnt;
2220 mac_info_t *mac_control;
2221 struct config_param *config;
2222 2587
2223 mac_control = &nic->mac_control; 2588 get_info = fifo_data->tx_curr_get_info;
2224 config = &nic->config; 2589 put_info = fifo_data->tx_curr_put_info;
2225 2590 txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2226 /* 2591 list_virt_addr;
2227 * tx_traffic_int reg is an R1 register, hence we read and write 2592 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2228 * back the samevalue in the register to clear it. 2593 (get_info.offset != put_info.offset) &&
2229 */ 2594 (txdlp->Host_Control)) {
2230 val64 = readq(&bar0->tx_traffic_int); 2595 /* Check for TxD errors */
2231 writeq(val64, &bar0->tx_traffic_int); 2596 if (txdlp->Control_1 & TXD_T_CODE) {
2597 unsigned long long err;
2598 err = txdlp->Control_1 & TXD_T_CODE;
2599 DBG_PRINT(ERR_DBG, "***TxD error %llx\n",
2600 err);
2601 }
2232 2602
2233 for (i = 0; i < config->tx_fifo_num; i++) { 2603 skb = (struct sk_buff *) ((unsigned long)
2234 get_info = mac_control->tx_curr_get_info[i]; 2604 txdlp->Host_Control);
2235 put_info = mac_control->tx_curr_put_info[i]; 2605 if (skb == NULL) {
2236 txdlp = (TxD_t *) nic->list_info[i][get_info.offset]. 2606 DBG_PRINT(ERR_DBG, "%s: Null skb ",
2237 list_virt_addr; 2607 __FUNCTION__);
2238 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) && 2608 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2239 (get_info.offset != put_info.offset) && 2609 return;
2240 (txdlp->Host_Control)) { 2610 }
2241 /* Check for TxD errors */
2242 if (txdlp->Control_1 & TXD_T_CODE) {
2243 unsigned long long err;
2244 err = txdlp->Control_1 & TXD_T_CODE;
2245 DBG_PRINT(ERR_DBG, "***TxD error %llx\n",
2246 err);
2247 }
2248 2611
2249 skb = (struct sk_buff *) ((unsigned long) 2612 frg_cnt = skb_shinfo(skb)->nr_frags;
2250 txdlp->Host_Control); 2613 nic->tx_pkt_count++;
2251 if (skb == NULL) { 2614
2252 DBG_PRINT(ERR_DBG, "%s: Null skb ", 2615 pci_unmap_single(nic->pdev, (dma_addr_t)
2253 dev->name); 2616 txdlp->Buffer_Pointer,
2254 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n"); 2617 skb->len - skb->data_len,
2255 return; 2618 PCI_DMA_TODEVICE);
2619 if (frg_cnt) {
2620 TxD_t *temp;
2621 temp = txdlp;
2622 txdlp++;
2623 for (j = 0; j < frg_cnt; j++, txdlp++) {
2624 skb_frag_t *frag =
2625 &skb_shinfo(skb)->frags[j];
2626 if (!txdlp->Buffer_Pointer)
2627 break;
2628 pci_unmap_page(nic->pdev,
2629 (dma_addr_t)
2630 txdlp->
2631 Buffer_Pointer,
2632 frag->size,
2633 PCI_DMA_TODEVICE);
2256 } 2634 }
2257 nic->tx_pkt_count++; 2635 txdlp = temp;
2258
2259 frg_cnt = skb_shinfo(skb)->nr_frags;
2260
2261 /* For unfragmented skb */
2262 pci_unmap_single(nic->pdev, (dma_addr_t)
2263 txdlp->Buffer_Pointer,
2264 skb->len - skb->data_len,
2265 PCI_DMA_TODEVICE);
2266 if (frg_cnt) {
2267 TxD_t *temp = txdlp;
2268 txdlp++;
2269 for (j = 0; j < frg_cnt; j++, txdlp++) {
2270 skb_frag_t *frag =
2271 &skb_shinfo(skb)->frags[j];
2272 pci_unmap_page(nic->pdev,
2273 (dma_addr_t)
2274 txdlp->
2275 Buffer_Pointer,
2276 frag->size,
2277 PCI_DMA_TODEVICE);
2278 }
2279 txdlp = temp;
2280 }
2281 memset(txdlp, 0,
2282 (sizeof(TxD_t) * config->max_txds));
2283
2284 /* Updating the statistics block */
2285 nic->stats.tx_packets++;
2286 nic->stats.tx_bytes += skb->len;
2287 dev_kfree_skb_irq(skb);
2288
2289 get_info.offset++;
2290 get_info.offset %= get_info.fifo_len + 1;
2291 txdlp = (TxD_t *) nic->list_info[i]
2292 [get_info.offset].list_virt_addr;
2293 mac_control->tx_curr_get_info[i].offset =
2294 get_info.offset;
2295 } 2636 }
2637 memset(txdlp, 0,
2638 (sizeof(TxD_t) * fifo_data->max_txds));
2639
2640 /* Updating the statistics block */
2641 nic->stats.tx_bytes += skb->len;
2642 dev_kfree_skb_irq(skb);
2643
2644 get_info.offset++;
2645 get_info.offset %= get_info.fifo_len + 1;
2646 txdlp = (TxD_t *) fifo_data->list_info
2647 [get_info.offset].list_virt_addr;
2648 fifo_data->tx_curr_get_info.offset =
2649 get_info.offset;
2296 } 2650 }
2297 2651
2298 spin_lock(&nic->tx_lock); 2652 spin_lock(&nic->tx_lock);
@@ -2301,13 +2655,13 @@ static void tx_intr_handler(struct s2io_nic *nic)
2301 spin_unlock(&nic->tx_lock); 2655 spin_unlock(&nic->tx_lock);
2302} 2656}
2303 2657
2304/** 2658/**
2305 * alarm_intr_handler - Alarm Interrrupt handler 2659 * alarm_intr_handler - Alarm Interrrupt handler
2306 * @nic: device private variable 2660 * @nic: device private variable
2307 * Description: If the interrupt was neither because of Rx packet or Tx 2661 * Description: If the interrupt was neither because of Rx packet or Tx
2308 * complete, this function is called. If the interrupt was to indicate 2662 * complete, this function is called. If the interrupt was to indicate
2309 * a loss of link, the OSM link status handler is invoked for any other 2663 * a loss of link, the OSM link status handler is invoked for any other
2310 * alarm interrupt the block that raised the interrupt is displayed 2664 * alarm interrupt the block that raised the interrupt is displayed
2311 * and a H/W reset is issued. 2665 * and a H/W reset is issued.
2312 * Return Value: 2666 * Return Value:
2313 * NONE 2667 * NONE
@@ -2320,10 +2674,32 @@ static void alarm_intr_handler(struct s2io_nic *nic)
2320 register u64 val64 = 0, err_reg = 0; 2674 register u64 val64 = 0, err_reg = 0;
2321 2675
2322 /* Handling link status change error Intr */ 2676 /* Handling link status change error Intr */
2323 err_reg = readq(&bar0->mac_rmac_err_reg); 2677 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2324 writeq(err_reg, &bar0->mac_rmac_err_reg); 2678 err_reg = readq(&bar0->mac_rmac_err_reg);
2325 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) { 2679 writeq(err_reg, &bar0->mac_rmac_err_reg);
2326 schedule_work(&nic->set_link_task); 2680 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
2681 schedule_work(&nic->set_link_task);
2682 }
2683 }
2684
2685 /* Handling Ecc errors */
2686 val64 = readq(&bar0->mc_err_reg);
2687 writeq(val64, &bar0->mc_err_reg);
2688 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
2689 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
2690 nic->mac_control.stats_info->sw_stat.
2691 double_ecc_errs++;
2692 DBG_PRINT(ERR_DBG, "%s: Device indicates ",
2693 dev->name);
2694 DBG_PRINT(ERR_DBG, "double ECC error!!\n");
2695 if (nic->device_type != XFRAME_II_DEVICE) {
2696 netif_stop_queue(dev);
2697 schedule_work(&nic->rst_timer_task);
2698 }
2699 } else {
2700 nic->mac_control.stats_info->sw_stat.
2701 single_ecc_errs++;
2702 }
2327 } 2703 }
2328 2704
2329 /* In case of a serious error, the device will be Reset. */ 2705 /* In case of a serious error, the device will be Reset. */
@@ -2338,7 +2714,7 @@ static void alarm_intr_handler(struct s2io_nic *nic)
2338 /* 2714 /*
2339 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC 2715 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
2340 * Error occurs, the adapter will be recycled by disabling the 2716 * Error occurs, the adapter will be recycled by disabling the
2341 * adapter enable bit and enabling it again after the device 2717 * adapter enable bit and enabling it again after the device
2342 * becomes Quiescent. 2718 * becomes Quiescent.
2343 */ 2719 */
2344 val64 = readq(&bar0->pcc_err_reg); 2720 val64 = readq(&bar0->pcc_err_reg);
@@ -2354,18 +2730,18 @@ static void alarm_intr_handler(struct s2io_nic *nic)
2354 /* Other type of interrupts are not being handled now, TODO */ 2730 /* Other type of interrupts are not being handled now, TODO */
2355} 2731}
2356 2732
2357/** 2733/**
2358 * wait_for_cmd_complete - waits for a command to complete. 2734 * wait_for_cmd_complete - waits for a command to complete.
2359 * @sp : private member of the device structure, which is a pointer to the 2735 * @sp : private member of the device structure, which is a pointer to the
2360 * s2io_nic structure. 2736 * s2io_nic structure.
2361 * Description: Function that waits for a command to Write into RMAC 2737 * Description: Function that waits for a command to Write into RMAC
2362 * ADDR DATA registers to be completed and returns either success or 2738 * ADDR DATA registers to be completed and returns either success or
2363 * error depending on whether the command was complete or not. 2739 * error depending on whether the command was complete or not.
2364 * Return value: 2740 * Return value:
2365 * SUCCESS on success and FAILURE on failure. 2741 * SUCCESS on success and FAILURE on failure.
2366 */ 2742 */
2367 2743
2368static int wait_for_cmd_complete(nic_t * sp) 2744int wait_for_cmd_complete(nic_t * sp)
2369{ 2745{
2370 XENA_dev_config_t __iomem *bar0 = sp->bar0; 2746 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2371 int ret = FAILURE, cnt = 0; 2747 int ret = FAILURE, cnt = 0;
@@ -2385,29 +2761,32 @@ static int wait_for_cmd_complete(nic_t * sp)
2385 return ret; 2761 return ret;
2386} 2762}
2387 2763
2388/** 2764/**
2389 * s2io_reset - Resets the card. 2765 * s2io_reset - Resets the card.
2390 * @sp : private member of the device structure. 2766 * @sp : private member of the device structure.
2391 * Description: Function to Reset the card. This function then also 2767 * Description: Function to Reset the card. This function then also
2392 * restores the previously saved PCI configuration space registers as 2768 * restores the previously saved PCI configuration space registers as
2393 * the card reset also resets the configuration space. 2769 * the card reset also resets the configuration space.
2394 * Return value: 2770 * Return value:
2395 * void. 2771 * void.
2396 */ 2772 */
2397 2773
2398static void s2io_reset(nic_t * sp) 2774void s2io_reset(nic_t * sp)
2399{ 2775{
2400 XENA_dev_config_t __iomem *bar0 = sp->bar0; 2776 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2401 u64 val64; 2777 u64 val64;
2402 u16 subid; 2778 u16 subid, pci_cmd;
2779
2780 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
2781 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
2403 2782
2404 val64 = SW_RESET_ALL; 2783 val64 = SW_RESET_ALL;
2405 writeq(val64, &bar0->sw_reset); 2784 writeq(val64, &bar0->sw_reset);
2406 2785
2407 /* 2786 /*
2408 * At this stage, if the PCI write is indeed completed, the 2787 * At this stage, if the PCI write is indeed completed, the
2409 * card is reset and so is the PCI Config space of the device. 2788 * card is reset and so is the PCI Config space of the device.
2410 * So a read cannot be issued at this stage on any of the 2789 * So a read cannot be issued at this stage on any of the
2411 * registers to ensure the write into "sw_reset" register 2790 * registers to ensure the write into "sw_reset" register
2412 * has gone through. 2791 * has gone through.
2413 * Question: Is there any system call that will explicitly force 2792 * Question: Is there any system call that will explicitly force
@@ -2418,42 +2797,72 @@ static void s2io_reset(nic_t * sp)
2418 */ 2797 */
2419 msleep(250); 2798 msleep(250);
2420 2799
2421 /* Restore the PCI state saved during initializarion. */ 2800 /* Restore the PCI state saved during initialization. */
2422 pci_restore_state(sp->pdev); 2801 pci_restore_state(sp->pdev);
2802 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
2803 pci_cmd);
2423 s2io_init_pci(sp); 2804 s2io_init_pci(sp);
2424 2805
2425 msleep(250); 2806 msleep(250);
2426 2807
2808 /* Set swapper to enable I/O register access */
2809 s2io_set_swapper(sp);
2810
2811 /* Clear certain PCI/PCI-X fields after reset */
2812 if (sp->device_type == XFRAME_II_DEVICE) {
2813 /* Clear parity err detect bit */
2814 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
2815
2816 /* Clearing PCIX Ecc status register */
2817 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
2818
2819 /* Clearing PCI_STATUS error reflected here */
2820 writeq(BIT(62), &bar0->txpic_int_reg);
2821 }
2822
2823 /* Reset device statistics maintained by OS */
2824 memset(&sp->stats, 0, sizeof (struct net_device_stats));
2825
2427 /* SXE-002: Configure link and activity LED to turn it off */ 2826 /* SXE-002: Configure link and activity LED to turn it off */
2428 subid = sp->pdev->subsystem_device; 2827 subid = sp->pdev->subsystem_device;
2429 if ((subid & 0xFF) >= 0x07) { 2828 if (((subid & 0xFF) >= 0x07) &&
2829 (sp->device_type == XFRAME_I_DEVICE)) {
2430 val64 = readq(&bar0->gpio_control); 2830 val64 = readq(&bar0->gpio_control);
2431 val64 |= 0x0000800000000000ULL; 2831 val64 |= 0x0000800000000000ULL;
2432 writeq(val64, &bar0->gpio_control); 2832 writeq(val64, &bar0->gpio_control);
2433 val64 = 0x0411040400000000ULL; 2833 val64 = 0x0411040400000000ULL;
2434 writeq(val64, (void __iomem *) bar0 + 0x2700); 2834 writeq(val64, (void __iomem *) ((u8 *) bar0 + 0x2700));
2835 }
2836
2837 /*
2838 * Clear spurious ECC interrupts that would have occured on
2839 * XFRAME II cards after reset.
2840 */
2841 if (sp->device_type == XFRAME_II_DEVICE) {
2842 val64 = readq(&bar0->pcc_err_reg);
2843 writeq(val64, &bar0->pcc_err_reg);
2435 } 2844 }
2436 2845
2437 sp->device_enabled_once = FALSE; 2846 sp->device_enabled_once = FALSE;
2438} 2847}
2439 2848
2440/** 2849/**
2441 * s2io_set_swapper - to set the swapper controle on the card 2850 * s2io_set_swapper - to set the swapper controle on the card
2442 * @sp : private member of the device structure, 2851 * @sp : private member of the device structure,
2443 * pointer to the s2io_nic structure. 2852 * pointer to the s2io_nic structure.
2444 * Description: Function to set the swapper control on the card 2853 * Description: Function to set the swapper control on the card
2445 * correctly depending on the 'endianness' of the system. 2854 * correctly depending on the 'endianness' of the system.
2446 * Return value: 2855 * Return value:
2447 * SUCCESS on success and FAILURE on failure. 2856 * SUCCESS on success and FAILURE on failure.
2448 */ 2857 */
2449 2858
2450static int s2io_set_swapper(nic_t * sp) 2859int s2io_set_swapper(nic_t * sp)
2451{ 2860{
2452 struct net_device *dev = sp->dev; 2861 struct net_device *dev = sp->dev;
2453 XENA_dev_config_t __iomem *bar0 = sp->bar0; 2862 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2454 u64 val64, valt, valr; 2863 u64 val64, valt, valr;
2455 2864
2456 /* 2865 /*
2457 * Set proper endian settings and verify the same by reading 2866 * Set proper endian settings and verify the same by reading
2458 * the PIF Feed-back register. 2867 * the PIF Feed-back register.
2459 */ 2868 */
@@ -2505,8 +2914,9 @@ static int s2io_set_swapper(nic_t * sp)
2505 i++; 2914 i++;
2506 } 2915 }
2507 if(i == 4) { 2916 if(i == 4) {
2917 unsigned long long x = val64;
2508 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr "); 2918 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
2509 DBG_PRINT(ERR_DBG, "reads:0x%llx\n",val64); 2919 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
2510 return FAILURE; 2920 return FAILURE;
2511 } 2921 }
2512 } 2922 }
@@ -2514,8 +2924,8 @@ static int s2io_set_swapper(nic_t * sp)
2514 val64 &= 0xFFFF000000000000ULL; 2924 val64 &= 0xFFFF000000000000ULL;
2515 2925
2516#ifdef __BIG_ENDIAN 2926#ifdef __BIG_ENDIAN
2517 /* 2927 /*
2518 * The device by default set to a big endian format, so a 2928 * The device by default set to a big endian format, so a
2519 * big endian driver need not set anything. 2929 * big endian driver need not set anything.
2520 */ 2930 */
2521 val64 |= (SWAPPER_CTRL_TXP_FE | 2931 val64 |= (SWAPPER_CTRL_TXP_FE |
@@ -2531,9 +2941,9 @@ static int s2io_set_swapper(nic_t * sp)
2531 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE); 2941 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
2532 writeq(val64, &bar0->swapper_ctrl); 2942 writeq(val64, &bar0->swapper_ctrl);
2533#else 2943#else
2534 /* 2944 /*
2535 * Initially we enable all bits to make it accessible by the 2945 * Initially we enable all bits to make it accessible by the
2536 * driver, then we selectively enable only those bits that 2946 * driver, then we selectively enable only those bits that
2537 * we want to set. 2947 * we want to set.
2538 */ 2948 */
2539 val64 |= (SWAPPER_CTRL_TXP_FE | 2949 val64 |= (SWAPPER_CTRL_TXP_FE |
@@ -2555,8 +2965,8 @@ static int s2io_set_swapper(nic_t * sp)
2555#endif 2965#endif
2556 val64 = readq(&bar0->swapper_ctrl); 2966 val64 = readq(&bar0->swapper_ctrl);
2557 2967
2558 /* 2968 /*
2559 * Verifying if endian settings are accurate by reading a 2969 * Verifying if endian settings are accurate by reading a
2560 * feedback register. 2970 * feedback register.
2561 */ 2971 */
2562 val64 = readq(&bar0->pif_rd_swapper_fb); 2972 val64 = readq(&bar0->pif_rd_swapper_fb);
@@ -2576,55 +2986,63 @@ static int s2io_set_swapper(nic_t * sp)
2576 * Functions defined below concern the OS part of the driver * 2986 * Functions defined below concern the OS part of the driver *
2577 * ********************************************************* */ 2987 * ********************************************************* */
2578 2988
2579/** 2989/**
2580 * s2io_open - open entry point of the driver 2990 * s2io_open - open entry point of the driver
2581 * @dev : pointer to the device structure. 2991 * @dev : pointer to the device structure.
2582 * Description: 2992 * Description:
2583 * This function is the open entry point of the driver. It mainly calls a 2993 * This function is the open entry point of the driver. It mainly calls a
2584 * function to allocate Rx buffers and inserts them into the buffer 2994 * function to allocate Rx buffers and inserts them into the buffer
2585 * descriptors and then enables the Rx part of the NIC. 2995 * descriptors and then enables the Rx part of the NIC.
2586 * Return value: 2996 * Return value:
2587 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2997 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2588 * file on failure. 2998 * file on failure.
2589 */ 2999 */
2590 3000
2591static int s2io_open(struct net_device *dev) 3001int s2io_open(struct net_device *dev)
2592{ 3002{
2593 nic_t *sp = dev->priv; 3003 nic_t *sp = dev->priv;
2594 int err = 0; 3004 int err = 0;
2595 3005
2596 /* 3006 /*
2597 * Make sure you have link off by default every time 3007 * Make sure you have link off by default every time
2598 * Nic is initialized 3008 * Nic is initialized
2599 */ 3009 */
2600 netif_carrier_off(dev); 3010 netif_carrier_off(dev);
2601 sp->last_link_state = LINK_DOWN; 3011 sp->last_link_state = 0;
2602 3012
2603 /* Initialize H/W and enable interrupts */ 3013 /* Initialize H/W and enable interrupts */
2604 if (s2io_card_up(sp)) { 3014 if (s2io_card_up(sp)) {
2605 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n", 3015 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
2606 dev->name); 3016 dev->name);
2607 return -ENODEV; 3017 err = -ENODEV;
3018 goto hw_init_failed;
2608 } 3019 }
2609 3020
2610 /* After proper initialization of H/W, register ISR */ 3021 /* After proper initialization of H/W, register ISR */
2611 err = request_irq((int) sp->irq, s2io_isr, SA_SHIRQ, 3022 err = request_irq((int) sp->pdev->irq, s2io_isr, SA_SHIRQ,
2612 sp->name, dev); 3023 sp->name, dev);
2613 if (err) { 3024 if (err) {
2614 s2io_reset(sp);
2615 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n", 3025 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
2616 dev->name); 3026 dev->name);
2617 return err; 3027 goto isr_registration_failed;
2618 } 3028 }
2619 3029
2620 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) { 3030 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
2621 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n"); 3031 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
2622 s2io_reset(sp); 3032 err = -ENODEV;
2623 return -ENODEV; 3033 goto setting_mac_address_failed;
2624 } 3034 }
2625 3035
2626 netif_start_queue(dev); 3036 netif_start_queue(dev);
2627 return 0; 3037 return 0;
3038
3039setting_mac_address_failed:
3040 free_irq(sp->pdev->irq, dev);
3041isr_registration_failed:
3042 del_timer_sync(&sp->alarm_timer);
3043 s2io_reset(sp);
3044hw_init_failed:
3045 return err;
2628} 3046}
2629 3047
2630/** 3048/**
@@ -2640,16 +3058,15 @@ static int s2io_open(struct net_device *dev)
2640 * file on failure. 3058 * file on failure.
2641 */ 3059 */
2642 3060
2643static int s2io_close(struct net_device *dev) 3061int s2io_close(struct net_device *dev)
2644{ 3062{
2645 nic_t *sp = dev->priv; 3063 nic_t *sp = dev->priv;
2646
2647 flush_scheduled_work(); 3064 flush_scheduled_work();
2648 netif_stop_queue(dev); 3065 netif_stop_queue(dev);
2649 /* Reset card, kill tasklet and free Tx and Rx buffers. */ 3066 /* Reset card, kill tasklet and free Tx and Rx buffers. */
2650 s2io_card_down(sp); 3067 s2io_card_down(sp);
2651 3068
2652 free_irq(dev->irq, dev); 3069 free_irq(sp->pdev->irq, dev);
2653 sp->device_close_flag = TRUE; /* Device is shut down. */ 3070 sp->device_close_flag = TRUE; /* Device is shut down. */
2654 return 0; 3071 return 0;
2655} 3072}
@@ -2667,7 +3084,7 @@ static int s2io_close(struct net_device *dev)
2667 * 0 on success & 1 on failure. 3084 * 0 on success & 1 on failure.
2668 */ 3085 */
2669 3086
2670static int s2io_xmit(struct sk_buff *skb, struct net_device *dev) 3087int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
2671{ 3088{
2672 nic_t *sp = dev->priv; 3089 nic_t *sp = dev->priv;
2673 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off; 3090 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
@@ -2678,29 +3095,39 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
2678#ifdef NETIF_F_TSO 3095#ifdef NETIF_F_TSO
2679 int mss; 3096 int mss;
2680#endif 3097#endif
3098 u16 vlan_tag = 0;
3099 int vlan_priority = 0;
2681 mac_info_t *mac_control; 3100 mac_info_t *mac_control;
2682 struct config_param *config; 3101 struct config_param *config;
2683 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2684 3102
2685 mac_control = &sp->mac_control; 3103 mac_control = &sp->mac_control;
2686 config = &sp->config; 3104 config = &sp->config;
2687 3105
2688 DBG_PRINT(TX_DBG, "%s: In S2IO Tx routine\n", dev->name); 3106 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
2689 spin_lock_irqsave(&sp->tx_lock, flags); 3107 spin_lock_irqsave(&sp->tx_lock, flags);
2690
2691 if (atomic_read(&sp->card_state) == CARD_DOWN) { 3108 if (atomic_read(&sp->card_state) == CARD_DOWN) {
2692 DBG_PRINT(ERR_DBG, "%s: Card going down for reset\n", 3109 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
2693 dev->name); 3110 dev->name);
2694 spin_unlock_irqrestore(&sp->tx_lock, flags); 3111 spin_unlock_irqrestore(&sp->tx_lock, flags);
2695 return 1; 3112 dev_kfree_skb(skb);
3113 return 0;
2696 } 3114 }
2697 3115
2698 queue = 0; 3116 queue = 0;
2699 put_off = (u16) mac_control->tx_curr_put_info[queue].offset;
2700 get_off = (u16) mac_control->tx_curr_get_info[queue].offset;
2701 txdp = (TxD_t *) sp->list_info[queue][put_off].list_virt_addr;
2702 3117
2703 queue_len = mac_control->tx_curr_put_info[queue].fifo_len + 1; 3118 /* Get Fifo number to Transmit based on vlan priority */
3119 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3120 vlan_tag = vlan_tx_tag_get(skb);
3121 vlan_priority = vlan_tag >> 13;
3122 queue = config->fifo_mapping[vlan_priority];
3123 }
3124
3125 put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3126 get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
3127 txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
3128 list_virt_addr;
3129
3130 queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
2704 /* Avoid "put" pointer going beyond "get" pointer */ 3131 /* Avoid "put" pointer going beyond "get" pointer */
2705 if (txdp->Host_Control || (((put_off + 1) % queue_len) == get_off)) { 3132 if (txdp->Host_Control || (((put_off + 1) % queue_len) == get_off)) {
2706 DBG_PRINT(ERR_DBG, "Error in xmit, No free TXDs.\n"); 3133 DBG_PRINT(ERR_DBG, "Error in xmit, No free TXDs.\n");
@@ -2709,6 +3136,15 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
2709 spin_unlock_irqrestore(&sp->tx_lock, flags); 3136 spin_unlock_irqrestore(&sp->tx_lock, flags);
2710 return 0; 3137 return 0;
2711 } 3138 }
3139
3140 /* A buffer with no data will be dropped */
3141 if (!skb->len) {
3142 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3143 dev_kfree_skb(skb);
3144 spin_unlock_irqrestore(&sp->tx_lock, flags);
3145 return 0;
3146 }
3147
2712#ifdef NETIF_F_TSO 3148#ifdef NETIF_F_TSO
2713 mss = skb_shinfo(skb)->tso_size; 3149 mss = skb_shinfo(skb)->tso_size;
2714 if (mss) { 3150 if (mss) {
@@ -2720,9 +3156,9 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
2720 frg_cnt = skb_shinfo(skb)->nr_frags; 3156 frg_cnt = skb_shinfo(skb)->nr_frags;
2721 frg_len = skb->len - skb->data_len; 3157 frg_len = skb->len - skb->data_len;
2722 3158
2723 txdp->Host_Control = (unsigned long) skb;
2724 txdp->Buffer_Pointer = pci_map_single 3159 txdp->Buffer_Pointer = pci_map_single
2725 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE); 3160 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
3161 txdp->Host_Control = (unsigned long) skb;
2726 if (skb->ip_summed == CHECKSUM_HW) { 3162 if (skb->ip_summed == CHECKSUM_HW) {
2727 txdp->Control_2 |= 3163 txdp->Control_2 |=
2728 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN | 3164 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
@@ -2731,6 +3167,11 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
2731 3167
2732 txdp->Control_2 |= config->tx_intr_type; 3168 txdp->Control_2 |= config->tx_intr_type;
2733 3169
3170 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3171 txdp->Control_2 |= TXD_VLAN_ENABLE;
3172 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3173 }
3174
2734 txdp->Control_1 |= (TXD_BUFFER0_SIZE(frg_len) | 3175 txdp->Control_1 |= (TXD_BUFFER0_SIZE(frg_len) |
2735 TXD_GATHER_CODE_FIRST); 3176 TXD_GATHER_CODE_FIRST);
2736 txdp->Control_1 |= TXD_LIST_OWN_XENA; 3177 txdp->Control_1 |= TXD_LIST_OWN_XENA;
@@ -2738,6 +3179,9 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
2738 /* For fragmented SKB. */ 3179 /* For fragmented SKB. */
2739 for (i = 0; i < frg_cnt; i++) { 3180 for (i = 0; i < frg_cnt; i++) {
2740 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3181 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3182 /* A '0' length fragment will be ignored */
3183 if (!frag->size)
3184 continue;
2741 txdp++; 3185 txdp++;
2742 txdp->Buffer_Pointer = (u64) pci_map_page 3186 txdp->Buffer_Pointer = (u64) pci_map_page
2743 (sp->pdev, frag->page, frag->page_offset, 3187 (sp->pdev, frag->page, frag->page_offset,
@@ -2747,23 +3191,23 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
2747 txdp->Control_1 |= TXD_GATHER_CODE_LAST; 3191 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
2748 3192
2749 tx_fifo = mac_control->tx_FIFO_start[queue]; 3193 tx_fifo = mac_control->tx_FIFO_start[queue];
2750 val64 = sp->list_info[queue][put_off].list_phy_addr; 3194 val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
2751 writeq(val64, &tx_fifo->TxDL_Pointer); 3195 writeq(val64, &tx_fifo->TxDL_Pointer);
2752 3196
2753 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST | 3197 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
2754 TX_FIFO_LAST_LIST); 3198 TX_FIFO_LAST_LIST);
3199
2755#ifdef NETIF_F_TSO 3200#ifdef NETIF_F_TSO
2756 if (mss) 3201 if (mss)
2757 val64 |= TX_FIFO_SPECIAL_FUNC; 3202 val64 |= TX_FIFO_SPECIAL_FUNC;
2758#endif 3203#endif
2759 writeq(val64, &tx_fifo->List_Control); 3204 writeq(val64, &tx_fifo->List_Control);
2760 3205
2761 /* Perform a PCI read to flush previous writes */ 3206 mmiowb();
2762 val64 = readq(&bar0->general_int_status);
2763 3207
2764 put_off++; 3208 put_off++;
2765 put_off %= mac_control->tx_curr_put_info[queue].fifo_len + 1; 3209 put_off %= mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
2766 mac_control->tx_curr_put_info[queue].offset = put_off; 3210 mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
2767 3211
2768 /* Avoid "put" pointer going beyond "get" pointer */ 3212 /* Avoid "put" pointer going beyond "get" pointer */
2769 if (((put_off + 1) % queue_len) == get_off) { 3213 if (((put_off + 1) % queue_len) == get_off) {
@@ -2779,18 +3223,74 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
2779 return 0; 3223 return 0;
2780} 3224}
2781 3225
3226static void
3227s2io_alarm_handle(unsigned long data)
3228{
3229 nic_t *sp = (nic_t *)data;
3230
3231 alarm_intr_handler(sp);
3232 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
3233}
3234
3235static void s2io_txpic_intr_handle(nic_t *sp)
3236{
3237 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
3238 u64 val64;
3239
3240 val64 = readq(&bar0->pic_int_status);
3241 if (val64 & PIC_INT_GPIO) {
3242 val64 = readq(&bar0->gpio_int_reg);
3243 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
3244 (val64 & GPIO_INT_REG_LINK_UP)) {
3245 val64 |= GPIO_INT_REG_LINK_DOWN;
3246 val64 |= GPIO_INT_REG_LINK_UP;
3247 writeq(val64, &bar0->gpio_int_reg);
3248 goto masking;
3249 }
3250
3251 if (((sp->last_link_state == LINK_UP) &&
3252 (val64 & GPIO_INT_REG_LINK_DOWN)) ||
3253 ((sp->last_link_state == LINK_DOWN) &&
3254 (val64 & GPIO_INT_REG_LINK_UP))) {
3255 val64 = readq(&bar0->gpio_int_mask);
3256 val64 |= GPIO_INT_MASK_LINK_DOWN;
3257 val64 |= GPIO_INT_MASK_LINK_UP;
3258 writeq(val64, &bar0->gpio_int_mask);
3259 s2io_set_link((unsigned long)sp);
3260 }
3261masking:
3262 if (sp->last_link_state == LINK_UP) {
3263 /*enable down interrupt */
3264 val64 = readq(&bar0->gpio_int_mask);
3265 /* unmasks link down intr */
3266 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
3267 /* masks link up intr */
3268 val64 |= GPIO_INT_MASK_LINK_UP;
3269 writeq(val64, &bar0->gpio_int_mask);
3270 } else {
3271 /*enable UP Interrupt */
3272 val64 = readq(&bar0->gpio_int_mask);
3273 /* unmasks link up interrupt */
3274 val64 &= ~GPIO_INT_MASK_LINK_UP;
3275 /* masks link down interrupt */
3276 val64 |= GPIO_INT_MASK_LINK_DOWN;
3277 writeq(val64, &bar0->gpio_int_mask);
3278 }
3279 }
3280}
3281
2782/** 3282/**
2783 * s2io_isr - ISR handler of the device . 3283 * s2io_isr - ISR handler of the device .
2784 * @irq: the irq of the device. 3284 * @irq: the irq of the device.
2785 * @dev_id: a void pointer to the dev structure of the NIC. 3285 * @dev_id: a void pointer to the dev structure of the NIC.
2786 * @pt_regs: pointer to the registers pushed on the stack. 3286 * @pt_regs: pointer to the registers pushed on the stack.
2787 * Description: This function is the ISR handler of the device. It 3287 * Description: This function is the ISR handler of the device. It
2788 * identifies the reason for the interrupt and calls the relevant 3288 * identifies the reason for the interrupt and calls the relevant
2789 * service routines. As a contongency measure, this ISR allocates the 3289 * service routines. As a contongency measure, this ISR allocates the
2790 * recv buffers, if their numbers are below the panic value which is 3290 * recv buffers, if their numbers are below the panic value which is
2791 * presently set to 25% of the original number of rcv buffers allocated. 3291 * presently set to 25% of the original number of rcv buffers allocated.
2792 * Return value: 3292 * Return value:
2793 * IRQ_HANDLED: will be returned if IRQ was handled by this routine 3293 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
2794 * IRQ_NONE: will be returned if interrupt is not from our device 3294 * IRQ_NONE: will be returned if interrupt is not from our device
2795 */ 3295 */
2796static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs) 3296static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
@@ -2798,40 +3298,31 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
2798 struct net_device *dev = (struct net_device *) dev_id; 3298 struct net_device *dev = (struct net_device *) dev_id;
2799 nic_t *sp = dev->priv; 3299 nic_t *sp = dev->priv;
2800 XENA_dev_config_t __iomem *bar0 = sp->bar0; 3300 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2801#ifndef CONFIG_S2IO_NAPI 3301 int i;
2802 int i, ret; 3302 u64 reason = 0, val64;
2803#endif
2804 u64 reason = 0;
2805 mac_info_t *mac_control; 3303 mac_info_t *mac_control;
2806 struct config_param *config; 3304 struct config_param *config;
2807 3305
3306 atomic_inc(&sp->isr_cnt);
2808 mac_control = &sp->mac_control; 3307 mac_control = &sp->mac_control;
2809 config = &sp->config; 3308 config = &sp->config;
2810 3309
2811 /* 3310 /*
2812 * Identify the cause for interrupt and call the appropriate 3311 * Identify the cause for interrupt and call the appropriate
2813 * interrupt handler. Causes for the interrupt could be; 3312 * interrupt handler. Causes for the interrupt could be;
2814 * 1. Rx of packet. 3313 * 1. Rx of packet.
2815 * 2. Tx complete. 3314 * 2. Tx complete.
2816 * 3. Link down. 3315 * 3. Link down.
2817 * 4. Error in any functional blocks of the NIC. 3316 * 4. Error in any functional blocks of the NIC.
2818 */ 3317 */
2819 reason = readq(&bar0->general_int_status); 3318 reason = readq(&bar0->general_int_status);
2820 3319
2821 if (!reason) { 3320 if (!reason) {
2822 /* The interrupt was not raised by Xena. */ 3321 /* The interrupt was not raised by Xena. */
3322 atomic_dec(&sp->isr_cnt);
2823 return IRQ_NONE; 3323 return IRQ_NONE;
2824 } 3324 }
2825 3325
2826 /* If Intr is because of Tx Traffic */
2827 if (reason & GEN_INTR_TXTRAFFIC) {
2828 tx_intr_handler(sp);
2829 }
2830
2831 /* If Intr is because of an error */
2832 if (reason & (GEN_ERROR_INTR))
2833 alarm_intr_handler(sp);
2834
2835#ifdef CONFIG_S2IO_NAPI 3326#ifdef CONFIG_S2IO_NAPI
2836 if (reason & GEN_INTR_RXTRAFFIC) { 3327 if (reason & GEN_INTR_RXTRAFFIC) {
2837 if (netif_rx_schedule_prep(dev)) { 3328 if (netif_rx_schedule_prep(dev)) {
@@ -2843,17 +3334,43 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
2843#else 3334#else
2844 /* If Intr is because of Rx Traffic */ 3335 /* If Intr is because of Rx Traffic */
2845 if (reason & GEN_INTR_RXTRAFFIC) { 3336 if (reason & GEN_INTR_RXTRAFFIC) {
2846 rx_intr_handler(sp); 3337 /*
3338 * rx_traffic_int reg is an R1 register, writing all 1's
3339 * will ensure that the actual interrupt causing bit get's
3340 * cleared and hence a read can be avoided.
3341 */
3342 val64 = 0xFFFFFFFFFFFFFFFFULL;
3343 writeq(val64, &bar0->rx_traffic_int);
3344 for (i = 0; i < config->rx_ring_num; i++) {
3345 rx_intr_handler(&mac_control->rings[i]);
3346 }
2847 } 3347 }
2848#endif 3348#endif
2849 3349
2850 /* 3350 /* If Intr is because of Tx Traffic */
2851 * If the Rx buffer count is below the panic threshold then 3351 if (reason & GEN_INTR_TXTRAFFIC) {
2852 * reallocate the buffers from the interrupt handler itself, 3352 /*
3353 * tx_traffic_int reg is an R1 register, writing all 1's
3354 * will ensure that the actual interrupt causing bit get's
3355 * cleared and hence a read can be avoided.
3356 */
3357 val64 = 0xFFFFFFFFFFFFFFFFULL;
3358 writeq(val64, &bar0->tx_traffic_int);
3359
3360 for (i = 0; i < config->tx_fifo_num; i++)
3361 tx_intr_handler(&mac_control->fifos[i]);
3362 }
3363
3364 if (reason & GEN_INTR_TXPIC)
3365 s2io_txpic_intr_handle(sp);
3366 /*
3367 * If the Rx buffer count is below the panic threshold then
3368 * reallocate the buffers from the interrupt handler itself,
2853 * else schedule a tasklet to reallocate the buffers. 3369 * else schedule a tasklet to reallocate the buffers.
2854 */ 3370 */
2855#ifndef CONFIG_S2IO_NAPI 3371#ifndef CONFIG_S2IO_NAPI
2856 for (i = 0; i < config->rx_ring_num; i++) { 3372 for (i = 0; i < config->rx_ring_num; i++) {
3373 int ret;
2857 int rxb_size = atomic_read(&sp->rx_bufs_left[i]); 3374 int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
2858 int level = rx_buffer_level(sp, rxb_size, i); 3375 int level = rx_buffer_level(sp, rxb_size, i);
2859 3376
@@ -2865,6 +3382,7 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
2865 dev->name); 3382 dev->name);
2866 DBG_PRINT(ERR_DBG, " in ISR!!\n"); 3383 DBG_PRINT(ERR_DBG, " in ISR!!\n");
2867 clear_bit(0, (&sp->tasklet_status)); 3384 clear_bit(0, (&sp->tasklet_status));
3385 atomic_dec(&sp->isr_cnt);
2868 return IRQ_HANDLED; 3386 return IRQ_HANDLED;
2869 } 3387 }
2870 clear_bit(0, (&sp->tasklet_status)); 3388 clear_bit(0, (&sp->tasklet_status));
@@ -2874,33 +3392,69 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
2874 } 3392 }
2875#endif 3393#endif
2876 3394
3395 atomic_dec(&sp->isr_cnt);
2877 return IRQ_HANDLED; 3396 return IRQ_HANDLED;
2878} 3397}
2879 3398
2880/** 3399/**
2881 * s2io_get_stats - Updates the device statistics structure. 3400 * s2io_updt_stats -
3401 */
3402static void s2io_updt_stats(nic_t *sp)
3403{
3404 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3405 u64 val64;
3406 int cnt = 0;
3407
3408 if (atomic_read(&sp->card_state) == CARD_UP) {
3409 /* Apprx 30us on a 133 MHz bus */
3410 val64 = SET_UPDT_CLICKS(10) |
3411 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
3412 writeq(val64, &bar0->stat_cfg);
3413 do {
3414 udelay(100);
3415 val64 = readq(&bar0->stat_cfg);
3416 if (!(val64 & BIT(0)))
3417 break;
3418 cnt++;
3419 if (cnt == 5)
3420 break; /* Updt failed */
3421 } while(1);
3422 }
3423}
3424
3425/**
3426 * s2io_get_stats - Updates the device statistics structure.
2882 * @dev : pointer to the device structure. 3427 * @dev : pointer to the device structure.
2883 * Description: 3428 * Description:
2884 * This function updates the device statistics structure in the s2io_nic 3429 * This function updates the device statistics structure in the s2io_nic
2885 * structure and returns a pointer to the same. 3430 * structure and returns a pointer to the same.
2886 * Return value: 3431 * Return value:
2887 * pointer to the updated net_device_stats structure. 3432 * pointer to the updated net_device_stats structure.
2888 */ 3433 */
2889 3434
2890static struct net_device_stats *s2io_get_stats(struct net_device *dev) 3435struct net_device_stats *s2io_get_stats(struct net_device *dev)
2891{ 3436{
2892 nic_t *sp = dev->priv; 3437 nic_t *sp = dev->priv;
2893 mac_info_t *mac_control; 3438 mac_info_t *mac_control;
2894 struct config_param *config; 3439 struct config_param *config;
2895 3440
3441
2896 mac_control = &sp->mac_control; 3442 mac_control = &sp->mac_control;
2897 config = &sp->config; 3443 config = &sp->config;
2898 3444
2899 sp->stats.tx_errors = mac_control->stats_info->tmac_any_err_frms; 3445 /* Configure Stats for immediate updt */
2900 sp->stats.rx_errors = mac_control->stats_info->rmac_drop_frms; 3446 s2io_updt_stats(sp);
2901 sp->stats.multicast = mac_control->stats_info->rmac_vld_mcst_frms; 3447
3448 sp->stats.tx_packets =
3449 le32_to_cpu(mac_control->stats_info->tmac_frms);
3450 sp->stats.tx_errors =
3451 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
3452 sp->stats.rx_errors =
3453 le32_to_cpu(mac_control->stats_info->rmac_drop_frms);
3454 sp->stats.multicast =
3455 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
2902 sp->stats.rx_length_errors = 3456 sp->stats.rx_length_errors =
2903 mac_control->stats_info->rmac_long_frms; 3457 le32_to_cpu(mac_control->stats_info->rmac_long_frms);
2904 3458
2905 return (&sp->stats); 3459 return (&sp->stats);
2906} 3460}
@@ -2909,8 +3463,8 @@ static struct net_device_stats *s2io_get_stats(struct net_device *dev)
2909 * s2io_set_multicast - entry point for multicast address enable/disable. 3463 * s2io_set_multicast - entry point for multicast address enable/disable.
2910 * @dev : pointer to the device structure 3464 * @dev : pointer to the device structure
2911 * Description: 3465 * Description:
2912 * This function is a driver entry point which gets called by the kernel 3466 * This function is a driver entry point which gets called by the kernel
2913 * whenever multicast addresses must be enabled/disabled. This also gets 3467 * whenever multicast addresses must be enabled/disabled. This also gets
2914 * called to set/reset promiscuous mode. Depending on the deivce flag, we 3468 * called to set/reset promiscuous mode. Depending on the deivce flag, we
2915 * determine, if multicast address must be enabled or if promiscuous mode 3469 * determine, if multicast address must be enabled or if promiscuous mode
2916 * is to be disabled etc. 3470 * is to be disabled etc.
@@ -2948,6 +3502,8 @@ static void s2io_set_multicast(struct net_device *dev)
2948 /* Disable all Multicast addresses */ 3502 /* Disable all Multicast addresses */
2949 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr), 3503 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
2950 &bar0->rmac_addr_data0_mem); 3504 &bar0->rmac_addr_data0_mem);
3505 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
3506 &bar0->rmac_addr_data1_mem);
2951 val64 = RMAC_ADDR_CMD_MEM_WE | 3507 val64 = RMAC_ADDR_CMD_MEM_WE |
2952 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | 3508 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
2953 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos); 3509 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
@@ -3010,7 +3566,7 @@ static void s2io_set_multicast(struct net_device *dev)
3010 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr), 3566 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
3011 &bar0->rmac_addr_data0_mem); 3567 &bar0->rmac_addr_data0_mem);
3012 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL), 3568 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
3013 &bar0->rmac_addr_data1_mem); 3569 &bar0->rmac_addr_data1_mem);
3014 val64 = RMAC_ADDR_CMD_MEM_WE | 3570 val64 = RMAC_ADDR_CMD_MEM_WE |
3015 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | 3571 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
3016 RMAC_ADDR_CMD_MEM_OFFSET 3572 RMAC_ADDR_CMD_MEM_OFFSET
@@ -3039,8 +3595,7 @@ static void s2io_set_multicast(struct net_device *dev)
3039 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr), 3595 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
3040 &bar0->rmac_addr_data0_mem); 3596 &bar0->rmac_addr_data0_mem);
3041 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL), 3597 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
3042 &bar0->rmac_addr_data1_mem); 3598 &bar0->rmac_addr_data1_mem);
3043
3044 val64 = RMAC_ADDR_CMD_MEM_WE | 3599 val64 = RMAC_ADDR_CMD_MEM_WE |
3045 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | 3600 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
3046 RMAC_ADDR_CMD_MEM_OFFSET 3601 RMAC_ADDR_CMD_MEM_OFFSET
@@ -3059,12 +3614,12 @@ static void s2io_set_multicast(struct net_device *dev)
3059} 3614}
3060 3615
3061/** 3616/**
3062 * s2io_set_mac_addr - Programs the Xframe mac address 3617 * s2io_set_mac_addr - Programs the Xframe mac address
3063 * @dev : pointer to the device structure. 3618 * @dev : pointer to the device structure.
3064 * @addr: a uchar pointer to the new mac address which is to be set. 3619 * @addr: a uchar pointer to the new mac address which is to be set.
3065 * Description : This procedure will program the Xframe to receive 3620 * Description : This procedure will program the Xframe to receive
3066 * frames with new Mac Address 3621 * frames with new Mac Address
3067 * Return value: SUCCESS on success and an appropriate (-)ve integer 3622 * Return value: SUCCESS on success and an appropriate (-)ve integer
3068 * as defined in errno.h file on failure. 3623 * as defined in errno.h file on failure.
3069 */ 3624 */
3070 3625
@@ -3075,10 +3630,10 @@ int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
3075 register u64 val64, mac_addr = 0; 3630 register u64 val64, mac_addr = 0;
3076 int i; 3631 int i;
3077 3632
3078 /* 3633 /*
3079 * Set the new MAC address as the new unicast filter and reflect this 3634 * Set the new MAC address as the new unicast filter and reflect this
3080 * change on the device address registered with the OS. It will be 3635 * change on the device address registered with the OS. It will be
3081 * at offset 0. 3636 * at offset 0.
3082 */ 3637 */
3083 for (i = 0; i < ETH_ALEN; i++) { 3638 for (i = 0; i < ETH_ALEN; i++) {
3084 mac_addr <<= 8; 3639 mac_addr <<= 8;
@@ -3102,12 +3657,12 @@ int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
3102} 3657}
3103 3658
3104/** 3659/**
3105 * s2io_ethtool_sset - Sets different link parameters. 3660 * s2io_ethtool_sset - Sets different link parameters.
3106 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. 3661 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
3107 * @info: pointer to the structure with parameters given by ethtool to set 3662 * @info: pointer to the structure with parameters given by ethtool to set
3108 * link information. 3663 * link information.
3109 * Description: 3664 * Description:
3110 * The function sets different link parameters provided by the user onto 3665 * The function sets different link parameters provided by the user onto
3111 * the NIC. 3666 * the NIC.
3112 * Return value: 3667 * Return value:
3113 * 0 on success. 3668 * 0 on success.
@@ -3129,7 +3684,7 @@ static int s2io_ethtool_sset(struct net_device *dev,
3129} 3684}
3130 3685
3131/** 3686/**
3132 * s2io_ethtol_gset - Return link specific information. 3687 * s2io_ethtol_gset - Return link specific information.
3133 * @sp : private member of the device structure, pointer to the 3688 * @sp : private member of the device structure, pointer to the
3134 * s2io_nic structure. 3689 * s2io_nic structure.
3135 * @info : pointer to the structure with parameters given by ethtool 3690 * @info : pointer to the structure with parameters given by ethtool
@@ -3161,8 +3716,8 @@ static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
3161} 3716}
3162 3717
3163/** 3718/**
3164 * s2io_ethtool_gdrvinfo - Returns driver specific information. 3719 * s2io_ethtool_gdrvinfo - Returns driver specific information.
3165 * @sp : private member of the device structure, which is a pointer to the 3720 * @sp : private member of the device structure, which is a pointer to the
3166 * s2io_nic structure. 3721 * s2io_nic structure.
3167 * @info : pointer to the structure with parameters given by ethtool to 3722 * @info : pointer to the structure with parameters given by ethtool to
3168 * return driver information. 3723 * return driver information.
@@ -3190,9 +3745,9 @@ static void s2io_ethtool_gdrvinfo(struct net_device *dev,
3190 3745
3191/** 3746/**
3192 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer. 3747 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
3193 * @sp: private member of the device structure, which is a pointer to the 3748 * @sp: private member of the device structure, which is a pointer to the
3194 * s2io_nic structure. 3749 * s2io_nic structure.
3195 * @regs : pointer to the structure with parameters given by ethtool for 3750 * @regs : pointer to the structure with parameters given by ethtool for
3196 * dumping the registers. 3751 * dumping the registers.
3197 * @reg_space: The input argumnet into which all the registers are dumped. 3752 * @reg_space: The input argumnet into which all the registers are dumped.
3198 * Description: 3753 * Description:
@@ -3221,11 +3776,11 @@ static void s2io_ethtool_gregs(struct net_device *dev,
3221 3776
3222/** 3777/**
3223 * s2io_phy_id - timer function that alternates adapter LED. 3778 * s2io_phy_id - timer function that alternates adapter LED.
3224 * @data : address of the private member of the device structure, which 3779 * @data : address of the private member of the device structure, which
3225 * is a pointer to the s2io_nic structure, provided as an u32. 3780 * is a pointer to the s2io_nic structure, provided as an u32.
3226 * Description: This is actually the timer function that alternates the 3781 * Description: This is actually the timer function that alternates the
3227 * adapter LED bit of the adapter control bit to set/reset every time on 3782 * adapter LED bit of the adapter control bit to set/reset every time on
3228 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks 3783 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
3229 * once every second. 3784 * once every second.
3230*/ 3785*/
3231static void s2io_phy_id(unsigned long data) 3786static void s2io_phy_id(unsigned long data)
@@ -3236,7 +3791,8 @@ static void s2io_phy_id(unsigned long data)
3236 u16 subid; 3791 u16 subid;
3237 3792
3238 subid = sp->pdev->subsystem_device; 3793 subid = sp->pdev->subsystem_device;
3239 if ((subid & 0xFF) >= 0x07) { 3794 if ((sp->device_type == XFRAME_II_DEVICE) ||
3795 ((subid & 0xFF) >= 0x07)) {
3240 val64 = readq(&bar0->gpio_control); 3796 val64 = readq(&bar0->gpio_control);
3241 val64 ^= GPIO_CTRL_GPIO_0; 3797 val64 ^= GPIO_CTRL_GPIO_0;
3242 writeq(val64, &bar0->gpio_control); 3798 writeq(val64, &bar0->gpio_control);
@@ -3253,12 +3809,12 @@ static void s2io_phy_id(unsigned long data)
3253 * s2io_ethtool_idnic - To physically identify the nic on the system. 3809 * s2io_ethtool_idnic - To physically identify the nic on the system.
3254 * @sp : private member of the device structure, which is a pointer to the 3810 * @sp : private member of the device structure, which is a pointer to the
3255 * s2io_nic structure. 3811 * s2io_nic structure.
3256 * @id : pointer to the structure with identification parameters given by 3812 * @id : pointer to the structure with identification parameters given by
3257 * ethtool. 3813 * ethtool.
3258 * Description: Used to physically identify the NIC on the system. 3814 * Description: Used to physically identify the NIC on the system.
3259 * The Link LED will blink for a time specified by the user for 3815 * The Link LED will blink for a time specified by the user for
3260 * identification. 3816 * identification.
3261 * NOTE: The Link has to be Up to be able to blink the LED. Hence 3817 * NOTE: The Link has to be Up to be able to blink the LED. Hence
3262 * identification is possible only if it's link is up. 3818 * identification is possible only if it's link is up.
3263 * Return value: 3819 * Return value:
3264 * int , returns 0 on success 3820 * int , returns 0 on success
@@ -3273,7 +3829,8 @@ static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
3273 3829
3274 subid = sp->pdev->subsystem_device; 3830 subid = sp->pdev->subsystem_device;
3275 last_gpio_ctrl_val = readq(&bar0->gpio_control); 3831 last_gpio_ctrl_val = readq(&bar0->gpio_control);
3276 if ((subid & 0xFF) < 0x07) { 3832 if ((sp->device_type == XFRAME_I_DEVICE) &&
3833 ((subid & 0xFF) < 0x07)) {
3277 val64 = readq(&bar0->adapter_control); 3834 val64 = readq(&bar0->adapter_control);
3278 if (!(val64 & ADAPTER_CNTL_EN)) { 3835 if (!(val64 & ADAPTER_CNTL_EN)) {
3279 printk(KERN_ERR 3836 printk(KERN_ERR
@@ -3288,12 +3845,12 @@ static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
3288 } 3845 }
3289 mod_timer(&sp->id_timer, jiffies); 3846 mod_timer(&sp->id_timer, jiffies);
3290 if (data) 3847 if (data)
3291 msleep(data * 1000); 3848 msleep_interruptible(data * HZ);
3292 else 3849 else
3293 msleep(0xFFFFFFFF); 3850 msleep_interruptible(MAX_FLICKER_TIME);
3294 del_timer_sync(&sp->id_timer); 3851 del_timer_sync(&sp->id_timer);
3295 3852
3296 if (CARDS_WITH_FAULTY_LINK_INDICATORS(subid)) { 3853 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
3297 writeq(last_gpio_ctrl_val, &bar0->gpio_control); 3854 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
3298 last_gpio_ctrl_val = readq(&bar0->gpio_control); 3855 last_gpio_ctrl_val = readq(&bar0->gpio_control);
3299 } 3856 }
@@ -3303,7 +3860,8 @@ static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
3303 3860
3304/** 3861/**
3305 * s2io_ethtool_getpause_data -Pause frame frame generation and reception. 3862 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
3306 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. 3863 * @sp : private member of the device structure, which is a pointer to the
3864 * s2io_nic structure.
3307 * @ep : pointer to the structure with pause parameters given by ethtool. 3865 * @ep : pointer to the structure with pause parameters given by ethtool.
3308 * Description: 3866 * Description:
3309 * Returns the Pause frame generation and reception capability of the NIC. 3867 * Returns the Pause frame generation and reception capability of the NIC.
@@ -3327,7 +3885,7 @@ static void s2io_ethtool_getpause_data(struct net_device *dev,
3327 3885
3328/** 3886/**
3329 * s2io_ethtool_setpause_data - set/reset pause frame generation. 3887 * s2io_ethtool_setpause_data - set/reset pause frame generation.
3330 * @sp : private member of the device structure, which is a pointer to the 3888 * @sp : private member of the device structure, which is a pointer to the
3331 * s2io_nic structure. 3889 * s2io_nic structure.
3332 * @ep : pointer to the structure with pause parameters given by ethtool. 3890 * @ep : pointer to the structure with pause parameters given by ethtool.
3333 * Description: 3891 * Description:
@@ -3338,7 +3896,7 @@ static void s2io_ethtool_getpause_data(struct net_device *dev,
3338 */ 3896 */
3339 3897
3340static int s2io_ethtool_setpause_data(struct net_device *dev, 3898static int s2io_ethtool_setpause_data(struct net_device *dev,
3341 struct ethtool_pauseparam *ep) 3899 struct ethtool_pauseparam *ep)
3342{ 3900{
3343 u64 val64; 3901 u64 val64;
3344 nic_t *sp = dev->priv; 3902 nic_t *sp = dev->priv;
@@ -3359,13 +3917,13 @@ static int s2io_ethtool_setpause_data(struct net_device *dev,
3359 3917
3360/** 3918/**
3361 * read_eeprom - reads 4 bytes of data from user given offset. 3919 * read_eeprom - reads 4 bytes of data from user given offset.
3362 * @sp : private member of the device structure, which is a pointer to the 3920 * @sp : private member of the device structure, which is a pointer to the
3363 * s2io_nic structure. 3921 * s2io_nic structure.
3364 * @off : offset at which the data must be written 3922 * @off : offset at which the data must be written
3365 * @data : Its an output parameter where the data read at the given 3923 * @data : Its an output parameter where the data read at the given
3366 * offset is stored. 3924 * offset is stored.
3367 * Description: 3925 * Description:
3368 * Will read 4 bytes of data from the user given offset and return the 3926 * Will read 4 bytes of data from the user given offset and return the
3369 * read data. 3927 * read data.
3370 * NOTE: Will allow to read only part of the EEPROM visible through the 3928 * NOTE: Will allow to read only part of the EEPROM visible through the
3371 * I2C bus. 3929 * I2C bus.
@@ -3406,7 +3964,7 @@ static int read_eeprom(nic_t * sp, int off, u32 * data)
3406 * s2io_nic structure. 3964 * s2io_nic structure.
3407 * @off : offset at which the data must be written 3965 * @off : offset at which the data must be written
3408 * @data : The data that is to be written 3966 * @data : The data that is to be written
3409 * @cnt : Number of bytes of the data that are actually to be written into 3967 * @cnt : Number of bytes of the data that are actually to be written into
3410 * the Eeprom. (max of 3) 3968 * the Eeprom. (max of 3)
3411 * Description: 3969 * Description:
3412 * Actually writes the relevant part of the data value into the Eeprom 3970 * Actually writes the relevant part of the data value into the Eeprom
@@ -3443,7 +4001,7 @@ static int write_eeprom(nic_t * sp, int off, u32 data, int cnt)
3443/** 4001/**
3444 * s2io_ethtool_geeprom - reads the value stored in the Eeprom. 4002 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
3445 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. 4003 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
3446 * @eeprom : pointer to the user level structure provided by ethtool, 4004 * @eeprom : pointer to the user level structure provided by ethtool,
3447 * containing all relevant information. 4005 * containing all relevant information.
3448 * @data_buf : user defined value to be written into Eeprom. 4006 * @data_buf : user defined value to be written into Eeprom.
3449 * Description: Reads the values stored in the Eeprom at given offset 4007 * Description: Reads the values stored in the Eeprom at given offset
@@ -3454,7 +4012,7 @@ static int write_eeprom(nic_t * sp, int off, u32 data, int cnt)
3454 */ 4012 */
3455 4013
3456static int s2io_ethtool_geeprom(struct net_device *dev, 4014static int s2io_ethtool_geeprom(struct net_device *dev,
3457 struct ethtool_eeprom *eeprom, u8 * data_buf) 4015 struct ethtool_eeprom *eeprom, u8 * data_buf)
3458{ 4016{
3459 u32 data, i, valid; 4017 u32 data, i, valid;
3460 nic_t *sp = dev->priv; 4018 nic_t *sp = dev->priv;
@@ -3479,7 +4037,7 @@ static int s2io_ethtool_geeprom(struct net_device *dev,
3479 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom 4037 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
3480 * @sp : private member of the device structure, which is a pointer to the 4038 * @sp : private member of the device structure, which is a pointer to the
3481 * s2io_nic structure. 4039 * s2io_nic structure.
3482 * @eeprom : pointer to the user level structure provided by ethtool, 4040 * @eeprom : pointer to the user level structure provided by ethtool,
3483 * containing all relevant information. 4041 * containing all relevant information.
3484 * @data_buf ; user defined value to be written into Eeprom. 4042 * @data_buf ; user defined value to be written into Eeprom.
3485 * Description: 4043 * Description:
@@ -3527,8 +4085,8 @@ static int s2io_ethtool_seeprom(struct net_device *dev,
3527} 4085}
3528 4086
3529/** 4087/**
3530 * s2io_register_test - reads and writes into all clock domains. 4088 * s2io_register_test - reads and writes into all clock domains.
3531 * @sp : private member of the device structure, which is a pointer to the 4089 * @sp : private member of the device structure, which is a pointer to the
3532 * s2io_nic structure. 4090 * s2io_nic structure.
3533 * @data : variable that returns the result of each of the test conducted b 4091 * @data : variable that returns the result of each of the test conducted b
3534 * by the driver. 4092 * by the driver.
@@ -3545,8 +4103,8 @@ static int s2io_register_test(nic_t * sp, uint64_t * data)
3545 u64 val64 = 0; 4103 u64 val64 = 0;
3546 int fail = 0; 4104 int fail = 0;
3547 4105
3548 val64 = readq(&bar0->pcc_enable); 4106 val64 = readq(&bar0->pif_rd_swapper_fb);
3549 if (val64 != 0xff00000000000000ULL) { 4107 if (val64 != 0x123456789abcdefULL) {
3550 fail = 1; 4108 fail = 1;
3551 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n"); 4109 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
3552 } 4110 }
@@ -3590,13 +4148,13 @@ static int s2io_register_test(nic_t * sp, uint64_t * data)
3590} 4148}
3591 4149
3592/** 4150/**
3593 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed. 4151 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
3594 * @sp : private member of the device structure, which is a pointer to the 4152 * @sp : private member of the device structure, which is a pointer to the
3595 * s2io_nic structure. 4153 * s2io_nic structure.
3596 * @data:variable that returns the result of each of the test conducted by 4154 * @data:variable that returns the result of each of the test conducted by
3597 * the driver. 4155 * the driver.
3598 * Description: 4156 * Description:
3599 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL 4157 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
3600 * register. 4158 * register.
3601 * Return value: 4159 * Return value:
3602 * 0 on success. 4160 * 0 on success.
@@ -3661,14 +4219,14 @@ static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
3661 4219
3662/** 4220/**
3663 * s2io_bist_test - invokes the MemBist test of the card . 4221 * s2io_bist_test - invokes the MemBist test of the card .
3664 * @sp : private member of the device structure, which is a pointer to the 4222 * @sp : private member of the device structure, which is a pointer to the
3665 * s2io_nic structure. 4223 * s2io_nic structure.
3666 * @data:variable that returns the result of each of the test conducted by 4224 * @data:variable that returns the result of each of the test conducted by
3667 * the driver. 4225 * the driver.
3668 * Description: 4226 * Description:
3669 * This invokes the MemBist test of the card. We give around 4227 * This invokes the MemBist test of the card. We give around
3670 * 2 secs time for the Test to complete. If it's still not complete 4228 * 2 secs time for the Test to complete. If it's still not complete
3671 * within this peiod, we consider that the test failed. 4229 * within this peiod, we consider that the test failed.
3672 * Return value: 4230 * Return value:
3673 * 0 on success and -1 on failure. 4231 * 0 on success and -1 on failure.
3674 */ 4232 */
@@ -3697,13 +4255,13 @@ static int s2io_bist_test(nic_t * sp, uint64_t * data)
3697} 4255}
3698 4256
3699/** 4257/**
3700 * s2io-link_test - verifies the link state of the nic 4258 * s2io-link_test - verifies the link state of the nic
3701 * @sp ; private member of the device structure, which is a pointer to the 4259 * @sp ; private member of the device structure, which is a pointer to the
3702 * s2io_nic structure. 4260 * s2io_nic structure.
3703 * @data: variable that returns the result of each of the test conducted by 4261 * @data: variable that returns the result of each of the test conducted by
3704 * the driver. 4262 * the driver.
3705 * Description: 4263 * Description:
3706 * The function verifies the link state of the NIC and updates the input 4264 * The function verifies the link state of the NIC and updates the input
3707 * argument 'data' appropriately. 4265 * argument 'data' appropriately.
3708 * Return value: 4266 * Return value:
3709 * 0 on success. 4267 * 0 on success.
@@ -3722,13 +4280,13 @@ static int s2io_link_test(nic_t * sp, uint64_t * data)
3722} 4280}
3723 4281
3724/** 4282/**
3725 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC 4283 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
3726 * @sp - private member of the device structure, which is a pointer to the 4284 * @sp - private member of the device structure, which is a pointer to the
3727 * s2io_nic structure. 4285 * s2io_nic structure.
3728 * @data - variable that returns the result of each of the test 4286 * @data - variable that returns the result of each of the test
3729 * conducted by the driver. 4287 * conducted by the driver.
3730 * Description: 4288 * Description:
3731 * This is one of the offline test that tests the read and write 4289 * This is one of the offline test that tests the read and write
3732 * access to the RldRam chip on the NIC. 4290 * access to the RldRam chip on the NIC.
3733 * Return value: 4291 * Return value:
3734 * 0 on success. 4292 * 0 on success.
@@ -3833,7 +4391,7 @@ static int s2io_rldram_test(nic_t * sp, uint64_t * data)
3833 * s2io_nic structure. 4391 * s2io_nic structure.
3834 * @ethtest : pointer to a ethtool command specific structure that will be 4392 * @ethtest : pointer to a ethtool command specific structure that will be
3835 * returned to the user. 4393 * returned to the user.
3836 * @data : variable that returns the result of each of the test 4394 * @data : variable that returns the result of each of the test
3837 * conducted by the driver. 4395 * conducted by the driver.
3838 * Description: 4396 * Description:
3839 * This function conducts 6 tests ( 4 offline and 2 online) to determine 4397 * This function conducts 6 tests ( 4 offline and 2 online) to determine
@@ -3851,23 +4409,18 @@ static void s2io_ethtool_test(struct net_device *dev,
3851 4409
3852 if (ethtest->flags == ETH_TEST_FL_OFFLINE) { 4410 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
3853 /* Offline Tests. */ 4411 /* Offline Tests. */
3854 if (orig_state) { 4412 if (orig_state)
3855 s2io_close(sp->dev); 4413 s2io_close(sp->dev);
3856 s2io_set_swapper(sp);
3857 } else
3858 s2io_set_swapper(sp);
3859 4414
3860 if (s2io_register_test(sp, &data[0])) 4415 if (s2io_register_test(sp, &data[0]))
3861 ethtest->flags |= ETH_TEST_FL_FAILED; 4416 ethtest->flags |= ETH_TEST_FL_FAILED;
3862 4417
3863 s2io_reset(sp); 4418 s2io_reset(sp);
3864 s2io_set_swapper(sp);
3865 4419
3866 if (s2io_rldram_test(sp, &data[3])) 4420 if (s2io_rldram_test(sp, &data[3]))
3867 ethtest->flags |= ETH_TEST_FL_FAILED; 4421 ethtest->flags |= ETH_TEST_FL_FAILED;
3868 4422
3869 s2io_reset(sp); 4423 s2io_reset(sp);
3870 s2io_set_swapper(sp);
3871 4424
3872 if (s2io_eeprom_test(sp, &data[1])) 4425 if (s2io_eeprom_test(sp, &data[1]))
3873 ethtest->flags |= ETH_TEST_FL_FAILED; 4426 ethtest->flags |= ETH_TEST_FL_FAILED;
@@ -3910,61 +4463,111 @@ static void s2io_get_ethtool_stats(struct net_device *dev,
3910 nic_t *sp = dev->priv; 4463 nic_t *sp = dev->priv;
3911 StatInfo_t *stat_info = sp->mac_control.stats_info; 4464 StatInfo_t *stat_info = sp->mac_control.stats_info;
3912 4465
3913 tmp_stats[i++] = le32_to_cpu(stat_info->tmac_frms); 4466 s2io_updt_stats(sp);
3914 tmp_stats[i++] = le32_to_cpu(stat_info->tmac_data_octets); 4467 tmp_stats[i++] =
4468 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
4469 le32_to_cpu(stat_info->tmac_frms);
4470 tmp_stats[i++] =
4471 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
4472 le32_to_cpu(stat_info->tmac_data_octets);
3915 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms); 4473 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
3916 tmp_stats[i++] = le32_to_cpu(stat_info->tmac_mcst_frms); 4474 tmp_stats[i++] =
3917 tmp_stats[i++] = le32_to_cpu(stat_info->tmac_bcst_frms); 4475 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
4476 le32_to_cpu(stat_info->tmac_mcst_frms);
4477 tmp_stats[i++] =
4478 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
4479 le32_to_cpu(stat_info->tmac_bcst_frms);
3918 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms); 4480 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
3919 tmp_stats[i++] = le32_to_cpu(stat_info->tmac_any_err_frms); 4481 tmp_stats[i++] =
4482 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
4483 le32_to_cpu(stat_info->tmac_any_err_frms);
3920 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets); 4484 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
3921 tmp_stats[i++] = le32_to_cpu(stat_info->tmac_vld_ip); 4485 tmp_stats[i++] =
3922 tmp_stats[i++] = le32_to_cpu(stat_info->tmac_drop_ip); 4486 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
3923 tmp_stats[i++] = le32_to_cpu(stat_info->tmac_icmp); 4487 le32_to_cpu(stat_info->tmac_vld_ip);
3924 tmp_stats[i++] = le32_to_cpu(stat_info->tmac_rst_tcp); 4488 tmp_stats[i++] =
4489 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
4490 le32_to_cpu(stat_info->tmac_drop_ip);
4491 tmp_stats[i++] =
4492 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
4493 le32_to_cpu(stat_info->tmac_icmp);
4494 tmp_stats[i++] =
4495 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
4496 le32_to_cpu(stat_info->tmac_rst_tcp);
3925 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp); 4497 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
3926 tmp_stats[i++] = le32_to_cpu(stat_info->tmac_udp); 4498 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
3927 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_vld_frms); 4499 le32_to_cpu(stat_info->tmac_udp);
3928 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_data_octets); 4500 tmp_stats[i++] =
4501 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
4502 le32_to_cpu(stat_info->rmac_vld_frms);
4503 tmp_stats[i++] =
4504 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
4505 le32_to_cpu(stat_info->rmac_data_octets);
3929 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms); 4506 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
3930 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms); 4507 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
3931 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_vld_mcst_frms); 4508 tmp_stats[i++] =
3932 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_vld_bcst_frms); 4509 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
4510 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
4511 tmp_stats[i++] =
4512 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
4513 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
3933 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms); 4514 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
3934 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms); 4515 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
3935 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms); 4516 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
3936 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_discarded_frms); 4517 tmp_stats[i++] =
3937 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_usized_frms); 4518 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
3938 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_osized_frms); 4519 le32_to_cpu(stat_info->rmac_discarded_frms);
3939 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_frag_frms); 4520 tmp_stats[i++] =
3940 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_jabber_frms); 4521 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
3941 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ip); 4522 le32_to_cpu(stat_info->rmac_usized_frms);
4523 tmp_stats[i++] =
4524 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
4525 le32_to_cpu(stat_info->rmac_osized_frms);
4526 tmp_stats[i++] =
4527 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
4528 le32_to_cpu(stat_info->rmac_frag_frms);
4529 tmp_stats[i++] =
4530 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
4531 le32_to_cpu(stat_info->rmac_jabber_frms);
4532 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
4533 le32_to_cpu(stat_info->rmac_ip);
3942 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets); 4534 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
3943 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip); 4535 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
3944 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_drop_ip); 4536 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
3945 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_icmp); 4537 le32_to_cpu(stat_info->rmac_drop_ip);
4538 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
4539 le32_to_cpu(stat_info->rmac_icmp);
3946 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp); 4540 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
3947 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_udp); 4541 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
3948 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_drp_udp); 4542 le32_to_cpu(stat_info->rmac_udp);
3949 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pause_cnt); 4543 tmp_stats[i++] =
3950 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_accepted_ip); 4544 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
4545 le32_to_cpu(stat_info->rmac_err_drp_udp);
4546 tmp_stats[i++] =
4547 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
4548 le32_to_cpu(stat_info->rmac_pause_cnt);
4549 tmp_stats[i++] =
4550 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
4551 le32_to_cpu(stat_info->rmac_accepted_ip);
3951 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp); 4552 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
4553 tmp_stats[i++] = 0;
4554 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
4555 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
3952} 4556}
3953 4557
3954static int s2io_ethtool_get_regs_len(struct net_device *dev) 4558int s2io_ethtool_get_regs_len(struct net_device *dev)
3955{ 4559{
3956 return (XENA_REG_SPACE); 4560 return (XENA_REG_SPACE);
3957} 4561}
3958 4562
3959 4563
3960static u32 s2io_ethtool_get_rx_csum(struct net_device * dev) 4564u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
3961{ 4565{
3962 nic_t *sp = dev->priv; 4566 nic_t *sp = dev->priv;
3963 4567
3964 return (sp->rx_csum); 4568 return (sp->rx_csum);
3965} 4569}
3966 4570int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
3967static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
3968{ 4571{
3969 nic_t *sp = dev->priv; 4572 nic_t *sp = dev->priv;
3970 4573
@@ -3975,19 +4578,17 @@ static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
3975 4578
3976 return 0; 4579 return 0;
3977} 4580}
3978 4581int s2io_get_eeprom_len(struct net_device *dev)
3979static int s2io_get_eeprom_len(struct net_device *dev)
3980{ 4582{
3981 return (XENA_EEPROM_SPACE); 4583 return (XENA_EEPROM_SPACE);
3982} 4584}
3983 4585
3984static int s2io_ethtool_self_test_count(struct net_device *dev) 4586int s2io_ethtool_self_test_count(struct net_device *dev)
3985{ 4587{
3986 return (S2IO_TEST_LEN); 4588 return (S2IO_TEST_LEN);
3987} 4589}
3988 4590void s2io_ethtool_get_strings(struct net_device *dev,
3989static void s2io_ethtool_get_strings(struct net_device *dev, 4591 u32 stringset, u8 * data)
3990 u32 stringset, u8 * data)
3991{ 4592{
3992 switch (stringset) { 4593 switch (stringset) {
3993 case ETH_SS_TEST: 4594 case ETH_SS_TEST:
@@ -3998,13 +4599,12 @@ static void s2io_ethtool_get_strings(struct net_device *dev,
3998 sizeof(ethtool_stats_keys)); 4599 sizeof(ethtool_stats_keys));
3999 } 4600 }
4000} 4601}
4001
4002static int s2io_ethtool_get_stats_count(struct net_device *dev) 4602static int s2io_ethtool_get_stats_count(struct net_device *dev)
4003{ 4603{
4004 return (S2IO_STAT_LEN); 4604 return (S2IO_STAT_LEN);
4005} 4605}
4006 4606
4007static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data) 4607int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
4008{ 4608{
4009 if (data) 4609 if (data)
4010 dev->features |= NETIF_F_IP_CSUM; 4610 dev->features |= NETIF_F_IP_CSUM;
@@ -4046,21 +4646,18 @@ static struct ethtool_ops netdev_ethtool_ops = {
4046}; 4646};
4047 4647
4048/** 4648/**
4049 * s2io_ioctl - Entry point for the Ioctl 4649 * s2io_ioctl - Entry point for the Ioctl
4050 * @dev : Device pointer. 4650 * @dev : Device pointer.
4051 * @ifr : An IOCTL specefic structure, that can contain a pointer to 4651 * @ifr : An IOCTL specefic structure, that can contain a pointer to
4052 * a proprietary structure used to pass information to the driver. 4652 * a proprietary structure used to pass information to the driver.
4053 * @cmd : This is used to distinguish between the different commands that 4653 * @cmd : This is used to distinguish between the different commands that
4054 * can be passed to the IOCTL functions. 4654 * can be passed to the IOCTL functions.
4055 * Description: 4655 * Description:
4056 * This function has support for ethtool, adding multiple MAC addresses on 4656 * Currently there are no special functionality supported in IOCTL, hence
4057 * the NIC and some DBG commands for the util tool. 4657 * function always return EOPNOTSUPPORTED
4058 * Return value:
4059 * Currently the IOCTL supports no operations, hence by default this
4060 * function returns OP NOT SUPPORTED value.
4061 */ 4658 */
4062 4659
4063static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 4660int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
4064{ 4661{
4065 return -EOPNOTSUPP; 4662 return -EOPNOTSUPP;
4066} 4663}
@@ -4076,17 +4673,9 @@ static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
4076 * file on failure. 4673 * file on failure.
4077 */ 4674 */
4078 4675
4079static int s2io_change_mtu(struct net_device *dev, int new_mtu) 4676int s2io_change_mtu(struct net_device *dev, int new_mtu)
4080{ 4677{
4081 nic_t *sp = dev->priv; 4678 nic_t *sp = dev->priv;
4082 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4083 register u64 val64;
4084
4085 if (netif_running(dev)) {
4086 DBG_PRINT(ERR_DBG, "%s: Must be stopped to ", dev->name);
4087 DBG_PRINT(ERR_DBG, "change its MTU \n");
4088 return -EBUSY;
4089 }
4090 4679
4091 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) { 4680 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
4092 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", 4681 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
@@ -4094,11 +4683,22 @@ static int s2io_change_mtu(struct net_device *dev, int new_mtu)
4094 return -EPERM; 4683 return -EPERM;
4095 } 4684 }
4096 4685
4097 /* Set the new MTU into the PYLD register of the NIC */
4098 val64 = new_mtu;
4099 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
4100
4101 dev->mtu = new_mtu; 4686 dev->mtu = new_mtu;
4687 if (netif_running(dev)) {
4688 s2io_card_down(sp);
4689 netif_stop_queue(dev);
4690 if (s2io_card_up(sp)) {
4691 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
4692 __FUNCTION__);
4693 }
4694 if (netif_queue_stopped(dev))
4695 netif_wake_queue(dev);
4696 } else { /* Device is down */
4697 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4698 u64 val64 = new_mtu;
4699
4700 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
4701 }
4102 4702
4103 return 0; 4703 return 0;
4104} 4704}
@@ -4108,9 +4708,9 @@ static int s2io_change_mtu(struct net_device *dev, int new_mtu)
4108 * @dev_adr : address of the device structure in dma_addr_t format. 4708 * @dev_adr : address of the device structure in dma_addr_t format.
4109 * Description: 4709 * Description:
4110 * This is the tasklet or the bottom half of the ISR. This is 4710 * This is the tasklet or the bottom half of the ISR. This is
4111 * an extension of the ISR which is scheduled by the scheduler to be run 4711 * an extension of the ISR which is scheduled by the scheduler to be run
4112 * when the load on the CPU is low. All low priority tasks of the ISR can 4712 * when the load on the CPU is low. All low priority tasks of the ISR can
4113 * be pushed into the tasklet. For now the tasklet is used only to 4713 * be pushed into the tasklet. For now the tasklet is used only to
4114 * replenish the Rx buffers in the Rx buffer descriptors. 4714 * replenish the Rx buffers in the Rx buffer descriptors.
4115 * Return value: 4715 * Return value:
4116 * void. 4716 * void.
@@ -4166,19 +4766,22 @@ static void s2io_set_link(unsigned long data)
4166 } 4766 }
4167 4767
4168 subid = nic->pdev->subsystem_device; 4768 subid = nic->pdev->subsystem_device;
4169 /* 4769 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
4170 * Allow a small delay for the NICs self initiated 4770 /*
4171 * cleanup to complete. 4771 * Allow a small delay for the NICs self initiated
4172 */ 4772 * cleanup to complete.
4173 msleep(100); 4773 */
4774 msleep(100);
4775 }
4174 4776
4175 val64 = readq(&bar0->adapter_status); 4777 val64 = readq(&bar0->adapter_status);
4176 if (verify_xena_quiescence(val64, nic->device_enabled_once)) { 4778 if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
4177 if (LINK_IS_UP(val64)) { 4779 if (LINK_IS_UP(val64)) {
4178 val64 = readq(&bar0->adapter_control); 4780 val64 = readq(&bar0->adapter_control);
4179 val64 |= ADAPTER_CNTL_EN; 4781 val64 |= ADAPTER_CNTL_EN;
4180 writeq(val64, &bar0->adapter_control); 4782 writeq(val64, &bar0->adapter_control);
4181 if (CARDS_WITH_FAULTY_LINK_INDICATORS(subid)) { 4783 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
4784 subid)) {
4182 val64 = readq(&bar0->gpio_control); 4785 val64 = readq(&bar0->gpio_control);
4183 val64 |= GPIO_CTRL_GPIO_0; 4786 val64 |= GPIO_CTRL_GPIO_0;
4184 writeq(val64, &bar0->gpio_control); 4787 writeq(val64, &bar0->gpio_control);
@@ -4187,20 +4790,24 @@ static void s2io_set_link(unsigned long data)
4187 val64 |= ADAPTER_LED_ON; 4790 val64 |= ADAPTER_LED_ON;
4188 writeq(val64, &bar0->adapter_control); 4791 writeq(val64, &bar0->adapter_control);
4189 } 4792 }
4190 val64 = readq(&bar0->adapter_status); 4793 if (s2io_link_fault_indication(nic) ==
4191 if (!LINK_IS_UP(val64)) { 4794 MAC_RMAC_ERR_TIMER) {
4192 DBG_PRINT(ERR_DBG, "%s:", dev->name); 4795 val64 = readq(&bar0->adapter_status);
4193 DBG_PRINT(ERR_DBG, " Link down"); 4796 if (!LINK_IS_UP(val64)) {
4194 DBG_PRINT(ERR_DBG, "after "); 4797 DBG_PRINT(ERR_DBG, "%s:", dev->name);
4195 DBG_PRINT(ERR_DBG, "enabling "); 4798 DBG_PRINT(ERR_DBG, " Link down");
4196 DBG_PRINT(ERR_DBG, "device \n"); 4799 DBG_PRINT(ERR_DBG, "after ");
4800 DBG_PRINT(ERR_DBG, "enabling ");
4801 DBG_PRINT(ERR_DBG, "device \n");
4802 }
4197 } 4803 }
4198 if (nic->device_enabled_once == FALSE) { 4804 if (nic->device_enabled_once == FALSE) {
4199 nic->device_enabled_once = TRUE; 4805 nic->device_enabled_once = TRUE;
4200 } 4806 }
4201 s2io_link(nic, LINK_UP); 4807 s2io_link(nic, LINK_UP);
4202 } else { 4808 } else {
4203 if (CARDS_WITH_FAULTY_LINK_INDICATORS(subid)) { 4809 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
4810 subid)) {
4204 val64 = readq(&bar0->gpio_control); 4811 val64 = readq(&bar0->gpio_control);
4205 val64 &= ~GPIO_CTRL_GPIO_0; 4812 val64 &= ~GPIO_CTRL_GPIO_0;
4206 writeq(val64, &bar0->gpio_control); 4813 writeq(val64, &bar0->gpio_control);
@@ -4223,9 +4830,11 @@ static void s2io_card_down(nic_t * sp)
4223 unsigned long flags; 4830 unsigned long flags;
4224 register u64 val64 = 0; 4831 register u64 val64 = 0;
4225 4832
4833 del_timer_sync(&sp->alarm_timer);
4226 /* If s2io_set_link task is executing, wait till it completes. */ 4834 /* If s2io_set_link task is executing, wait till it completes. */
4227 while (test_and_set_bit(0, &(sp->link_state))) 4835 while (test_and_set_bit(0, &(sp->link_state))) {
4228 msleep(50); 4836 msleep(50);
4837 }
4229 atomic_set(&sp->card_state, CARD_DOWN); 4838 atomic_set(&sp->card_state, CARD_DOWN);
4230 4839
4231 /* disable Tx and Rx traffic on the NIC */ 4840 /* disable Tx and Rx traffic on the NIC */
@@ -4237,7 +4846,7 @@ static void s2io_card_down(nic_t * sp)
4237 /* Check if the device is Quiescent and then Reset the NIC */ 4846 /* Check if the device is Quiescent and then Reset the NIC */
4238 do { 4847 do {
4239 val64 = readq(&bar0->adapter_status); 4848 val64 = readq(&bar0->adapter_status);
4240 if (verify_xena_quiescence(val64, sp->device_enabled_once)) { 4849 if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) {
4241 break; 4850 break;
4242 } 4851 }
4243 4852
@@ -4251,14 +4860,27 @@ static void s2io_card_down(nic_t * sp)
4251 break; 4860 break;
4252 } 4861 }
4253 } while (1); 4862 } while (1);
4254 spin_lock_irqsave(&sp->tx_lock, flags);
4255 s2io_reset(sp); 4863 s2io_reset(sp);
4256 4864
4257 /* Free all unused Tx and Rx buffers */ 4865 /* Waiting till all Interrupt handlers are complete */
4866 cnt = 0;
4867 do {
4868 msleep(10);
4869 if (!atomic_read(&sp->isr_cnt))
4870 break;
4871 cnt++;
4872 } while(cnt < 5);
4873
4874 spin_lock_irqsave(&sp->tx_lock, flags);
4875 /* Free all Tx buffers */
4258 free_tx_buffers(sp); 4876 free_tx_buffers(sp);
4877 spin_unlock_irqrestore(&sp->tx_lock, flags);
4878
4879 /* Free all Rx buffers */
4880 spin_lock_irqsave(&sp->rx_lock, flags);
4259 free_rx_buffers(sp); 4881 free_rx_buffers(sp);
4882 spin_unlock_irqrestore(&sp->rx_lock, flags);
4260 4883
4261 spin_unlock_irqrestore(&sp->tx_lock, flags);
4262 clear_bit(0, &(sp->link_state)); 4884 clear_bit(0, &(sp->link_state));
4263} 4885}
4264 4886
@@ -4276,8 +4898,8 @@ static int s2io_card_up(nic_t * sp)
4276 return -ENODEV; 4898 return -ENODEV;
4277 } 4899 }
4278 4900
4279 /* 4901 /*
4280 * Initializing the Rx buffers. For now we are considering only 1 4902 * Initializing the Rx buffers. For now we are considering only 1
4281 * Rx ring and initializing buffers into 30 Rx blocks 4903 * Rx ring and initializing buffers into 30 Rx blocks
4282 */ 4904 */
4283 mac_control = &sp->mac_control; 4905 mac_control = &sp->mac_control;
@@ -4311,16 +4933,18 @@ static int s2io_card_up(nic_t * sp)
4311 return -ENODEV; 4933 return -ENODEV;
4312 } 4934 }
4313 4935
4936 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
4937
4314 atomic_set(&sp->card_state, CARD_UP); 4938 atomic_set(&sp->card_state, CARD_UP);
4315 return 0; 4939 return 0;
4316} 4940}
4317 4941
4318/** 4942/**
4319 * s2io_restart_nic - Resets the NIC. 4943 * s2io_restart_nic - Resets the NIC.
4320 * @data : long pointer to the device private structure 4944 * @data : long pointer to the device private structure
4321 * Description: 4945 * Description:
4322 * This function is scheduled to be run by the s2io_tx_watchdog 4946 * This function is scheduled to be run by the s2io_tx_watchdog
4323 * function after 0.5 secs to reset the NIC. The idea is to reduce 4947 * function after 0.5 secs to reset the NIC. The idea is to reduce
4324 * the run time of the watch dog routine which is run holding a 4948 * the run time of the watch dog routine which is run holding a
4325 * spin lock. 4949 * spin lock.
4326 */ 4950 */
@@ -4338,10 +4962,11 @@ static void s2io_restart_nic(unsigned long data)
4338 netif_wake_queue(dev); 4962 netif_wake_queue(dev);
4339 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", 4963 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
4340 dev->name); 4964 dev->name);
4965
4341} 4966}
4342 4967
4343/** 4968/**
4344 * s2io_tx_watchdog - Watchdog for transmit side. 4969 * s2io_tx_watchdog - Watchdog for transmit side.
4345 * @dev : Pointer to net device structure 4970 * @dev : Pointer to net device structure
4346 * Description: 4971 * Description:
4347 * This function is triggered if the Tx Queue is stopped 4972 * This function is triggered if the Tx Queue is stopped
@@ -4369,7 +4994,7 @@ static void s2io_tx_watchdog(struct net_device *dev)
4369 * @len : length of the packet 4994 * @len : length of the packet
4370 * @cksum : FCS checksum of the frame. 4995 * @cksum : FCS checksum of the frame.
4371 * @ring_no : the ring from which this RxD was extracted. 4996 * @ring_no : the ring from which this RxD was extracted.
4372 * Description: 4997 * Description:
4373 * This function is called by the Tx interrupt serivce routine to perform 4998 * This function is called by the Tx interrupt serivce routine to perform
4374 * some OS related operations on the SKB before passing it to the upper 4999 * some OS related operations on the SKB before passing it to the upper
4375 * layers. It mainly checks if the checksum is OK, if so adds it to the 5000 * layers. It mainly checks if the checksum is OK, if so adds it to the
@@ -4379,35 +5004,68 @@ static void s2io_tx_watchdog(struct net_device *dev)
4379 * Return value: 5004 * Return value:
4380 * SUCCESS on success and -1 on failure. 5005 * SUCCESS on success and -1 on failure.
4381 */ 5006 */
4382#ifndef CONFIG_2BUFF_MODE 5007static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
4383static int rx_osm_handler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no)
4384#else
4385static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no,
4386 buffAdd_t * ba)
4387#endif
4388{ 5008{
5009 nic_t *sp = ring_data->nic;
4389 struct net_device *dev = (struct net_device *) sp->dev; 5010 struct net_device *dev = (struct net_device *) sp->dev;
4390 struct sk_buff *skb = 5011 struct sk_buff *skb = (struct sk_buff *)
4391 (struct sk_buff *) ((unsigned long) rxdp->Host_Control); 5012 ((unsigned long) rxdp->Host_Control);
5013 int ring_no = ring_data->ring_no;
4392 u16 l3_csum, l4_csum; 5014 u16 l3_csum, l4_csum;
4393#ifdef CONFIG_2BUFF_MODE 5015#ifdef CONFIG_2BUFF_MODE
4394 int buf0_len, buf2_len; 5016 int buf0_len = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
5017 int buf2_len = RXD_GET_BUFFER2_SIZE(rxdp->Control_2);
5018 int get_block = ring_data->rx_curr_get_info.block_index;
5019 int get_off = ring_data->rx_curr_get_info.offset;
5020 buffAdd_t *ba = &ring_data->ba[get_block][get_off];
4395 unsigned char *buff; 5021 unsigned char *buff;
5022#else
5023 u16 len = (u16) ((RXD_GET_BUFFER0_SIZE(rxdp->Control_2)) >> 48);;
4396#endif 5024#endif
5025 skb->dev = dev;
5026 if (rxdp->Control_1 & RXD_T_CODE) {
5027 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
5028 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
5029 dev->name, err);
5030 dev_kfree_skb(skb);
5031 sp->stats.rx_crc_errors++;
5032 atomic_dec(&sp->rx_bufs_left[ring_no]);
5033 rxdp->Host_Control = 0;
5034 return 0;
5035 }
4397 5036
4398 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1); 5037 /* Updating statistics */
4399 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && (sp->rx_csum)) { 5038 rxdp->Host_Control = 0;
5039 sp->rx_pkt_count++;
5040 sp->stats.rx_packets++;
5041#ifndef CONFIG_2BUFF_MODE
5042 sp->stats.rx_bytes += len;
5043#else
5044 sp->stats.rx_bytes += buf0_len + buf2_len;
5045#endif
5046
5047#ifndef CONFIG_2BUFF_MODE
5048 skb_put(skb, len);
5049#else
5050 buff = skb_push(skb, buf0_len);
5051 memcpy(buff, ba->ba_0, buf0_len);
5052 skb_put(skb, buf2_len);
5053#endif
5054
5055 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
5056 (sp->rx_csum)) {
5057 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
4400 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1); 5058 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
4401 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) { 5059 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
4402 /* 5060 /*
4403 * NIC verifies if the Checksum of the received 5061 * NIC verifies if the Checksum of the received
4404 * frame is Ok or not and accordingly returns 5062 * frame is Ok or not and accordingly returns
4405 * a flag in the RxD. 5063 * a flag in the RxD.
4406 */ 5064 */
4407 skb->ip_summed = CHECKSUM_UNNECESSARY; 5065 skb->ip_summed = CHECKSUM_UNNECESSARY;
4408 } else { 5066 } else {
4409 /* 5067 /*
4410 * Packet with erroneous checksum, let the 5068 * Packet with erroneous checksum, let the
4411 * upper layers deal with it. 5069 * upper layers deal with it.
4412 */ 5070 */
4413 skb->ip_summed = CHECKSUM_NONE; 5071 skb->ip_summed = CHECKSUM_NONE;
@@ -4416,44 +5074,26 @@ static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no,
4416 skb->ip_summed = CHECKSUM_NONE; 5074 skb->ip_summed = CHECKSUM_NONE;
4417 } 5075 }
4418 5076
4419 if (rxdp->Control_1 & RXD_T_CODE) {
4420 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
4421 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
4422 dev->name, err);
4423 }
4424#ifdef CONFIG_2BUFF_MODE
4425 buf0_len = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
4426 buf2_len = RXD_GET_BUFFER2_SIZE(rxdp->Control_2);
4427#endif
4428
4429 skb->dev = dev;
4430#ifndef CONFIG_2BUFF_MODE
4431 skb_put(skb, len);
4432 skb->protocol = eth_type_trans(skb, dev);
4433#else
4434 buff = skb_push(skb, buf0_len);
4435 memcpy(buff, ba->ba_0, buf0_len);
4436 skb_put(skb, buf2_len);
4437 skb->protocol = eth_type_trans(skb, dev); 5077 skb->protocol = eth_type_trans(skb, dev);
4438#endif
4439
4440#ifdef CONFIG_S2IO_NAPI 5078#ifdef CONFIG_S2IO_NAPI
4441 netif_receive_skb(skb); 5079 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
5080 /* Queueing the vlan frame to the upper layer */
5081 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
5082 RXD_GET_VLAN_TAG(rxdp->Control_2));
5083 } else {
5084 netif_receive_skb(skb);
5085 }
4442#else 5086#else
4443 netif_rx(skb); 5087 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
5088 /* Queueing the vlan frame to the upper layer */
5089 vlan_hwaccel_rx(skb, sp->vlgrp,
5090 RXD_GET_VLAN_TAG(rxdp->Control_2));
5091 } else {
5092 netif_rx(skb);
5093 }
4444#endif 5094#endif
4445
4446 dev->last_rx = jiffies; 5095 dev->last_rx = jiffies;
4447 sp->rx_pkt_count++;
4448 sp->stats.rx_packets++;
4449#ifndef CONFIG_2BUFF_MODE
4450 sp->stats.rx_bytes += len;
4451#else
4452 sp->stats.rx_bytes += buf0_len + buf2_len;
4453#endif
4454
4455 atomic_dec(&sp->rx_bufs_left[ring_no]); 5096 atomic_dec(&sp->rx_bufs_left[ring_no]);
4456 rxdp->Host_Control = 0;
4457 return SUCCESS; 5097 return SUCCESS;
4458} 5098}
4459 5099
@@ -4464,13 +5104,13 @@ static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no,
4464 * @link : inidicates whether link is UP/DOWN. 5104 * @link : inidicates whether link is UP/DOWN.
4465 * Description: 5105 * Description:
4466 * This function stops/starts the Tx queue depending on whether the link 5106 * This function stops/starts the Tx queue depending on whether the link
4467 * status of the NIC is is down or up. This is called by the Alarm 5107 * status of the NIC is is down or up. This is called by the Alarm
4468 * interrupt handler whenever a link change interrupt comes up. 5108 * interrupt handler whenever a link change interrupt comes up.
4469 * Return value: 5109 * Return value:
4470 * void. 5110 * void.
4471 */ 5111 */
4472 5112
4473static void s2io_link(nic_t * sp, int link) 5113void s2io_link(nic_t * sp, int link)
4474{ 5114{
4475 struct net_device *dev = (struct net_device *) sp->dev; 5115 struct net_device *dev = (struct net_device *) sp->dev;
4476 5116
@@ -4487,8 +5127,25 @@ static void s2io_link(nic_t * sp, int link)
4487} 5127}
4488 5128
4489/** 5129/**
4490 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers . 5130 * get_xena_rev_id - to identify revision ID of xena.
4491 * @sp : private member of the device structure, which is a pointer to the 5131 * @pdev : PCI Dev structure
5132 * Description:
5133 * Function to identify the Revision ID of xena.
5134 * Return value:
5135 * returns the revision ID of the device.
5136 */
5137
5138int get_xena_rev_id(struct pci_dev *pdev)
5139{
5140 u8 id = 0;
5141 int ret;
5142 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
5143 return id;
5144}
5145
5146/**
5147 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
5148 * @sp : private member of the device structure, which is a pointer to the
4492 * s2io_nic structure. 5149 * s2io_nic structure.
4493 * Description: 5150 * Description:
4494 * This function initializes a few of the PCI and PCI-X configuration registers 5151 * This function initializes a few of the PCI and PCI-X configuration registers
@@ -4499,15 +5156,15 @@ static void s2io_link(nic_t * sp, int link)
4499 5156
4500static void s2io_init_pci(nic_t * sp) 5157static void s2io_init_pci(nic_t * sp)
4501{ 5158{
4502 u16 pci_cmd = 0; 5159 u16 pci_cmd = 0, pcix_cmd = 0;
4503 5160
4504 /* Enable Data Parity Error Recovery in PCI-X command register. */ 5161 /* Enable Data Parity Error Recovery in PCI-X command register. */
4505 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, 5162 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4506 &(sp->pcix_cmd)); 5163 &(pcix_cmd));
4507 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, 5164 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4508 (sp->pcix_cmd | 1)); 5165 (pcix_cmd | 1));
4509 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, 5166 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4510 &(sp->pcix_cmd)); 5167 &(pcix_cmd));
4511 5168
4512 /* Set the PErr Response bit in PCI command register. */ 5169 /* Set the PErr Response bit in PCI command register. */
4513 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd); 5170 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
@@ -4515,53 +5172,43 @@ static void s2io_init_pci(nic_t * sp)
4515 (pci_cmd | PCI_COMMAND_PARITY)); 5172 (pci_cmd | PCI_COMMAND_PARITY));
4516 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd); 5173 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
4517 5174
4518 /* Set MMRB count to 1024 in PCI-X Command register. */
4519 sp->pcix_cmd &= 0xFFF3;
4520 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, (sp->pcix_cmd | (0x1 << 2))); /* MMRBC 1K */
4521 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4522 &(sp->pcix_cmd));
4523
4524 /* Setting Maximum outstanding splits based on system type. */
4525 sp->pcix_cmd &= 0xFF8F;
4526
4527 sp->pcix_cmd |= XENA_MAX_OUTSTANDING_SPLITS(0x1); /* 2 splits. */
4528 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4529 sp->pcix_cmd);
4530 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4531 &(sp->pcix_cmd));
4532 /* Forcibly disabling relaxed ordering capability of the card. */ 5175 /* Forcibly disabling relaxed ordering capability of the card. */
4533 sp->pcix_cmd &= 0xfffd; 5176 pcix_cmd &= 0xfffd;
4534 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, 5177 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4535 sp->pcix_cmd); 5178 pcix_cmd);
4536 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, 5179 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4537 &(sp->pcix_cmd)); 5180 &(pcix_cmd));
4538} 5181}
4539 5182
4540MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>"); 5183MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
4541MODULE_LICENSE("GPL"); 5184MODULE_LICENSE("GPL");
4542module_param(tx_fifo_num, int, 0); 5185module_param(tx_fifo_num, int, 0);
4543module_param_array(tx_fifo_len, int, NULL, 0);
4544module_param(rx_ring_num, int, 0); 5186module_param(rx_ring_num, int, 0);
4545module_param_array(rx_ring_sz, int, NULL, 0); 5187module_param_array(tx_fifo_len, uint, NULL, 0);
4546module_param(Stats_refresh_time, int, 0); 5188module_param_array(rx_ring_sz, uint, NULL, 0);
5189module_param_array(rts_frm_len, uint, NULL, 0);
5190module_param(use_continuous_tx_intrs, int, 1);
4547module_param(rmac_pause_time, int, 0); 5191module_param(rmac_pause_time, int, 0);
4548module_param(mc_pause_threshold_q0q3, int, 0); 5192module_param(mc_pause_threshold_q0q3, int, 0);
4549module_param(mc_pause_threshold_q4q7, int, 0); 5193module_param(mc_pause_threshold_q4q7, int, 0);
4550module_param(shared_splits, int, 0); 5194module_param(shared_splits, int, 0);
4551module_param(tmac_util_period, int, 0); 5195module_param(tmac_util_period, int, 0);
4552module_param(rmac_util_period, int, 0); 5196module_param(rmac_util_period, int, 0);
5197module_param(bimodal, bool, 0);
4553#ifndef CONFIG_S2IO_NAPI 5198#ifndef CONFIG_S2IO_NAPI
4554module_param(indicate_max_pkts, int, 0); 5199module_param(indicate_max_pkts, int, 0);
4555#endif 5200#endif
5201module_param(rxsync_frequency, int, 0);
5202
4556/** 5203/**
4557 * s2io_init_nic - Initialization of the adapter . 5204 * s2io_init_nic - Initialization of the adapter .
4558 * @pdev : structure containing the PCI related information of the device. 5205 * @pdev : structure containing the PCI related information of the device.
4559 * @pre: List of PCI devices supported by the driver listed in s2io_tbl. 5206 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
4560 * Description: 5207 * Description:
4561 * The function initializes an adapter identified by the pci_dec structure. 5208 * The function initializes an adapter identified by the pci_dec structure.
4562 * All OS related initialization including memory and device structure and 5209 * All OS related initialization including memory and device structure and
4563 * initlaization of the device private variable is done. Also the swapper 5210 * initlaization of the device private variable is done. Also the swapper
4564 * control register is initialized to enable read and write into the I/O 5211 * control register is initialized to enable read and write into the I/O
4565 * registers of the device. 5212 * registers of the device.
4566 * Return value: 5213 * Return value:
4567 * returns 0 on success and negative on failure. 5214 * returns 0 on success and negative on failure.
@@ -4572,7 +5219,6 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4572{ 5219{
4573 nic_t *sp; 5220 nic_t *sp;
4574 struct net_device *dev; 5221 struct net_device *dev;
4575 char *dev_name = "S2IO 10GE NIC";
4576 int i, j, ret; 5222 int i, j, ret;
4577 int dma_flag = FALSE; 5223 int dma_flag = FALSE;
4578 u32 mac_up, mac_down; 5224 u32 mac_up, mac_down;
@@ -4581,10 +5227,11 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4581 u16 subid; 5227 u16 subid;
4582 mac_info_t *mac_control; 5228 mac_info_t *mac_control;
4583 struct config_param *config; 5229 struct config_param *config;
5230 int mode;
4584 5231
4585 5232#ifdef CONFIG_S2IO_NAPI
4586 DBG_PRINT(ERR_DBG, "Loading S2IO driver with %s\n", 5233 DBG_PRINT(ERR_DBG, "NAPI support has been enabled\n");
4587 s2io_driver_version); 5234#endif
4588 5235
4589 if ((ret = pci_enable_device(pdev))) { 5236 if ((ret = pci_enable_device(pdev))) {
4590 DBG_PRINT(ERR_DBG, 5237 DBG_PRINT(ERR_DBG,
@@ -4595,7 +5242,6 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4595 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 5242 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
4596 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n"); 5243 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
4597 dma_flag = TRUE; 5244 dma_flag = TRUE;
4598
4599 if (pci_set_consistent_dma_mask 5245 if (pci_set_consistent_dma_mask
4600 (pdev, DMA_64BIT_MASK)) { 5246 (pdev, DMA_64BIT_MASK)) {
4601 DBG_PRINT(ERR_DBG, 5247 DBG_PRINT(ERR_DBG,
@@ -4635,34 +5281,41 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4635 memset(sp, 0, sizeof(nic_t)); 5281 memset(sp, 0, sizeof(nic_t));
4636 sp->dev = dev; 5282 sp->dev = dev;
4637 sp->pdev = pdev; 5283 sp->pdev = pdev;
4638 sp->vendor_id = pdev->vendor;
4639 sp->device_id = pdev->device;
4640 sp->high_dma_flag = dma_flag; 5284 sp->high_dma_flag = dma_flag;
4641 sp->irq = pdev->irq;
4642 sp->device_enabled_once = FALSE; 5285 sp->device_enabled_once = FALSE;
4643 strcpy(sp->name, dev_name); 5286
5287 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
5288 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
5289 sp->device_type = XFRAME_II_DEVICE;
5290 else
5291 sp->device_type = XFRAME_I_DEVICE;
4644 5292
4645 /* Initialize some PCI/PCI-X fields of the NIC. */ 5293 /* Initialize some PCI/PCI-X fields of the NIC. */
4646 s2io_init_pci(sp); 5294 s2io_init_pci(sp);
4647 5295
4648 /* 5296 /*
4649 * Setting the device configuration parameters. 5297 * Setting the device configuration parameters.
4650 * Most of these parameters can be specified by the user during 5298 * Most of these parameters can be specified by the user during
4651 * module insertion as they are module loadable parameters. If 5299 * module insertion as they are module loadable parameters. If
4652 * these parameters are not not specified during load time, they 5300 * these parameters are not not specified during load time, they
4653 * are initialized with default values. 5301 * are initialized with default values.
4654 */ 5302 */
4655 mac_control = &sp->mac_control; 5303 mac_control = &sp->mac_control;
4656 config = &sp->config; 5304 config = &sp->config;
4657 5305
4658 /* Tx side parameters. */ 5306 /* Tx side parameters. */
4659 tx_fifo_len[0] = DEFAULT_FIFO_LEN; /* Default value. */ 5307 if (tx_fifo_len[0] == 0)
5308 tx_fifo_len[0] = DEFAULT_FIFO_LEN; /* Default value. */
4660 config->tx_fifo_num = tx_fifo_num; 5309 config->tx_fifo_num = tx_fifo_num;
4661 for (i = 0; i < MAX_TX_FIFOS; i++) { 5310 for (i = 0; i < MAX_TX_FIFOS; i++) {
4662 config->tx_cfg[i].fifo_len = tx_fifo_len[i]; 5311 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
4663 config->tx_cfg[i].fifo_priority = i; 5312 config->tx_cfg[i].fifo_priority = i;
4664 } 5313 }
4665 5314
5315 /* mapping the QoS priority to the configured fifos */
5316 for (i = 0; i < MAX_TX_FIFOS; i++)
5317 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
5318
4666 config->tx_intr_type = TXD_INT_TYPE_UTILZ; 5319 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
4667 for (i = 0; i < config->tx_fifo_num; i++) { 5320 for (i = 0; i < config->tx_fifo_num; i++) {
4668 config->tx_cfg[i].f_no_snoop = 5321 config->tx_cfg[i].f_no_snoop =
@@ -4675,7 +5328,8 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4675 config->max_txds = MAX_SKB_FRAGS; 5328 config->max_txds = MAX_SKB_FRAGS;
4676 5329
4677 /* Rx side parameters. */ 5330 /* Rx side parameters. */
4678 rx_ring_sz[0] = SMALL_BLK_CNT; /* Default value. */ 5331 if (rx_ring_sz[0] == 0)
5332 rx_ring_sz[0] = SMALL_BLK_CNT; /* Default value. */
4679 config->rx_ring_num = rx_ring_num; 5333 config->rx_ring_num = rx_ring_num;
4680 for (i = 0; i < MAX_RX_RINGS; i++) { 5334 for (i = 0; i < MAX_RX_RINGS; i++) {
4681 config->rx_cfg[i].num_rxd = rx_ring_sz[i] * 5335 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
@@ -4699,10 +5353,13 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4699 for (i = 0; i < config->rx_ring_num; i++) 5353 for (i = 0; i < config->rx_ring_num; i++)
4700 atomic_set(&sp->rx_bufs_left[i], 0); 5354 atomic_set(&sp->rx_bufs_left[i], 0);
4701 5355
5356 /* Initialize the number of ISRs currently running */
5357 atomic_set(&sp->isr_cnt, 0);
5358
4702 /* initialize the shared memory used by the NIC and the host */ 5359 /* initialize the shared memory used by the NIC and the host */
4703 if (init_shared_mem(sp)) { 5360 if (init_shared_mem(sp)) {
4704 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", 5361 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
4705 dev->name); 5362 __FUNCTION__);
4706 ret = -ENOMEM; 5363 ret = -ENOMEM;
4707 goto mem_alloc_failed; 5364 goto mem_alloc_failed;
4708 } 5365 }
@@ -4743,13 +5400,17 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4743 dev->do_ioctl = &s2io_ioctl; 5400 dev->do_ioctl = &s2io_ioctl;
4744 dev->change_mtu = &s2io_change_mtu; 5401 dev->change_mtu = &s2io_change_mtu;
4745 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops); 5402 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
5403 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5404 dev->vlan_rx_register = s2io_vlan_rx_register;
5405 dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
5406
4746 /* 5407 /*
4747 * will use eth_mac_addr() for dev->set_mac_address 5408 * will use eth_mac_addr() for dev->set_mac_address
4748 * mac address will be set every time dev->open() is called 5409 * mac address will be set every time dev->open() is called
4749 */ 5410 */
4750#ifdef CONFIG_S2IO_NAPI 5411#if defined(CONFIG_S2IO_NAPI)
4751 dev->poll = s2io_poll; 5412 dev->poll = s2io_poll;
4752 dev->weight = 90; 5413 dev->weight = 32;
4753#endif 5414#endif
4754 5415
4755 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; 5416 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
@@ -4776,22 +5437,28 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4776 goto set_swap_failed; 5437 goto set_swap_failed;
4777 } 5438 }
4778 5439
4779 /* Fix for all "FFs" MAC address problems observed on Alpha platforms */ 5440 /* Verify if the Herc works on the slot its placed into */
4780 fix_mac_address(sp); 5441 if (sp->device_type & XFRAME_II_DEVICE) {
4781 s2io_reset(sp); 5442 mode = s2io_verify_pci_mode(sp);
5443 if (mode < 0) {
5444 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
5445 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
5446 ret = -EBADSLT;
5447 goto set_swap_failed;
5448 }
5449 }
4782 5450
4783 /* 5451 /* Not needed for Herc */
4784 * Setting swapper control on the NIC, so the MAC address can be read. 5452 if (sp->device_type & XFRAME_I_DEVICE) {
4785 */ 5453 /*
4786 if (s2io_set_swapper(sp)) { 5454 * Fix for all "FFs" MAC address problems observed on
4787 DBG_PRINT(ERR_DBG, 5455 * Alpha platforms
4788 "%s: S2IO: swapper settings are wrong\n", 5456 */
4789 dev->name); 5457 fix_mac_address(sp);
4790 ret = -EAGAIN; 5458 s2io_reset(sp);
4791 goto set_swap_failed;
4792 } 5459 }
4793 5460
4794 /* 5461 /*
4795 * MAC address initialization. 5462 * MAC address initialization.
4796 * For now only one mac address will be read and used. 5463 * For now only one mac address will be read and used.
4797 */ 5464 */
@@ -4814,37 +5481,28 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4814 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16); 5481 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
4815 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24); 5482 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
4816 5483
4817 DBG_PRINT(INIT_DBG,
4818 "DEFAULT MAC ADDR:0x%02x-%02x-%02x-%02x-%02x-%02x\n",
4819 sp->def_mac_addr[0].mac_addr[0],
4820 sp->def_mac_addr[0].mac_addr[1],
4821 sp->def_mac_addr[0].mac_addr[2],
4822 sp->def_mac_addr[0].mac_addr[3],
4823 sp->def_mac_addr[0].mac_addr[4],
4824 sp->def_mac_addr[0].mac_addr[5]);
4825
4826 /* Set the factory defined MAC address initially */ 5484 /* Set the factory defined MAC address initially */
4827 dev->addr_len = ETH_ALEN; 5485 dev->addr_len = ETH_ALEN;
4828 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN); 5486 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
4829 5487
4830 /* 5488 /*
4831 * Initialize the tasklet status and link state flags 5489 * Initialize the tasklet status and link state flags
4832 * and the card statte parameter 5490 * and the card state parameter
4833 */ 5491 */
4834 atomic_set(&(sp->card_state), 0); 5492 atomic_set(&(sp->card_state), 0);
4835 sp->tasklet_status = 0; 5493 sp->tasklet_status = 0;
4836 sp->link_state = 0; 5494 sp->link_state = 0;
4837 5495
4838
4839 /* Initialize spinlocks */ 5496 /* Initialize spinlocks */
4840 spin_lock_init(&sp->tx_lock); 5497 spin_lock_init(&sp->tx_lock);
4841#ifndef CONFIG_S2IO_NAPI 5498#ifndef CONFIG_S2IO_NAPI
4842 spin_lock_init(&sp->put_lock); 5499 spin_lock_init(&sp->put_lock);
4843#endif 5500#endif
5501 spin_lock_init(&sp->rx_lock);
4844 5502
4845 /* 5503 /*
4846 * SXE-002: Configure link and activity LED to init state 5504 * SXE-002: Configure link and activity LED to init state
4847 * on driver load. 5505 * on driver load.
4848 */ 5506 */
4849 subid = sp->pdev->subsystem_device; 5507 subid = sp->pdev->subsystem_device;
4850 if ((subid & 0xFF) >= 0x07) { 5508 if ((subid & 0xFF) >= 0x07) {
@@ -4864,13 +5522,61 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4864 goto register_failed; 5522 goto register_failed;
4865 } 5523 }
4866 5524
4867 /* 5525 if (sp->device_type & XFRAME_II_DEVICE) {
4868 * Make Link state as off at this point, when the Link change 5526 DBG_PRINT(ERR_DBG, "%s: Neterion Xframe II 10GbE adapter ",
4869 * interrupt comes the state will be automatically changed to 5527 dev->name);
5528 DBG_PRINT(ERR_DBG, "(rev %d), Driver %s\n",
5529 get_xena_rev_id(sp->pdev),
5530 s2io_driver_version);
5531 DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
5532 sp->def_mac_addr[0].mac_addr[0],
5533 sp->def_mac_addr[0].mac_addr[1],
5534 sp->def_mac_addr[0].mac_addr[2],
5535 sp->def_mac_addr[0].mac_addr[3],
5536 sp->def_mac_addr[0].mac_addr[4],
5537 sp->def_mac_addr[0].mac_addr[5]);
5538 mode = s2io_print_pci_mode(sp);
5539 if (mode < 0) {
5540 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode ");
5541 ret = -EBADSLT;
5542 goto set_swap_failed;
5543 }
5544 } else {
5545 DBG_PRINT(ERR_DBG, "%s: Neterion Xframe I 10GbE adapter ",
5546 dev->name);
5547 DBG_PRINT(ERR_DBG, "(rev %d), Driver %s\n",
5548 get_xena_rev_id(sp->pdev),
5549 s2io_driver_version);
5550 DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
5551 sp->def_mac_addr[0].mac_addr[0],
5552 sp->def_mac_addr[0].mac_addr[1],
5553 sp->def_mac_addr[0].mac_addr[2],
5554 sp->def_mac_addr[0].mac_addr[3],
5555 sp->def_mac_addr[0].mac_addr[4],
5556 sp->def_mac_addr[0].mac_addr[5]);
5557 }
5558
5559 /* Initialize device name */
5560 strcpy(sp->name, dev->name);
5561 if (sp->device_type & XFRAME_II_DEVICE)
5562 strcat(sp->name, ": Neterion Xframe II 10GbE adapter");
5563 else
5564 strcat(sp->name, ": Neterion Xframe I 10GbE adapter");
5565
5566 /* Initialize bimodal Interrupts */
5567 sp->config.bimodal = bimodal;
5568 if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
5569 sp->config.bimodal = 0;
5570 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
5571 dev->name);
5572 }
5573
5574 /*
5575 * Make Link state as off at this point, when the Link change
5576 * interrupt comes the state will be automatically changed to
4870 * the right state. 5577 * the right state.
4871 */ 5578 */
4872 netif_carrier_off(dev); 5579 netif_carrier_off(dev);
4873 sp->last_link_state = LINK_DOWN;
4874 5580
4875 return 0; 5581 return 0;
4876 5582
@@ -4891,11 +5597,11 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4891} 5597}
4892 5598
4893/** 5599/**
4894 * s2io_rem_nic - Free the PCI device 5600 * s2io_rem_nic - Free the PCI device
4895 * @pdev: structure containing the PCI related information of the device. 5601 * @pdev: structure containing the PCI related information of the device.
4896 * Description: This function is called by the Pci subsystem to release a 5602 * Description: This function is called by the Pci subsystem to release a
4897 * PCI device and free up all resource held up by the device. This could 5603 * PCI device and free up all resource held up by the device. This could
4898 * be in response to a Hot plug event or when the driver is to be removed 5604 * be in response to a Hot plug event or when the driver is to be removed
4899 * from memory. 5605 * from memory.
4900 */ 5606 */
4901 5607
@@ -4919,7 +5625,6 @@ static void __devexit s2io_rem_nic(struct pci_dev *pdev)
4919 pci_disable_device(pdev); 5625 pci_disable_device(pdev);
4920 pci_release_regions(pdev); 5626 pci_release_regions(pdev);
4921 pci_set_drvdata(pdev, NULL); 5627 pci_set_drvdata(pdev, NULL);
4922
4923 free_netdev(dev); 5628 free_netdev(dev);
4924} 5629}
4925 5630
@@ -4935,11 +5640,11 @@ int __init s2io_starter(void)
4935} 5640}
4936 5641
4937/** 5642/**
4938 * s2io_closer - Cleanup routine for the driver 5643 * s2io_closer - Cleanup routine for the driver
4939 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver. 5644 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
4940 */ 5645 */
4941 5646
4942static void s2io_closer(void) 5647void s2io_closer(void)
4943{ 5648{
4944 pci_unregister_driver(&s2io_driver); 5649 pci_unregister_driver(&s2io_driver);
4945 DBG_PRINT(INIT_DBG, "cleanup done\n"); 5650 DBG_PRINT(INIT_DBG, "cleanup done\n");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 17:51:55 -0500