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path: root/drivers/net/s2io.c
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Diffstat (limited to 'drivers/net/s2io.c')
-rw-r--r--drivers/net/s2io.c1178
1 files changed, 572 insertions, 606 deletions
diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c
index 1dd66b8ea0fa..639fbc0f16f3 100644
--- a/drivers/net/s2io.c
+++ b/drivers/net/s2io.c
@@ -77,7 +77,7 @@
77#include "s2io.h" 77#include "s2io.h"
78#include "s2io-regs.h" 78#include "s2io-regs.h"
79 79
80#define DRV_VERSION "2.0.15.2" 80#define DRV_VERSION "2.0.16.1"
81 81
82/* S2io Driver name & version. */ 82/* S2io Driver name & version. */
83static char s2io_driver_name[] = "Neterion"; 83static char s2io_driver_name[] = "Neterion";
@@ -86,7 +86,7 @@ static char s2io_driver_version[] = DRV_VERSION;
86static int rxd_size[4] = {32,48,48,64}; 86static int rxd_size[4] = {32,48,48,64};
87static int rxd_count[4] = {127,85,85,63}; 87static int rxd_count[4] = {127,85,85,63};
88 88
89static inline int RXD_IS_UP2DT(RxD_t *rxdp) 89static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
90{ 90{
91 int ret; 91 int ret;
92 92
@@ -111,9 +111,9 @@ static inline int RXD_IS_UP2DT(RxD_t *rxdp)
111#define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status)) 111#define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
112#define PANIC 1 112#define PANIC 1
113#define LOW 2 113#define LOW 2
114static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring) 114static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
115{ 115{
116 mac_info_t *mac_control; 116 struct mac_info *mac_control;
117 117
118 mac_control = &sp->mac_control; 118 mac_control = &sp->mac_control;
119 if (rxb_size <= rxd_count[sp->rxd_mode]) 119 if (rxb_size <= rxd_count[sp->rxd_mode])
@@ -286,7 +286,7 @@ static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
286static void s2io_vlan_rx_register(struct net_device *dev, 286static void s2io_vlan_rx_register(struct net_device *dev,
287 struct vlan_group *grp) 287 struct vlan_group *grp)
288{ 288{
289 nic_t *nic = dev->priv; 289 struct s2io_nic *nic = dev->priv;
290 unsigned long flags; 290 unsigned long flags;
291 291
292 spin_lock_irqsave(&nic->tx_lock, flags); 292 spin_lock_irqsave(&nic->tx_lock, flags);
@@ -297,7 +297,7 @@ static void s2io_vlan_rx_register(struct net_device *dev,
297/* Unregister the vlan */ 297/* Unregister the vlan */
298static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid) 298static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
299{ 299{
300 nic_t *nic = dev->priv; 300 struct s2io_nic *nic = dev->priv;
301 unsigned long flags; 301 unsigned long flags;
302 302
303 spin_lock_irqsave(&nic->tx_lock, flags); 303 spin_lock_irqsave(&nic->tx_lock, flags);
@@ -401,9 +401,10 @@ S2IO_PARM_INT(lro, 0);
401 * aggregation happens until we hit max IP pkt size(64K) 401 * aggregation happens until we hit max IP pkt size(64K)
402 */ 402 */
403S2IO_PARM_INT(lro_max_pkts, 0xFFFF); 403S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
404#ifndef CONFIG_S2IO_NAPI
405S2IO_PARM_INT(indicate_max_pkts, 0); 404S2IO_PARM_INT(indicate_max_pkts, 0);
406#endif 405
406S2IO_PARM_INT(napi, 1);
407S2IO_PARM_INT(ufo, 0);
407 408
408static unsigned int tx_fifo_len[MAX_TX_FIFOS] = 409static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
409 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN}; 410 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
@@ -457,14 +458,14 @@ static int init_shared_mem(struct s2io_nic *nic)
457 u32 size; 458 u32 size;
458 void *tmp_v_addr, *tmp_v_addr_next; 459 void *tmp_v_addr, *tmp_v_addr_next;
459 dma_addr_t tmp_p_addr, tmp_p_addr_next; 460 dma_addr_t tmp_p_addr, tmp_p_addr_next;
460 RxD_block_t *pre_rxd_blk = NULL; 461 struct RxD_block *pre_rxd_blk = NULL;
461 int i, j, blk_cnt, rx_sz, tx_sz; 462 int i, j, blk_cnt;
462 int lst_size, lst_per_page; 463 int lst_size, lst_per_page;
463 struct net_device *dev = nic->dev; 464 struct net_device *dev = nic->dev;
464 unsigned long tmp; 465 unsigned long tmp;
465 buffAdd_t *ba; 466 struct buffAdd *ba;
466 467
467 mac_info_t *mac_control; 468 struct mac_info *mac_control;
468 struct config_param *config; 469 struct config_param *config;
469 470
470 mac_control = &nic->mac_control; 471 mac_control = &nic->mac_control;
@@ -482,13 +483,12 @@ static int init_shared_mem(struct s2io_nic *nic)
482 return -EINVAL; 483 return -EINVAL;
483 } 484 }
484 485
485 lst_size = (sizeof(TxD_t) * config->max_txds); 486 lst_size = (sizeof(struct TxD) * config->max_txds);
486 tx_sz = lst_size * size;
487 lst_per_page = PAGE_SIZE / lst_size; 487 lst_per_page = PAGE_SIZE / lst_size;
488 488
489 for (i = 0; i < config->tx_fifo_num; i++) { 489 for (i = 0; i < config->tx_fifo_num; i++) {
490 int fifo_len = config->tx_cfg[i].fifo_len; 490 int fifo_len = config->tx_cfg[i].fifo_len;
491 int list_holder_size = fifo_len * sizeof(list_info_hold_t); 491 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
492 mac_control->fifos[i].list_info = kmalloc(list_holder_size, 492 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
493 GFP_KERNEL); 493 GFP_KERNEL);
494 if (!mac_control->fifos[i].list_info) { 494 if (!mac_control->fifos[i].list_info) {
@@ -579,10 +579,9 @@ static int init_shared_mem(struct s2io_nic *nic)
579 mac_control->rings[i].block_count; 579 mac_control->rings[i].block_count;
580 } 580 }
581 if (nic->rxd_mode == RXD_MODE_1) 581 if (nic->rxd_mode == RXD_MODE_1)
582 size = (size * (sizeof(RxD1_t))); 582 size = (size * (sizeof(struct RxD1)));
583 else 583 else
584 size = (size * (sizeof(RxD3_t))); 584 size = (size * (sizeof(struct RxD3)));
585 rx_sz = size;
586 585
587 for (i = 0; i < config->rx_ring_num; i++) { 586 for (i = 0; i < config->rx_ring_num; i++) {
588 mac_control->rings[i].rx_curr_get_info.block_index = 0; 587 mac_control->rings[i].rx_curr_get_info.block_index = 0;
@@ -600,7 +599,7 @@ static int init_shared_mem(struct s2io_nic *nic)
600 (rxd_count[nic->rxd_mode] + 1); 599 (rxd_count[nic->rxd_mode] + 1);
601 /* Allocating all the Rx blocks */ 600 /* Allocating all the Rx blocks */
602 for (j = 0; j < blk_cnt; j++) { 601 for (j = 0; j < blk_cnt; j++) {
603 rx_block_info_t *rx_blocks; 602 struct rx_block_info *rx_blocks;
604 int l; 603 int l;
605 604
606 rx_blocks = &mac_control->rings[i].rx_blocks[j]; 605 rx_blocks = &mac_control->rings[i].rx_blocks[j];
@@ -620,9 +619,11 @@ static int init_shared_mem(struct s2io_nic *nic)
620 memset(tmp_v_addr, 0, size); 619 memset(tmp_v_addr, 0, size);
621 rx_blocks->block_virt_addr = tmp_v_addr; 620 rx_blocks->block_virt_addr = tmp_v_addr;
622 rx_blocks->block_dma_addr = tmp_p_addr; 621 rx_blocks->block_dma_addr = tmp_p_addr;
623 rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)* 622 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
624 rxd_count[nic->rxd_mode], 623 rxd_count[nic->rxd_mode],
625 GFP_KERNEL); 624 GFP_KERNEL);
625 if (!rx_blocks->rxds)
626 return -ENOMEM;
626 for (l=0; l<rxd_count[nic->rxd_mode];l++) { 627 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
627 rx_blocks->rxds[l].virt_addr = 628 rx_blocks->rxds[l].virt_addr =
628 rx_blocks->block_virt_addr + 629 rx_blocks->block_virt_addr +
@@ -645,7 +646,7 @@ static int init_shared_mem(struct s2io_nic *nic)
645 mac_control->rings[i].rx_blocks[(j + 1) % 646 mac_control->rings[i].rx_blocks[(j + 1) %
646 blk_cnt].block_dma_addr; 647 blk_cnt].block_dma_addr;
647 648
648 pre_rxd_blk = (RxD_block_t *) tmp_v_addr; 649 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
649 pre_rxd_blk->reserved_2_pNext_RxD_block = 650 pre_rxd_blk->reserved_2_pNext_RxD_block =
650 (unsigned long) tmp_v_addr_next; 651 (unsigned long) tmp_v_addr_next;
651 pre_rxd_blk->pNext_RxD_Blk_physical = 652 pre_rxd_blk->pNext_RxD_Blk_physical =
@@ -661,14 +662,14 @@ static int init_shared_mem(struct s2io_nic *nic)
661 blk_cnt = config->rx_cfg[i].num_rxd / 662 blk_cnt = config->rx_cfg[i].num_rxd /
662 (rxd_count[nic->rxd_mode]+ 1); 663 (rxd_count[nic->rxd_mode]+ 1);
663 mac_control->rings[i].ba = 664 mac_control->rings[i].ba =
664 kmalloc((sizeof(buffAdd_t *) * blk_cnt), 665 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
665 GFP_KERNEL); 666 GFP_KERNEL);
666 if (!mac_control->rings[i].ba) 667 if (!mac_control->rings[i].ba)
667 return -ENOMEM; 668 return -ENOMEM;
668 for (j = 0; j < blk_cnt; j++) { 669 for (j = 0; j < blk_cnt; j++) {
669 int k = 0; 670 int k = 0;
670 mac_control->rings[i].ba[j] = 671 mac_control->rings[i].ba[j] =
671 kmalloc((sizeof(buffAdd_t) * 672 kmalloc((sizeof(struct buffAdd) *
672 (rxd_count[nic->rxd_mode] + 1)), 673 (rxd_count[nic->rxd_mode] + 1)),
673 GFP_KERNEL); 674 GFP_KERNEL);
674 if (!mac_control->rings[i].ba[j]) 675 if (!mac_control->rings[i].ba[j])
@@ -700,7 +701,7 @@ static int init_shared_mem(struct s2io_nic *nic)
700 } 701 }
701 702
702 /* Allocation and initialization of Statistics block */ 703 /* Allocation and initialization of Statistics block */
703 size = sizeof(StatInfo_t); 704 size = sizeof(struct stat_block);
704 mac_control->stats_mem = pci_alloc_consistent 705 mac_control->stats_mem = pci_alloc_consistent
705 (nic->pdev, size, &mac_control->stats_mem_phy); 706 (nic->pdev, size, &mac_control->stats_mem_phy);
706 707
@@ -715,7 +716,7 @@ static int init_shared_mem(struct s2io_nic *nic)
715 mac_control->stats_mem_sz = size; 716 mac_control->stats_mem_sz = size;
716 717
717 tmp_v_addr = mac_control->stats_mem; 718 tmp_v_addr = mac_control->stats_mem;
718 mac_control->stats_info = (StatInfo_t *) tmp_v_addr; 719 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
719 memset(tmp_v_addr, 0, size); 720 memset(tmp_v_addr, 0, size);
720 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name, 721 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
721 (unsigned long long) tmp_p_addr); 722 (unsigned long long) tmp_p_addr);
@@ -735,7 +736,7 @@ static void free_shared_mem(struct s2io_nic *nic)
735 int i, j, blk_cnt, size; 736 int i, j, blk_cnt, size;
736 void *tmp_v_addr; 737 void *tmp_v_addr;
737 dma_addr_t tmp_p_addr; 738 dma_addr_t tmp_p_addr;
738 mac_info_t *mac_control; 739 struct mac_info *mac_control;
739 struct config_param *config; 740 struct config_param *config;
740 int lst_size, lst_per_page; 741 int lst_size, lst_per_page;
741 struct net_device *dev = nic->dev; 742 struct net_device *dev = nic->dev;
@@ -746,7 +747,7 @@ static void free_shared_mem(struct s2io_nic *nic)
746 mac_control = &nic->mac_control; 747 mac_control = &nic->mac_control;
747 config = &nic->config; 748 config = &nic->config;
748 749
749 lst_size = (sizeof(TxD_t) * config->max_txds); 750 lst_size = (sizeof(struct TxD) * config->max_txds);
750 lst_per_page = PAGE_SIZE / lst_size; 751 lst_per_page = PAGE_SIZE / lst_size;
751 752
752 for (i = 0; i < config->tx_fifo_num; i++) { 753 for (i = 0; i < config->tx_fifo_num; i++) {
@@ -809,7 +810,7 @@ static void free_shared_mem(struct s2io_nic *nic)
809 if (!mac_control->rings[i].ba[j]) 810 if (!mac_control->rings[i].ba[j])
810 continue; 811 continue;
811 while (k != rxd_count[nic->rxd_mode]) { 812 while (k != rxd_count[nic->rxd_mode]) {
812 buffAdd_t *ba = 813 struct buffAdd *ba =
813 &mac_control->rings[i].ba[j][k]; 814 &mac_control->rings[i].ba[j][k];
814 kfree(ba->ba_0_org); 815 kfree(ba->ba_0_org);
815 kfree(ba->ba_1_org); 816 kfree(ba->ba_1_org);
@@ -835,9 +836,9 @@ static void free_shared_mem(struct s2io_nic *nic)
835 * s2io_verify_pci_mode - 836 * s2io_verify_pci_mode -
836 */ 837 */
837 838
838static int s2io_verify_pci_mode(nic_t *nic) 839static int s2io_verify_pci_mode(struct s2io_nic *nic)
839{ 840{
840 XENA_dev_config_t __iomem *bar0 = nic->bar0; 841 struct XENA_dev_config __iomem *bar0 = nic->bar0;
841 register u64 val64 = 0; 842 register u64 val64 = 0;
842 int mode; 843 int mode;
843 844
@@ -868,9 +869,9 @@ static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
868/** 869/**
869 * s2io_print_pci_mode - 870 * s2io_print_pci_mode -
870 */ 871 */
871static int s2io_print_pci_mode(nic_t *nic) 872static int s2io_print_pci_mode(struct s2io_nic *nic)
872{ 873{
873 XENA_dev_config_t __iomem *bar0 = nic->bar0; 874 struct XENA_dev_config __iomem *bar0 = nic->bar0;
874 register u64 val64 = 0; 875 register u64 val64 = 0;
875 int mode; 876 int mode;
876 struct config_param *config = &nic->config; 877 struct config_param *config = &nic->config;
@@ -938,13 +939,13 @@ static int s2io_print_pci_mode(nic_t *nic)
938 939
939static int init_nic(struct s2io_nic *nic) 940static int init_nic(struct s2io_nic *nic)
940{ 941{
941 XENA_dev_config_t __iomem *bar0 = nic->bar0; 942 struct XENA_dev_config __iomem *bar0 = nic->bar0;
942 struct net_device *dev = nic->dev; 943 struct net_device *dev = nic->dev;
943 register u64 val64 = 0; 944 register u64 val64 = 0;
944 void __iomem *add; 945 void __iomem *add;
945 u32 time; 946 u32 time;
946 int i, j; 947 int i, j;
947 mac_info_t *mac_control; 948 struct mac_info *mac_control;
948 struct config_param *config; 949 struct config_param *config;
949 int dtx_cnt = 0; 950 int dtx_cnt = 0;
950 unsigned long long mem_share; 951 unsigned long long mem_share;
@@ -1414,7 +1415,7 @@ static int init_nic(struct s2io_nic *nic)
1414 1415
1415 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | 1416 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1416 TTI_DATA2_MEM_TX_UFC_B(0x20) | 1417 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1417 TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80); 1418 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1418 writeq(val64, &bar0->tti_data2_mem); 1419 writeq(val64, &bar0->tti_data2_mem);
1419 1420
1420 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD; 1421 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
@@ -1610,7 +1611,8 @@ static int init_nic(struct s2io_nic *nic)
1610 * that does not start on an ADB to reduce disconnects. 1611 * that does not start on an ADB to reduce disconnects.
1611 */ 1612 */
1612 if (nic->device_type == XFRAME_II_DEVICE) { 1613 if (nic->device_type == XFRAME_II_DEVICE) {
1613 val64 = EXT_REQ_EN | MISC_LINK_STABILITY_PRD(3); 1614 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1615 MISC_LINK_STABILITY_PRD(3);
1614 writeq(val64, &bar0->misc_control); 1616 writeq(val64, &bar0->misc_control);
1615 val64 = readq(&bar0->pic_control2); 1617 val64 = readq(&bar0->pic_control2);
1616 val64 &= ~(BIT(13)|BIT(14)|BIT(15)); 1618 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
@@ -1626,7 +1628,7 @@ static int init_nic(struct s2io_nic *nic)
1626#define LINK_UP_DOWN_INTERRUPT 1 1628#define LINK_UP_DOWN_INTERRUPT 1
1627#define MAC_RMAC_ERR_TIMER 2 1629#define MAC_RMAC_ERR_TIMER 2
1628 1630
1629static int s2io_link_fault_indication(nic_t *nic) 1631static int s2io_link_fault_indication(struct s2io_nic *nic)
1630{ 1632{
1631 if (nic->intr_type != INTA) 1633 if (nic->intr_type != INTA)
1632 return MAC_RMAC_ERR_TIMER; 1634 return MAC_RMAC_ERR_TIMER;
@@ -1649,14 +1651,14 @@ static int s2io_link_fault_indication(nic_t *nic)
1649 1651
1650static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag) 1652static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1651{ 1653{
1652 XENA_dev_config_t __iomem *bar0 = nic->bar0; 1654 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1653 register u64 val64 = 0, temp64 = 0; 1655 register u64 val64 = 0, temp64 = 0;
1654 1656
1655 /* Top level interrupt classification */ 1657 /* Top level interrupt classification */
1656 /* PIC Interrupts */ 1658 /* PIC Interrupts */
1657 if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) { 1659 if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1658 /* Enable PIC Intrs in the general intr mask register */ 1660 /* Enable PIC Intrs in the general intr mask register */
1659 val64 = TXPIC_INT_M | PIC_RX_INT_M; 1661 val64 = TXPIC_INT_M;
1660 if (flag == ENABLE_INTRS) { 1662 if (flag == ENABLE_INTRS) {
1661 temp64 = readq(&bar0->general_int_mask); 1663 temp64 = readq(&bar0->general_int_mask);
1662 temp64 &= ~((u64) val64); 1664 temp64 &= ~((u64) val64);
@@ -1694,70 +1696,6 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1694 } 1696 }
1695 } 1697 }
1696 1698
1697 /* DMA Interrupts */
1698 /* Enabling/Disabling Tx DMA interrupts */
1699 if (mask & TX_DMA_INTR) {
1700 /* Enable TxDMA Intrs in the general intr mask register */
1701 val64 = TXDMA_INT_M;
1702 if (flag == ENABLE_INTRS) {
1703 temp64 = readq(&bar0->general_int_mask);
1704 temp64 &= ~((u64) val64);
1705 writeq(temp64, &bar0->general_int_mask);
1706 /*
1707 * Keep all interrupts other than PFC interrupt
1708 * and PCC interrupt disabled in DMA level.
1709 */
1710 val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1711 TXDMA_PCC_INT_M);
1712 writeq(val64, &bar0->txdma_int_mask);
1713 /*
1714 * Enable only the MISC error 1 interrupt in PFC block
1715 */
1716 val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1717 writeq(val64, &bar0->pfc_err_mask);
1718 /*
1719 * Enable only the FB_ECC error interrupt in PCC block
1720 */
1721 val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1722 writeq(val64, &bar0->pcc_err_mask);
1723 } else if (flag == DISABLE_INTRS) {
1724 /*
1725 * Disable TxDMA Intrs in the general intr mask
1726 * register
1727 */
1728 writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1729 writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1730 temp64 = readq(&bar0->general_int_mask);
1731 val64 |= temp64;
1732 writeq(val64, &bar0->general_int_mask);
1733 }
1734 }
1735
1736 /* Enabling/Disabling Rx DMA interrupts */
1737 if (mask & RX_DMA_INTR) {
1738 /* Enable RxDMA Intrs in the general intr mask register */
1739 val64 = RXDMA_INT_M;
1740 if (flag == ENABLE_INTRS) {
1741 temp64 = readq(&bar0->general_int_mask);
1742 temp64 &= ~((u64) val64);
1743 writeq(temp64, &bar0->general_int_mask);
1744 /*
1745 * All RxDMA block interrupts are disabled for now
1746 * TODO
1747 */
1748 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1749 } else if (flag == DISABLE_INTRS) {
1750 /*
1751 * Disable RxDMA Intrs in the general intr mask
1752 * register
1753 */
1754 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1755 temp64 = readq(&bar0->general_int_mask);
1756 val64 |= temp64;
1757 writeq(val64, &bar0->general_int_mask);
1758 }
1759 }
1760
1761 /* MAC Interrupts */ 1699 /* MAC Interrupts */
1762 /* Enabling/Disabling MAC interrupts */ 1700 /* Enabling/Disabling MAC interrupts */
1763 if (mask & (TX_MAC_INTR | RX_MAC_INTR)) { 1701 if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
@@ -1784,53 +1722,6 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1784 } 1722 }
1785 } 1723 }
1786 1724
1787 /* XGXS Interrupts */
1788 if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1789 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1790 if (flag == ENABLE_INTRS) {
1791 temp64 = readq(&bar0->general_int_mask);
1792 temp64 &= ~((u64) val64);
1793 writeq(temp64, &bar0->general_int_mask);
1794 /*
1795 * All XGXS block error interrupts are disabled for now
1796 * TODO
1797 */
1798 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1799 } else if (flag == DISABLE_INTRS) {
1800 /*
1801 * Disable MC Intrs in the general intr mask register
1802 */
1803 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1804 temp64 = readq(&bar0->general_int_mask);
1805 val64 |= temp64;
1806 writeq(val64, &bar0->general_int_mask);
1807 }
1808 }
1809
1810 /* Memory Controller(MC) interrupts */
1811 if (mask & MC_INTR) {
1812 val64 = MC_INT_M;
1813 if (flag == ENABLE_INTRS) {
1814 temp64 = readq(&bar0->general_int_mask);
1815 temp64 &= ~((u64) val64);
1816 writeq(temp64, &bar0->general_int_mask);
1817 /*
1818 * Enable all MC Intrs.
1819 */
1820 writeq(0x0, &bar0->mc_int_mask);
1821 writeq(0x0, &bar0->mc_err_mask);
1822 } else if (flag == DISABLE_INTRS) {
1823 /*
1824 * Disable MC Intrs in the general intr mask register
1825 */
1826 writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1827 temp64 = readq(&bar0->general_int_mask);
1828 val64 |= temp64;
1829 writeq(val64, &bar0->general_int_mask);
1830 }
1831 }
1832
1833
1834 /* Tx traffic interrupts */ 1725 /* Tx traffic interrupts */
1835 if (mask & TX_TRAFFIC_INTR) { 1726 if (mask & TX_TRAFFIC_INTR) {
1836 val64 = TXTRAFFIC_INT_M; 1727 val64 = TXTRAFFIC_INT_M;
@@ -1877,41 +1768,36 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1877 } 1768 }
1878} 1769}
1879 1770
1880static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc) 1771/**
1772 * verify_pcc_quiescent- Checks for PCC quiescent state
1773 * Return: 1 If PCC is quiescence
1774 * 0 If PCC is not quiescence
1775 */
1776static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
1881{ 1777{
1882 int ret = 0; 1778 int ret = 0, herc;
1779 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1780 u64 val64 = readq(&bar0->adapter_status);
1781
1782 herc = (sp->device_type == XFRAME_II_DEVICE);
1883 1783
1884 if (flag == FALSE) { 1784 if (flag == FALSE) {
1885 if ((!herc && (rev_id >= 4)) || herc) { 1785 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
1886 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) && 1786 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
1887 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1888 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1889 ret = 1; 1787 ret = 1;
1890 } 1788 } else {
1891 }else { 1789 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1892 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1893 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1894 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1895 ret = 1; 1790 ret = 1;
1896 }
1897 } 1791 }
1898 } else { 1792 } else {
1899 if ((!herc && (rev_id >= 4)) || herc) { 1793 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
1900 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) == 1794 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1901 ADAPTER_STATUS_RMAC_PCC_IDLE) && 1795 ADAPTER_STATUS_RMAC_PCC_IDLE))
1902 (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1903 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1904 ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1905 ret = 1; 1796 ret = 1;
1906 }
1907 } else { 1797 } else {
1908 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) == 1798 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1909 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) && 1799 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1910 (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1911 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1912 ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1913 ret = 1; 1800 ret = 1;
1914 }
1915 } 1801 }
1916 } 1802 }
1917 1803
@@ -1919,9 +1805,6 @@ static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
1919} 1805}
1920/** 1806/**
1921 * verify_xena_quiescence - Checks whether the H/W is ready 1807 * verify_xena_quiescence - Checks whether the H/W is ready
1922 * @val64 : Value read from adapter status register.
1923 * @flag : indicates if the adapter enable bit was ever written once
1924 * before.
1925 * Description: Returns whether the H/W is ready to go or not. Depending 1808 * Description: Returns whether the H/W is ready to go or not. Depending
1926 * on whether adapter enable bit was written or not the comparison 1809 * on whether adapter enable bit was written or not the comparison
1927 * differs and the calling function passes the input argument flag to 1810 * differs and the calling function passes the input argument flag to
@@ -1930,24 +1813,63 @@ static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
1930 * 0 If Xena is not quiescence 1813 * 0 If Xena is not quiescence
1931 */ 1814 */
1932 1815
1933static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag) 1816static int verify_xena_quiescence(struct s2io_nic *sp)
1934{ 1817{
1935 int ret = 0, herc; 1818 int mode;
1936 u64 tmp64 = ~((u64) val64); 1819 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1937 int rev_id = get_xena_rev_id(sp->pdev); 1820 u64 val64 = readq(&bar0->adapter_status);
1821 mode = s2io_verify_pci_mode(sp);
1938 1822
1939 herc = (sp->device_type == XFRAME_II_DEVICE); 1823 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
1940 if (! 1824 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
1941 (tmp64 & 1825 return 0;
1942 (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY | 1826 }
1943 ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY | 1827 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
1944 ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY | 1828 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
1945 ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK | 1829 return 0;
1946 ADAPTER_STATUS_P_PLL_LOCK))) { 1830 }
1947 ret = check_prc_pcc_state(val64, flag, rev_id, herc); 1831 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
1832 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
1833 return 0;
1834 }
1835 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
1836 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
1837 return 0;
1838 }
1839 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
1840 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
1841 return 0;
1842 }
1843 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
1844 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
1845 return 0;
1846 }
1847 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
1848 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
1849 return 0;
1850 }
1851 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
1852 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
1853 return 0;
1948 } 1854 }
1949 1855
1950 return ret; 1856 /*
1857 * In PCI 33 mode, the P_PLL is not used, and therefore,
1858 * the the P_PLL_LOCK bit in the adapter_status register will
1859 * not be asserted.
1860 */
1861 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
1862 sp->device_type == XFRAME_II_DEVICE && mode !=
1863 PCI_MODE_PCI_33) {
1864 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
1865 return 0;
1866 }
1867 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1868 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1869 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
1870 return 0;
1871 }
1872 return 1;
1951} 1873}
1952 1874
1953/** 1875/**
@@ -1958,9 +1880,9 @@ static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
1958 * 1880 *
1959 */ 1881 */
1960 1882
1961static void fix_mac_address(nic_t * sp) 1883static void fix_mac_address(struct s2io_nic * sp)
1962{ 1884{
1963 XENA_dev_config_t __iomem *bar0 = sp->bar0; 1885 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1964 u64 val64; 1886 u64 val64;
1965 int i = 0; 1887 int i = 0;
1966 1888
@@ -1986,11 +1908,11 @@ static void fix_mac_address(nic_t * sp)
1986 1908
1987static int start_nic(struct s2io_nic *nic) 1909static int start_nic(struct s2io_nic *nic)
1988{ 1910{
1989 XENA_dev_config_t __iomem *bar0 = nic->bar0; 1911 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1990 struct net_device *dev = nic->dev; 1912 struct net_device *dev = nic->dev;
1991 register u64 val64 = 0; 1913 register u64 val64 = 0;
1992 u16 subid, i; 1914 u16 subid, i;
1993 mac_info_t *mac_control; 1915 struct mac_info *mac_control;
1994 struct config_param *config; 1916 struct config_param *config;
1995 1917
1996 mac_control = &nic->mac_control; 1918 mac_control = &nic->mac_control;
@@ -2052,7 +1974,7 @@ static int start_nic(struct s2io_nic *nic)
2052 * it. 1974 * it.
2053 */ 1975 */
2054 val64 = readq(&bar0->adapter_status); 1976 val64 = readq(&bar0->adapter_status);
2055 if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) { 1977 if (!verify_xena_quiescence(nic)) {
2056 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name); 1978 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2057 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n", 1979 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2058 (unsigned long long) val64); 1980 (unsigned long long) val64);
@@ -2095,11 +2017,12 @@ static int start_nic(struct s2io_nic *nic)
2095/** 2017/**
2096 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb 2018 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2097 */ 2019 */
2098static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, int get_off) 2020static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2021 TxD *txdlp, int get_off)
2099{ 2022{
2100 nic_t *nic = fifo_data->nic; 2023 struct s2io_nic *nic = fifo_data->nic;
2101 struct sk_buff *skb; 2024 struct sk_buff *skb;
2102 TxD_t *txds; 2025 struct TxD *txds;
2103 u16 j, frg_cnt; 2026 u16 j, frg_cnt;
2104 2027
2105 txds = txdlp; 2028 txds = txdlp;
@@ -2113,7 +2036,7 @@ static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, in
2113 skb = (struct sk_buff *) ((unsigned long) 2036 skb = (struct sk_buff *) ((unsigned long)
2114 txds->Host_Control); 2037 txds->Host_Control);
2115 if (!skb) { 2038 if (!skb) {
2116 memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds)); 2039 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2117 return NULL; 2040 return NULL;
2118 } 2041 }
2119 pci_unmap_single(nic->pdev, (dma_addr_t) 2042 pci_unmap_single(nic->pdev, (dma_addr_t)
@@ -2132,7 +2055,7 @@ static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, in
2132 frag->size, PCI_DMA_TODEVICE); 2055 frag->size, PCI_DMA_TODEVICE);
2133 } 2056 }
2134 } 2057 }
2135 memset(txdlp,0, (sizeof(TxD_t) * fifo_data->max_txds)); 2058 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
2136 return(skb); 2059 return(skb);
2137} 2060}
2138 2061
@@ -2148,9 +2071,9 @@ static void free_tx_buffers(struct s2io_nic *nic)
2148{ 2071{
2149 struct net_device *dev = nic->dev; 2072 struct net_device *dev = nic->dev;
2150 struct sk_buff *skb; 2073 struct sk_buff *skb;
2151 TxD_t *txdp; 2074 struct TxD *txdp;
2152 int i, j; 2075 int i, j;
2153 mac_info_t *mac_control; 2076 struct mac_info *mac_control;
2154 struct config_param *config; 2077 struct config_param *config;
2155 int cnt = 0; 2078 int cnt = 0;
2156 2079
@@ -2159,7 +2082,7 @@ static void free_tx_buffers(struct s2io_nic *nic)
2159 2082
2160 for (i = 0; i < config->tx_fifo_num; i++) { 2083 for (i = 0; i < config->tx_fifo_num; i++) {
2161 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) { 2084 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2162 txdp = (TxD_t *) mac_control->fifos[i].list_info[j]. 2085 txdp = (struct TxD *) mac_control->fifos[i].list_info[j].
2163 list_virt_addr; 2086 list_virt_addr;
2164 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j); 2087 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2165 if (skb) { 2088 if (skb) {
@@ -2187,10 +2110,10 @@ static void free_tx_buffers(struct s2io_nic *nic)
2187 2110
2188static void stop_nic(struct s2io_nic *nic) 2111static void stop_nic(struct s2io_nic *nic)
2189{ 2112{
2190 XENA_dev_config_t __iomem *bar0 = nic->bar0; 2113 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2191 register u64 val64 = 0; 2114 register u64 val64 = 0;
2192 u16 interruptible; 2115 u16 interruptible;
2193 mac_info_t *mac_control; 2116 struct mac_info *mac_control;
2194 struct config_param *config; 2117 struct config_param *config;
2195 2118
2196 mac_control = &nic->mac_control; 2119 mac_control = &nic->mac_control;
@@ -2208,14 +2131,15 @@ static void stop_nic(struct s2io_nic *nic)
2208 writeq(val64, &bar0->adapter_control); 2131 writeq(val64, &bar0->adapter_control);
2209} 2132}
2210 2133
2211static int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb) 2134static int fill_rxd_3buf(struct s2io_nic *nic, struct RxD_t *rxdp, struct \
2135 sk_buff *skb)
2212{ 2136{
2213 struct net_device *dev = nic->dev; 2137 struct net_device *dev = nic->dev;
2214 struct sk_buff *frag_list; 2138 struct sk_buff *frag_list;
2215 void *tmp; 2139 void *tmp;
2216 2140
2217 /* Buffer-1 receives L3/L4 headers */ 2141 /* Buffer-1 receives L3/L4 headers */
2218 ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single 2142 ((struct RxD3*)rxdp)->Buffer1_ptr = pci_map_single
2219 (nic->pdev, skb->data, l3l4hdr_size + 4, 2143 (nic->pdev, skb->data, l3l4hdr_size + 4,
2220 PCI_DMA_FROMDEVICE); 2144 PCI_DMA_FROMDEVICE);
2221 2145
@@ -2226,13 +2150,14 @@ static int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
2226 return -ENOMEM ; 2150 return -ENOMEM ;
2227 } 2151 }
2228 frag_list = skb_shinfo(skb)->frag_list; 2152 frag_list = skb_shinfo(skb)->frag_list;
2153 skb->truesize += frag_list->truesize;
2229 frag_list->next = NULL; 2154 frag_list->next = NULL;
2230 tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1); 2155 tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2231 frag_list->data = tmp; 2156 frag_list->data = tmp;
2232 frag_list->tail = tmp; 2157 frag_list->tail = tmp;
2233 2158
2234 /* Buffer-2 receives L4 data payload */ 2159 /* Buffer-2 receives L4 data payload */
2235 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev, 2160 ((struct RxD3*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2236 frag_list->data, dev->mtu, 2161 frag_list->data, dev->mtu,
2237 PCI_DMA_FROMDEVICE); 2162 PCI_DMA_FROMDEVICE);
2238 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4); 2163 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
@@ -2266,18 +2191,16 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2266{ 2191{
2267 struct net_device *dev = nic->dev; 2192 struct net_device *dev = nic->dev;
2268 struct sk_buff *skb; 2193 struct sk_buff *skb;
2269 RxD_t *rxdp; 2194 struct RxD_t *rxdp;
2270 int off, off1, size, block_no, block_no1; 2195 int off, off1, size, block_no, block_no1;
2271 u32 alloc_tab = 0; 2196 u32 alloc_tab = 0;
2272 u32 alloc_cnt; 2197 u32 alloc_cnt;
2273 mac_info_t *mac_control; 2198 struct mac_info *mac_control;
2274 struct config_param *config; 2199 struct config_param *config;
2275 u64 tmp; 2200 u64 tmp;
2276 buffAdd_t *ba; 2201 struct buffAdd *ba;
2277#ifndef CONFIG_S2IO_NAPI
2278 unsigned long flags; 2202 unsigned long flags;
2279#endif 2203 struct RxD_t *first_rxdp = NULL;
2280 RxD_t *first_rxdp = NULL;
2281 2204
2282 mac_control = &nic->mac_control; 2205 mac_control = &nic->mac_control;
2283 config = &nic->config; 2206 config = &nic->config;
@@ -2320,12 +2243,15 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2320 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n", 2243 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2321 dev->name, rxdp); 2244 dev->name, rxdp);
2322 } 2245 }
2323#ifndef CONFIG_S2IO_NAPI 2246 if(!napi) {
2324 spin_lock_irqsave(&nic->put_lock, flags); 2247 spin_lock_irqsave(&nic->put_lock, flags);
2325 mac_control->rings[ring_no].put_pos = 2248 mac_control->rings[ring_no].put_pos =
2326 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off; 2249 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2327 spin_unlock_irqrestore(&nic->put_lock, flags); 2250 spin_unlock_irqrestore(&nic->put_lock, flags);
2328#endif 2251 } else {
2252 mac_control->rings[ring_no].put_pos =
2253 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2254 }
2329 if ((rxdp->Control_1 & RXD_OWN_XENA) && 2255 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2330 ((nic->rxd_mode >= RXD_MODE_3A) && 2256 ((nic->rxd_mode >= RXD_MODE_3A) &&
2331 (rxdp->Control_2 & BIT(0)))) { 2257 (rxdp->Control_2 & BIT(0)))) {
@@ -2356,9 +2282,9 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2356 } 2282 }
2357 if (nic->rxd_mode == RXD_MODE_1) { 2283 if (nic->rxd_mode == RXD_MODE_1) {
2358 /* 1 buffer mode - normal operation mode */ 2284 /* 1 buffer mode - normal operation mode */
2359 memset(rxdp, 0, sizeof(RxD1_t)); 2285 memset(rxdp, 0, sizeof(struct RxD1));
2360 skb_reserve(skb, NET_IP_ALIGN); 2286 skb_reserve(skb, NET_IP_ALIGN);
2361 ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single 2287 ((struct RxD1*)rxdp)->Buffer0_ptr = pci_map_single
2362 (nic->pdev, skb->data, size - NET_IP_ALIGN, 2288 (nic->pdev, skb->data, size - NET_IP_ALIGN,
2363 PCI_DMA_FROMDEVICE); 2289 PCI_DMA_FROMDEVICE);
2364 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN); 2290 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
@@ -2375,7 +2301,7 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2375 * payload 2301 * payload
2376 */ 2302 */
2377 2303
2378 memset(rxdp, 0, sizeof(RxD3_t)); 2304 memset(rxdp, 0, sizeof(struct RxD3));
2379 ba = &mac_control->rings[ring_no].ba[block_no][off]; 2305 ba = &mac_control->rings[ring_no].ba[block_no][off];
2380 skb_reserve(skb, BUF0_LEN); 2306 skb_reserve(skb, BUF0_LEN);
2381 tmp = (u64)(unsigned long) skb->data; 2307 tmp = (u64)(unsigned long) skb->data;
@@ -2384,13 +2310,13 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2384 skb->data = (void *) (unsigned long)tmp; 2310 skb->data = (void *) (unsigned long)tmp;
2385 skb->tail = (void *) (unsigned long)tmp; 2311 skb->tail = (void *) (unsigned long)tmp;
2386 2312
2387 if (!(((RxD3_t*)rxdp)->Buffer0_ptr)) 2313 if (!(((struct RxD3*)rxdp)->Buffer0_ptr))
2388 ((RxD3_t*)rxdp)->Buffer0_ptr = 2314 ((struct RxD3*)rxdp)->Buffer0_ptr =
2389 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN, 2315 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2390 PCI_DMA_FROMDEVICE); 2316 PCI_DMA_FROMDEVICE);
2391 else 2317 else
2392 pci_dma_sync_single_for_device(nic->pdev, 2318 pci_dma_sync_single_for_device(nic->pdev,
2393 (dma_addr_t) ((RxD3_t*)rxdp)->Buffer0_ptr, 2319 (dma_addr_t) ((struct RxD3*)rxdp)->Buffer0_ptr,
2394 BUF0_LEN, PCI_DMA_FROMDEVICE); 2320 BUF0_LEN, PCI_DMA_FROMDEVICE);
2395 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN); 2321 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2396 if (nic->rxd_mode == RXD_MODE_3B) { 2322 if (nic->rxd_mode == RXD_MODE_3B) {
@@ -2400,13 +2326,13 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2400 * Buffer2 will have L3/L4 header plus 2326 * Buffer2 will have L3/L4 header plus
2401 * L4 payload 2327 * L4 payload
2402 */ 2328 */
2403 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single 2329 ((struct RxD3*)rxdp)->Buffer2_ptr = pci_map_single
2404 (nic->pdev, skb->data, dev->mtu + 4, 2330 (nic->pdev, skb->data, dev->mtu + 4,
2405 PCI_DMA_FROMDEVICE); 2331 PCI_DMA_FROMDEVICE);
2406 2332
2407 /* Buffer-1 will be dummy buffer. Not used */ 2333 /* Buffer-1 will be dummy buffer. Not used */
2408 if (!(((RxD3_t*)rxdp)->Buffer1_ptr)) { 2334 if (!(((struct RxD3*)rxdp)->Buffer1_ptr)) {
2409 ((RxD3_t*)rxdp)->Buffer1_ptr = 2335 ((struct RxD3*)rxdp)->Buffer1_ptr =
2410 pci_map_single(nic->pdev, 2336 pci_map_single(nic->pdev,
2411 ba->ba_1, BUF1_LEN, 2337 ba->ba_1, BUF1_LEN,
2412 PCI_DMA_FROMDEVICE); 2338 PCI_DMA_FROMDEVICE);
@@ -2466,9 +2392,9 @@ static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2466 struct net_device *dev = sp->dev; 2392 struct net_device *dev = sp->dev;
2467 int j; 2393 int j;
2468 struct sk_buff *skb; 2394 struct sk_buff *skb;
2469 RxD_t *rxdp; 2395 struct RxD_t *rxdp;
2470 mac_info_t *mac_control; 2396 struct mac_info *mac_control;
2471 buffAdd_t *ba; 2397 struct buffAdd *ba;
2472 2398
2473 mac_control = &sp->mac_control; 2399 mac_control = &sp->mac_control;
2474 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) { 2400 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
@@ -2481,41 +2407,41 @@ static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2481 } 2407 }
2482 if (sp->rxd_mode == RXD_MODE_1) { 2408 if (sp->rxd_mode == RXD_MODE_1) {
2483 pci_unmap_single(sp->pdev, (dma_addr_t) 2409 pci_unmap_single(sp->pdev, (dma_addr_t)
2484 ((RxD1_t*)rxdp)->Buffer0_ptr, 2410 ((struct RxD1*)rxdp)->Buffer0_ptr,
2485 dev->mtu + 2411 dev->mtu +
2486 HEADER_ETHERNET_II_802_3_SIZE 2412 HEADER_ETHERNET_II_802_3_SIZE
2487 + HEADER_802_2_SIZE + 2413 + HEADER_802_2_SIZE +
2488 HEADER_SNAP_SIZE, 2414 HEADER_SNAP_SIZE,
2489 PCI_DMA_FROMDEVICE); 2415 PCI_DMA_FROMDEVICE);
2490 memset(rxdp, 0, sizeof(RxD1_t)); 2416 memset(rxdp, 0, sizeof(struct RxD1));
2491 } else if(sp->rxd_mode == RXD_MODE_3B) { 2417 } else if(sp->rxd_mode == RXD_MODE_3B) {
2492 ba = &mac_control->rings[ring_no]. 2418 ba = &mac_control->rings[ring_no].
2493 ba[blk][j]; 2419 ba[blk][j];
2494 pci_unmap_single(sp->pdev, (dma_addr_t) 2420 pci_unmap_single(sp->pdev, (dma_addr_t)
2495 ((RxD3_t*)rxdp)->Buffer0_ptr, 2421 ((struct RxD3*)rxdp)->Buffer0_ptr,
2496 BUF0_LEN, 2422 BUF0_LEN,
2497 PCI_DMA_FROMDEVICE); 2423 PCI_DMA_FROMDEVICE);
2498 pci_unmap_single(sp->pdev, (dma_addr_t) 2424 pci_unmap_single(sp->pdev, (dma_addr_t)
2499 ((RxD3_t*)rxdp)->Buffer1_ptr, 2425 ((struct RxD3*)rxdp)->Buffer1_ptr,
2500 BUF1_LEN, 2426 BUF1_LEN,
2501 PCI_DMA_FROMDEVICE); 2427 PCI_DMA_FROMDEVICE);
2502 pci_unmap_single(sp->pdev, (dma_addr_t) 2428 pci_unmap_single(sp->pdev, (dma_addr_t)
2503 ((RxD3_t*)rxdp)->Buffer2_ptr, 2429 ((struct RxD3*)rxdp)->Buffer2_ptr,
2504 dev->mtu + 4, 2430 dev->mtu + 4,
2505 PCI_DMA_FROMDEVICE); 2431 PCI_DMA_FROMDEVICE);
2506 memset(rxdp, 0, sizeof(RxD3_t)); 2432 memset(rxdp, 0, sizeof(struct RxD3));
2507 } else { 2433 } else {
2508 pci_unmap_single(sp->pdev, (dma_addr_t) 2434 pci_unmap_single(sp->pdev, (dma_addr_t)
2509 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN, 2435 ((struct RxD3*)rxdp)->Buffer0_ptr, BUF0_LEN,
2510 PCI_DMA_FROMDEVICE); 2436 PCI_DMA_FROMDEVICE);
2511 pci_unmap_single(sp->pdev, (dma_addr_t) 2437 pci_unmap_single(sp->pdev, (dma_addr_t)
2512 ((RxD3_t*)rxdp)->Buffer1_ptr, 2438 ((struct RxD3*)rxdp)->Buffer1_ptr,
2513 l3l4hdr_size + 4, 2439 l3l4hdr_size + 4,
2514 PCI_DMA_FROMDEVICE); 2440 PCI_DMA_FROMDEVICE);
2515 pci_unmap_single(sp->pdev, (dma_addr_t) 2441 pci_unmap_single(sp->pdev, (dma_addr_t)
2516 ((RxD3_t*)rxdp)->Buffer2_ptr, dev->mtu, 2442 ((struct RxD3*)rxdp)->Buffer2_ptr, dev->mtu,
2517 PCI_DMA_FROMDEVICE); 2443 PCI_DMA_FROMDEVICE);
2518 memset(rxdp, 0, sizeof(RxD3_t)); 2444 memset(rxdp, 0, sizeof(struct RxD3));
2519 } 2445 }
2520 dev_kfree_skb(skb); 2446 dev_kfree_skb(skb);
2521 atomic_dec(&sp->rx_bufs_left[ring_no]); 2447 atomic_dec(&sp->rx_bufs_left[ring_no]);
@@ -2535,7 +2461,7 @@ static void free_rx_buffers(struct s2io_nic *sp)
2535{ 2461{
2536 struct net_device *dev = sp->dev; 2462 struct net_device *dev = sp->dev;
2537 int i, blk = 0, buf_cnt = 0; 2463 int i, blk = 0, buf_cnt = 0;
2538 mac_info_t *mac_control; 2464 struct mac_info *mac_control;
2539 struct config_param *config; 2465 struct config_param *config;
2540 2466
2541 mac_control = &sp->mac_control; 2467 mac_control = &sp->mac_control;
@@ -2568,15 +2494,13 @@ static void free_rx_buffers(struct s2io_nic *sp)
2568 * 0 on success and 1 if there are No Rx packets to be processed. 2494 * 0 on success and 1 if there are No Rx packets to be processed.
2569 */ 2495 */
2570 2496
2571#if defined(CONFIG_S2IO_NAPI)
2572static int s2io_poll(struct net_device *dev, int *budget) 2497static int s2io_poll(struct net_device *dev, int *budget)
2573{ 2498{
2574 nic_t *nic = dev->priv; 2499 struct s2io_nic *nic = dev->priv;
2575 int pkt_cnt = 0, org_pkts_to_process; 2500 int pkt_cnt = 0, org_pkts_to_process;
2576 mac_info_t *mac_control; 2501 struct mac_info *mac_control;
2577 struct config_param *config; 2502 struct config_param *config;
2578 XENA_dev_config_t __iomem *bar0 = nic->bar0; 2503 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2579 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2580 int i; 2504 int i;
2581 2505
2582 atomic_inc(&nic->isr_cnt); 2506 atomic_inc(&nic->isr_cnt);
@@ -2588,8 +2512,8 @@ static int s2io_poll(struct net_device *dev, int *budget)
2588 nic->pkts_to_process = dev->quota; 2512 nic->pkts_to_process = dev->quota;
2589 org_pkts_to_process = nic->pkts_to_process; 2513 org_pkts_to_process = nic->pkts_to_process;
2590 2514
2591 writeq(val64, &bar0->rx_traffic_int); 2515 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2592 val64 = readl(&bar0->rx_traffic_int); 2516 readl(&bar0->rx_traffic_int);
2593 2517
2594 for (i = 0; i < config->rx_ring_num; i++) { 2518 for (i = 0; i < config->rx_ring_num; i++) {
2595 rx_intr_handler(&mac_control->rings[i]); 2519 rx_intr_handler(&mac_control->rings[i]);
@@ -2615,7 +2539,7 @@ static int s2io_poll(struct net_device *dev, int *budget)
2615 } 2539 }
2616 /* Re enable the Rx interrupts. */ 2540 /* Re enable the Rx interrupts. */
2617 writeq(0x0, &bar0->rx_traffic_mask); 2541 writeq(0x0, &bar0->rx_traffic_mask);
2618 val64 = readl(&bar0->rx_traffic_mask); 2542 readl(&bar0->rx_traffic_mask);
2619 atomic_dec(&nic->isr_cnt); 2543 atomic_dec(&nic->isr_cnt);
2620 return 0; 2544 return 0;
2621 2545
@@ -2633,7 +2557,6 @@ no_rx:
2633 atomic_dec(&nic->isr_cnt); 2557 atomic_dec(&nic->isr_cnt);
2634 return 1; 2558 return 1;
2635} 2559}
2636#endif
2637 2560
2638#ifdef CONFIG_NET_POLL_CONTROLLER 2561#ifdef CONFIG_NET_POLL_CONTROLLER
2639/** 2562/**
@@ -2647,10 +2570,10 @@ no_rx:
2647 */ 2570 */
2648static void s2io_netpoll(struct net_device *dev) 2571static void s2io_netpoll(struct net_device *dev)
2649{ 2572{
2650 nic_t *nic = dev->priv; 2573 struct s2io_nic *nic = dev->priv;
2651 mac_info_t *mac_control; 2574 struct mac_info *mac_control;
2652 struct config_param *config; 2575 struct config_param *config;
2653 XENA_dev_config_t __iomem *bar0 = nic->bar0; 2576 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2654 u64 val64 = 0xFFFFFFFFFFFFFFFFULL; 2577 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2655 int i; 2578 int i;
2656 2579
@@ -2699,17 +2622,15 @@ static void s2io_netpoll(struct net_device *dev)
2699 * Return Value: 2622 * Return Value:
2700 * NONE. 2623 * NONE.
2701 */ 2624 */
2702static void rx_intr_handler(ring_info_t *ring_data) 2625static void rx_intr_handler(struct ring_info *ring_data)
2703{ 2626{
2704 nic_t *nic = ring_data->nic; 2627 struct s2io_nic *nic = ring_data->nic;
2705 struct net_device *dev = (struct net_device *) nic->dev; 2628 struct net_device *dev = (struct net_device *) nic->dev;
2706 int get_block, put_block, put_offset; 2629 int get_block, put_block, put_offset;
2707 rx_curr_get_info_t get_info, put_info; 2630 struct rx_curr_get_info get_info, put_info;
2708 RxD_t *rxdp; 2631 struct RxD_t *rxdp;
2709 struct sk_buff *skb; 2632 struct sk_buff *skb;
2710#ifndef CONFIG_S2IO_NAPI
2711 int pkt_cnt = 0; 2633 int pkt_cnt = 0;
2712#endif
2713 int i; 2634 int i;
2714 2635
2715 spin_lock(&nic->rx_lock); 2636 spin_lock(&nic->rx_lock);
@@ -2722,19 +2643,21 @@ static void rx_intr_handler(ring_info_t *ring_data)
2722 2643
2723 get_info = ring_data->rx_curr_get_info; 2644 get_info = ring_data->rx_curr_get_info;
2724 get_block = get_info.block_index; 2645 get_block = get_info.block_index;
2725 put_info = ring_data->rx_curr_put_info; 2646 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2726 put_block = put_info.block_index; 2647 put_block = put_info.block_index;
2727 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr; 2648 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2728#ifndef CONFIG_S2IO_NAPI 2649 if (!napi) {
2729 spin_lock(&nic->put_lock); 2650 spin_lock(&nic->put_lock);
2730 put_offset = ring_data->put_pos; 2651 put_offset = ring_data->put_pos;
2731 spin_unlock(&nic->put_lock); 2652 spin_unlock(&nic->put_lock);
2732#else 2653 } else
2733 put_offset = (put_block * (rxd_count[nic->rxd_mode] + 1)) + 2654 put_offset = ring_data->put_pos;
2734 put_info.offset; 2655
2735#endif
2736 while (RXD_IS_UP2DT(rxdp)) { 2656 while (RXD_IS_UP2DT(rxdp)) {
2737 /* If your are next to put index then it's FIFO full condition */ 2657 /*
2658 * If your are next to put index then it's
2659 * FIFO full condition
2660 */
2738 if ((get_block == put_block) && 2661 if ((get_block == put_block) &&
2739 (get_info.offset + 1) == put_info.offset) { 2662 (get_info.offset + 1) == put_info.offset) {
2740 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name); 2663 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
@@ -2750,7 +2673,7 @@ static void rx_intr_handler(ring_info_t *ring_data)
2750 } 2673 }
2751 if (nic->rxd_mode == RXD_MODE_1) { 2674 if (nic->rxd_mode == RXD_MODE_1) {
2752 pci_unmap_single(nic->pdev, (dma_addr_t) 2675 pci_unmap_single(nic->pdev, (dma_addr_t)
2753 ((RxD1_t*)rxdp)->Buffer0_ptr, 2676 ((struct RxD1*)rxdp)->Buffer0_ptr,
2754 dev->mtu + 2677 dev->mtu +
2755 HEADER_ETHERNET_II_802_3_SIZE + 2678 HEADER_ETHERNET_II_802_3_SIZE +
2756 HEADER_802_2_SIZE + 2679 HEADER_802_2_SIZE +
@@ -2758,22 +2681,22 @@ static void rx_intr_handler(ring_info_t *ring_data)
2758 PCI_DMA_FROMDEVICE); 2681 PCI_DMA_FROMDEVICE);
2759 } else if (nic->rxd_mode == RXD_MODE_3B) { 2682 } else if (nic->rxd_mode == RXD_MODE_3B) {
2760 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t) 2683 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2761 ((RxD3_t*)rxdp)->Buffer0_ptr, 2684 ((struct RxD3*)rxdp)->Buffer0_ptr,
2762 BUF0_LEN, PCI_DMA_FROMDEVICE); 2685 BUF0_LEN, PCI_DMA_FROMDEVICE);
2763 pci_unmap_single(nic->pdev, (dma_addr_t) 2686 pci_unmap_single(nic->pdev, (dma_addr_t)
2764 ((RxD3_t*)rxdp)->Buffer2_ptr, 2687 ((struct RxD3*)rxdp)->Buffer2_ptr,
2765 dev->mtu + 4, 2688 dev->mtu + 4,
2766 PCI_DMA_FROMDEVICE); 2689 PCI_DMA_FROMDEVICE);
2767 } else { 2690 } else {
2768 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t) 2691 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2769 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN, 2692 ((struct RxD3*)rxdp)->Buffer0_ptr, BUF0_LEN,
2770 PCI_DMA_FROMDEVICE); 2693 PCI_DMA_FROMDEVICE);
2771 pci_unmap_single(nic->pdev, (dma_addr_t) 2694 pci_unmap_single(nic->pdev, (dma_addr_t)
2772 ((RxD3_t*)rxdp)->Buffer1_ptr, 2695 ((struct RxD3*)rxdp)->Buffer1_ptr,
2773 l3l4hdr_size + 4, 2696 l3l4hdr_size + 4,
2774 PCI_DMA_FROMDEVICE); 2697 PCI_DMA_FROMDEVICE);
2775 pci_unmap_single(nic->pdev, (dma_addr_t) 2698 pci_unmap_single(nic->pdev, (dma_addr_t)
2776 ((RxD3_t*)rxdp)->Buffer2_ptr, 2699 ((struct RxD3*)rxdp)->Buffer2_ptr,
2777 dev->mtu, PCI_DMA_FROMDEVICE); 2700 dev->mtu, PCI_DMA_FROMDEVICE);
2778 } 2701 }
2779 prefetch(skb->data); 2702 prefetch(skb->data);
@@ -2792,20 +2715,17 @@ static void rx_intr_handler(ring_info_t *ring_data)
2792 rxdp = ring_data->rx_blocks[get_block].block_virt_addr; 2715 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2793 } 2716 }
2794 2717
2795#ifdef CONFIG_S2IO_NAPI
2796 nic->pkts_to_process -= 1; 2718 nic->pkts_to_process -= 1;
2797 if (!nic->pkts_to_process) 2719 if ((napi) && (!nic->pkts_to_process))
2798 break; 2720 break;
2799#else
2800 pkt_cnt++; 2721 pkt_cnt++;
2801 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts)) 2722 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2802 break; 2723 break;
2803#endif
2804 } 2724 }
2805 if (nic->lro) { 2725 if (nic->lro) {
2806 /* Clear all LRO sessions before exiting */ 2726 /* Clear all LRO sessions before exiting */
2807 for (i=0; i<MAX_LRO_SESSIONS; i++) { 2727 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2808 lro_t *lro = &nic->lro0_n[i]; 2728 struct lro *lro = &nic->lro0_n[i];
2809 if (lro->in_use) { 2729 if (lro->in_use) {
2810 update_L3L4_header(nic, lro); 2730 update_L3L4_header(nic, lro);
2811 queue_rx_frame(lro->parent); 2731 queue_rx_frame(lro->parent);
@@ -2829,17 +2749,17 @@ static void rx_intr_handler(ring_info_t *ring_data)
2829 * NONE 2749 * NONE
2830 */ 2750 */
2831 2751
2832static void tx_intr_handler(fifo_info_t *fifo_data) 2752static void tx_intr_handler(struct fifo_info *fifo_data)
2833{ 2753{
2834 nic_t *nic = fifo_data->nic; 2754 struct s2io_nic *nic = fifo_data->nic;
2835 struct net_device *dev = (struct net_device *) nic->dev; 2755 struct net_device *dev = (struct net_device *) nic->dev;
2836 tx_curr_get_info_t get_info, put_info; 2756 struct tx_curr_get_info get_info, put_info;
2837 struct sk_buff *skb; 2757 struct sk_buff *skb;
2838 TxD_t *txdlp; 2758 struct TxD *txdlp;
2839 2759
2840 get_info = fifo_data->tx_curr_get_info; 2760 get_info = fifo_data->tx_curr_get_info;
2841 put_info = fifo_data->tx_curr_put_info; 2761 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
2842 txdlp = (TxD_t *) fifo_data->list_info[get_info.offset]. 2762 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
2843 list_virt_addr; 2763 list_virt_addr;
2844 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) && 2764 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2845 (get_info.offset != put_info.offset) && 2765 (get_info.offset != put_info.offset) &&
@@ -2854,11 +2774,10 @@ static void tx_intr_handler(fifo_info_t *fifo_data)
2854 } 2774 }
2855 if ((err >> 48) == 0xA) { 2775 if ((err >> 48) == 0xA) {
2856 DBG_PRINT(TX_DBG, "TxD returned due \ 2776 DBG_PRINT(TX_DBG, "TxD returned due \
2857to loss of link\n"); 2777 to loss of link\n");
2858 } 2778 }
2859 else { 2779 else {
2860 DBG_PRINT(ERR_DBG, "***TxD error \ 2780 DBG_PRINT(ERR_DBG, "***TxD error %llx\n", err);
2861%llx\n", err);
2862 } 2781 }
2863 } 2782 }
2864 2783
@@ -2877,7 +2796,7 @@ to loss of link\n");
2877 get_info.offset++; 2796 get_info.offset++;
2878 if (get_info.offset == get_info.fifo_len + 1) 2797 if (get_info.offset == get_info.fifo_len + 1)
2879 get_info.offset = 0; 2798 get_info.offset = 0;
2880 txdlp = (TxD_t *) fifo_data->list_info 2799 txdlp = (struct TxD *) fifo_data->list_info
2881 [get_info.offset].list_virt_addr; 2800 [get_info.offset].list_virt_addr;
2882 fifo_data->tx_curr_get_info.offset = 2801 fifo_data->tx_curr_get_info.offset =
2883 get_info.offset; 2802 get_info.offset;
@@ -2902,8 +2821,8 @@ to loss of link\n");
2902static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev) 2821static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2903{ 2822{
2904 u64 val64 = 0x0; 2823 u64 val64 = 0x0;
2905 nic_t *sp = dev->priv; 2824 struct s2io_nic *sp = dev->priv;
2906 XENA_dev_config_t __iomem *bar0 = sp->bar0; 2825 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2907 2826
2908 //address transaction 2827 //address transaction
2909 val64 = val64 | MDIO_MMD_INDX_ADDR(addr) 2828 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
@@ -2951,8 +2870,8 @@ static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2951{ 2870{
2952 u64 val64 = 0x0; 2871 u64 val64 = 0x0;
2953 u64 rval64 = 0x0; 2872 u64 rval64 = 0x0;
2954 nic_t *sp = dev->priv; 2873 struct s2io_nic *sp = dev->priv;
2955 XENA_dev_config_t __iomem *bar0 = sp->bar0; 2874 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2956 2875
2957 /* address transaction */ 2876 /* address transaction */
2958 val64 = val64 | MDIO_MMD_INDX_ADDR(addr) 2877 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
@@ -3055,8 +2974,8 @@ static void s2io_updt_xpak_counter(struct net_device *dev)
3055 u64 val64 = 0x0; 2974 u64 val64 = 0x0;
3056 u64 addr = 0x0; 2975 u64 addr = 0x0;
3057 2976
3058 nic_t *sp = dev->priv; 2977 struct s2io_nic *sp = dev->priv;
3059 StatInfo_t *stat_info = sp->mac_control.stats_info; 2978 struct stat_block *stat_info = sp->mac_control.stats_info;
3060 2979
3061 /* Check the communication with the MDIO slave */ 2980 /* Check the communication with the MDIO slave */
3062 addr = 0x0000; 2981 addr = 0x0000;
@@ -3154,10 +3073,12 @@ static void s2io_updt_xpak_counter(struct net_device *dev)
3154static void alarm_intr_handler(struct s2io_nic *nic) 3073static void alarm_intr_handler(struct s2io_nic *nic)
3155{ 3074{
3156 struct net_device *dev = (struct net_device *) nic->dev; 3075 struct net_device *dev = (struct net_device *) nic->dev;
3157 XENA_dev_config_t __iomem *bar0 = nic->bar0; 3076 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3158 register u64 val64 = 0, err_reg = 0; 3077 register u64 val64 = 0, err_reg = 0;
3159 u64 cnt; 3078 u64 cnt;
3160 int i; 3079 int i;
3080 if (atomic_read(&nic->card_state) == CARD_DOWN)
3081 return;
3161 nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0; 3082 nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3162 /* Handling the XPAK counters update */ 3083 /* Handling the XPAK counters update */
3163 if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) { 3084 if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
@@ -3297,6 +3218,25 @@ static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit)
3297 } 3218 }
3298 return ret; 3219 return ret;
3299} 3220}
3221/*
3222 * check_pci_device_id - Checks if the device id is supported
3223 * @id : device id
3224 * Description: Function to check if the pci device id is supported by driver.
3225 * Return value: Actual device id if supported else PCI_ANY_ID
3226 */
3227static u16 check_pci_device_id(u16 id)
3228{
3229 switch (id) {
3230 case PCI_DEVICE_ID_HERC_WIN:
3231 case PCI_DEVICE_ID_HERC_UNI:
3232 return XFRAME_II_DEVICE;
3233 case PCI_DEVICE_ID_S2IO_UNI:
3234 case PCI_DEVICE_ID_S2IO_WIN:
3235 return XFRAME_I_DEVICE;
3236 default:
3237 return PCI_ANY_ID;
3238 }
3239}
3300 3240
3301/** 3241/**
3302 * s2io_reset - Resets the card. 3242 * s2io_reset - Resets the card.
@@ -3308,42 +3248,57 @@ static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit)
3308 * void. 3248 * void.
3309 */ 3249 */
3310 3250
3311static void s2io_reset(nic_t * sp) 3251static void s2io_reset(struct s2io_nic * sp)
3312{ 3252{
3313 XENA_dev_config_t __iomem *bar0 = sp->bar0; 3253 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3314 u64 val64; 3254 u64 val64;
3315 u16 subid, pci_cmd; 3255 u16 subid, pci_cmd;
3256 int i;
3257 u16 val16;
3258 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3259 __FUNCTION__, sp->dev->name);
3316 3260
3317 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */ 3261 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3318 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd)); 3262 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3319 3263
3264 if (sp->device_type == XFRAME_II_DEVICE) {
3265 int ret;
3266 ret = pci_set_power_state(sp->pdev, 3);
3267 if (!ret)
3268 ret = pci_set_power_state(sp->pdev, 0);
3269 else {
3270 DBG_PRINT(ERR_DBG,"%s PME based SW_Reset failed!\n",
3271 __FUNCTION__);
3272 goto old_way;
3273 }
3274 msleep(20);
3275 goto new_way;
3276 }
3277old_way:
3320 val64 = SW_RESET_ALL; 3278 val64 = SW_RESET_ALL;
3321 writeq(val64, &bar0->sw_reset); 3279 writeq(val64, &bar0->sw_reset);
3322 3280new_way:
3323 /*
3324 * At this stage, if the PCI write is indeed completed, the
3325 * card is reset and so is the PCI Config space of the device.
3326 * So a read cannot be issued at this stage on any of the
3327 * registers to ensure the write into "sw_reset" register
3328 * has gone through.
3329 * Question: Is there any system call that will explicitly force
3330 * all the write commands still pending on the bus to be pushed
3331 * through?
3332 * As of now I'am just giving a 250ms delay and hoping that the
3333 * PCI write to sw_reset register is done by this time.
3334 */
3335 msleep(250);
3336 if (strstr(sp->product_name, "CX4")) { 3281 if (strstr(sp->product_name, "CX4")) {
3337 msleep(750); 3282 msleep(750);
3338 } 3283 }
3284 msleep(250);
3285 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3339 3286
3340 /* Restore the PCI state saved during initialization. */ 3287 /* Restore the PCI state saved during initialization. */
3341 pci_restore_state(sp->pdev); 3288 pci_restore_state(sp->pdev);
3342 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, 3289 pci_read_config_word(sp->pdev, 0x2, &val16);
3343 pci_cmd); 3290 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3344 s2io_init_pci(sp); 3291 break;
3292 msleep(200);
3293 }
3345 3294
3346 msleep(250); 3295 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3296 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3297 }
3298
3299 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3300
3301 s2io_init_pci(sp);
3347 3302
3348 /* Set swapper to enable I/O register access */ 3303 /* Set swapper to enable I/O register access */
3349 s2io_set_swapper(sp); 3304 s2io_set_swapper(sp);
@@ -3399,10 +3354,10 @@ static void s2io_reset(nic_t * sp)
3399 * SUCCESS on success and FAILURE on failure. 3354 * SUCCESS on success and FAILURE on failure.
3400 */ 3355 */
3401 3356
3402static int s2io_set_swapper(nic_t * sp) 3357static int s2io_set_swapper(struct s2io_nic * sp)
3403{ 3358{
3404 struct net_device *dev = sp->dev; 3359 struct net_device *dev = sp->dev;
3405 XENA_dev_config_t __iomem *bar0 = sp->bar0; 3360 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3406 u64 val64, valt, valr; 3361 u64 val64, valt, valr;
3407 3362
3408 /* 3363 /*
@@ -3527,9 +3482,9 @@ static int s2io_set_swapper(nic_t * sp)
3527 return SUCCESS; 3482 return SUCCESS;
3528} 3483}
3529 3484
3530static int wait_for_msix_trans(nic_t *nic, int i) 3485static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3531{ 3486{
3532 XENA_dev_config_t __iomem *bar0 = nic->bar0; 3487 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3533 u64 val64; 3488 u64 val64;
3534 int ret = 0, cnt = 0; 3489 int ret = 0, cnt = 0;
3535 3490
@@ -3548,9 +3503,9 @@ static int wait_for_msix_trans(nic_t *nic, int i)
3548 return ret; 3503 return ret;
3549} 3504}
3550 3505
3551static void restore_xmsi_data(nic_t *nic) 3506static void restore_xmsi_data(struct s2io_nic *nic)
3552{ 3507{
3553 XENA_dev_config_t __iomem *bar0 = nic->bar0; 3508 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3554 u64 val64; 3509 u64 val64;
3555 int i; 3510 int i;
3556 3511
@@ -3566,9 +3521,9 @@ static void restore_xmsi_data(nic_t *nic)
3566 } 3521 }
3567} 3522}
3568 3523
3569static void store_xmsi_data(nic_t *nic) 3524static void store_xmsi_data(struct s2io_nic *nic)
3570{ 3525{
3571 XENA_dev_config_t __iomem *bar0 = nic->bar0; 3526 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3572 u64 val64, addr, data; 3527 u64 val64, addr, data;
3573 int i; 3528 int i;
3574 3529
@@ -3589,9 +3544,9 @@ static void store_xmsi_data(nic_t *nic)
3589 } 3544 }
3590} 3545}
3591 3546
3592int s2io_enable_msi(nic_t *nic) 3547int s2io_enable_msi(struct s2io_nic *nic)
3593{ 3548{
3594 XENA_dev_config_t __iomem *bar0 = nic->bar0; 3549 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3595 u16 msi_ctrl, msg_val; 3550 u16 msi_ctrl, msg_val;
3596 struct config_param *config = &nic->config; 3551 struct config_param *config = &nic->config;
3597 struct net_device *dev = nic->dev; 3552 struct net_device *dev = nic->dev;
@@ -3639,9 +3594,9 @@ int s2io_enable_msi(nic_t *nic)
3639 return 0; 3594 return 0;
3640} 3595}
3641 3596
3642static int s2io_enable_msi_x(nic_t *nic) 3597static int s2io_enable_msi_x(struct s2io_nic *nic)
3643{ 3598{
3644 XENA_dev_config_t __iomem *bar0 = nic->bar0; 3599 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3645 u64 tx_mat, rx_mat; 3600 u64 tx_mat, rx_mat;
3646 u16 msi_control; /* Temp variable */ 3601 u16 msi_control; /* Temp variable */
3647 int ret, i, j, msix_indx = 1; 3602 int ret, i, j, msix_indx = 1;
@@ -3749,7 +3704,7 @@ static int s2io_enable_msi_x(nic_t *nic)
3749 3704
3750static int s2io_open(struct net_device *dev) 3705static int s2io_open(struct net_device *dev)
3751{ 3706{
3752 nic_t *sp = dev->priv; 3707 struct s2io_nic *sp = dev->priv;
3753 int err = 0; 3708 int err = 0;
3754 3709
3755 /* 3710 /*
@@ -3802,7 +3757,7 @@ hw_init_failed:
3802 3757
3803static int s2io_close(struct net_device *dev) 3758static int s2io_close(struct net_device *dev)
3804{ 3759{
3805 nic_t *sp = dev->priv; 3760 struct s2io_nic *sp = dev->priv;
3806 3761
3807 flush_scheduled_work(); 3762 flush_scheduled_work();
3808 netif_stop_queue(dev); 3763 netif_stop_queue(dev);
@@ -3828,15 +3783,15 @@ static int s2io_close(struct net_device *dev)
3828 3783
3829static int s2io_xmit(struct sk_buff *skb, struct net_device *dev) 3784static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3830{ 3785{
3831 nic_t *sp = dev->priv; 3786 struct s2io_nic *sp = dev->priv;
3832 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off; 3787 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3833 register u64 val64; 3788 register u64 val64;
3834 TxD_t *txdp; 3789 struct TxD *txdp;
3835 TxFIFO_element_t __iomem *tx_fifo; 3790 struct TxFIFO_element __iomem *tx_fifo;
3836 unsigned long flags; 3791 unsigned long flags;
3837 u16 vlan_tag = 0; 3792 u16 vlan_tag = 0;
3838 int vlan_priority = 0; 3793 int vlan_priority = 0;
3839 mac_info_t *mac_control; 3794 struct mac_info *mac_control;
3840 struct config_param *config; 3795 struct config_param *config;
3841 int offload_type; 3796 int offload_type;
3842 3797
@@ -3864,7 +3819,7 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3864 3819
3865 put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset; 3820 put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3866 get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset; 3821 get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
3867 txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off]. 3822 txdp = (struct TxD *) mac_control->fifos[queue].list_info[put_off].
3868 list_virt_addr; 3823 list_virt_addr;
3869 3824
3870 queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1; 3825 queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
@@ -3887,12 +3842,10 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3887 } 3842 }
3888 3843
3889 offload_type = s2io_offload_type(skb); 3844 offload_type = s2io_offload_type(skb);
3890#ifdef NETIF_F_TSO
3891 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 3845 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3892 txdp->Control_1 |= TXD_TCP_LSO_EN; 3846 txdp->Control_1 |= TXD_TCP_LSO_EN;
3893 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb)); 3847 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
3894 } 3848 }
3895#endif
3896 if (skb->ip_summed == CHECKSUM_PARTIAL) { 3849 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3897 txdp->Control_2 |= 3850 txdp->Control_2 |=
3898 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN | 3851 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
@@ -3993,13 +3946,13 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3993static void 3946static void
3994s2io_alarm_handle(unsigned long data) 3947s2io_alarm_handle(unsigned long data)
3995{ 3948{
3996 nic_t *sp = (nic_t *)data; 3949 struct s2io_nic *sp = (struct s2io_nic *)data;
3997 3950
3998 alarm_intr_handler(sp); 3951 alarm_intr_handler(sp);
3999 mod_timer(&sp->alarm_timer, jiffies + HZ / 2); 3952 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4000} 3953}
4001 3954
4002static int s2io_chk_rx_buffers(nic_t *sp, int rng_n) 3955static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
4003{ 3956{
4004 int rxb_size, level; 3957 int rxb_size, level;
4005 3958
@@ -4031,9 +3984,9 @@ static int s2io_chk_rx_buffers(nic_t *sp, int rng_n)
4031static irqreturn_t s2io_msi_handle(int irq, void *dev_id) 3984static irqreturn_t s2io_msi_handle(int irq, void *dev_id)
4032{ 3985{
4033 struct net_device *dev = (struct net_device *) dev_id; 3986 struct net_device *dev = (struct net_device *) dev_id;
4034 nic_t *sp = dev->priv; 3987 struct s2io_nic *sp = dev->priv;
4035 int i; 3988 int i;
4036 mac_info_t *mac_control; 3989 struct mac_info *mac_control;
4037 struct config_param *config; 3990 struct config_param *config;
4038 3991
4039 atomic_inc(&sp->isr_cnt); 3992 atomic_inc(&sp->isr_cnt);
@@ -4063,8 +4016,8 @@ static irqreturn_t s2io_msi_handle(int irq, void *dev_id)
4063 4016
4064static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id) 4017static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4065{ 4018{
4066 ring_info_t *ring = (ring_info_t *)dev_id; 4019 struct ring_info *ring = (struct ring_info *)dev_id;
4067 nic_t *sp = ring->nic; 4020 struct s2io_nic *sp = ring->nic;
4068 4021
4069 atomic_inc(&sp->isr_cnt); 4022 atomic_inc(&sp->isr_cnt);
4070 4023
@@ -4077,17 +4030,17 @@ static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4077 4030
4078static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id) 4031static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4079{ 4032{
4080 fifo_info_t *fifo = (fifo_info_t *)dev_id; 4033 struct fifo_info *fifo = (struct fifo_info *)dev_id;
4081 nic_t *sp = fifo->nic; 4034 struct s2io_nic *sp = fifo->nic;
4082 4035
4083 atomic_inc(&sp->isr_cnt); 4036 atomic_inc(&sp->isr_cnt);
4084 tx_intr_handler(fifo); 4037 tx_intr_handler(fifo);
4085 atomic_dec(&sp->isr_cnt); 4038 atomic_dec(&sp->isr_cnt);
4086 return IRQ_HANDLED; 4039 return IRQ_HANDLED;
4087} 4040}
4088static void s2io_txpic_intr_handle(nic_t *sp) 4041static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4089{ 4042{
4090 XENA_dev_config_t __iomem *bar0 = sp->bar0; 4043 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4091 u64 val64; 4044 u64 val64;
4092 4045
4093 val64 = readq(&bar0->pic_int_status); 4046 val64 = readq(&bar0->pic_int_status);
@@ -4109,39 +4062,33 @@ static void s2io_txpic_intr_handle(nic_t *sp)
4109 } 4062 }
4110 else if (val64 & GPIO_INT_REG_LINK_UP) { 4063 else if (val64 & GPIO_INT_REG_LINK_UP) {
4111 val64 = readq(&bar0->adapter_status); 4064 val64 = readq(&bar0->adapter_status);
4112 if (verify_xena_quiescence(sp, val64,
4113 sp->device_enabled_once)) {
4114 /* Enable Adapter */ 4065 /* Enable Adapter */
4115 val64 = readq(&bar0->adapter_control); 4066 val64 = readq(&bar0->adapter_control);
4116 val64 |= ADAPTER_CNTL_EN; 4067 val64 |= ADAPTER_CNTL_EN;
4117 writeq(val64, &bar0->adapter_control); 4068 writeq(val64, &bar0->adapter_control);
4118 val64 |= ADAPTER_LED_ON; 4069 val64 |= ADAPTER_LED_ON;
4119 writeq(val64, &bar0->adapter_control); 4070 writeq(val64, &bar0->adapter_control);
4120 if (!sp->device_enabled_once) 4071 if (!sp->device_enabled_once)
4121 sp->device_enabled_once = 1; 4072 sp->device_enabled_once = 1;
4122 4073
4123 s2io_link(sp, LINK_UP); 4074 s2io_link(sp, LINK_UP);
4124 /* 4075 /*
4125 * unmask link down interrupt and mask link-up 4076 * unmask link down interrupt and mask link-up
4126 * intr 4077 * intr
4127 */ 4078 */
4128 val64 = readq(&bar0->gpio_int_mask); 4079 val64 = readq(&bar0->gpio_int_mask);
4129 val64 &= ~GPIO_INT_MASK_LINK_DOWN; 4080 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4130 val64 |= GPIO_INT_MASK_LINK_UP; 4081 val64 |= GPIO_INT_MASK_LINK_UP;
4131 writeq(val64, &bar0->gpio_int_mask); 4082 writeq(val64, &bar0->gpio_int_mask);
4132 4083
4133 }
4134 }else if (val64 & GPIO_INT_REG_LINK_DOWN) { 4084 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4135 val64 = readq(&bar0->adapter_status); 4085 val64 = readq(&bar0->adapter_status);
4136 if (verify_xena_quiescence(sp, val64, 4086 s2io_link(sp, LINK_DOWN);
4137 sp->device_enabled_once)) { 4087 /* Link is down so unmaks link up interrupt */
4138 s2io_link(sp, LINK_DOWN); 4088 val64 = readq(&bar0->gpio_int_mask);
4139 /* Link is down so unmaks link up interrupt */ 4089 val64 &= ~GPIO_INT_MASK_LINK_UP;
4140 val64 = readq(&bar0->gpio_int_mask); 4090 val64 |= GPIO_INT_MASK_LINK_DOWN;
4141 val64 &= ~GPIO_INT_MASK_LINK_UP; 4091 writeq(val64, &bar0->gpio_int_mask);
4142 val64 |= GPIO_INT_MASK_LINK_DOWN;
4143 writeq(val64, &bar0->gpio_int_mask);
4144 }
4145 } 4092 }
4146 } 4093 }
4147 val64 = readq(&bar0->gpio_int_mask); 4094 val64 = readq(&bar0->gpio_int_mask);
@@ -4163,11 +4110,11 @@ static void s2io_txpic_intr_handle(nic_t *sp)
4163static irqreturn_t s2io_isr(int irq, void *dev_id) 4110static irqreturn_t s2io_isr(int irq, void *dev_id)
4164{ 4111{
4165 struct net_device *dev = (struct net_device *) dev_id; 4112 struct net_device *dev = (struct net_device *) dev_id;
4166 nic_t *sp = dev->priv; 4113 struct s2io_nic *sp = dev->priv;
4167 XENA_dev_config_t __iomem *bar0 = sp->bar0; 4114 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4168 int i; 4115 int i;
4169 u64 reason = 0, val64, org_mask; 4116 u64 reason = 0;
4170 mac_info_t *mac_control; 4117 struct mac_info *mac_control;
4171 struct config_param *config; 4118 struct config_param *config;
4172 4119
4173 atomic_inc(&sp->isr_cnt); 4120 atomic_inc(&sp->isr_cnt);
@@ -4185,43 +4132,48 @@ static irqreturn_t s2io_isr(int irq, void *dev_id)
4185 reason = readq(&bar0->general_int_status); 4132 reason = readq(&bar0->general_int_status);
4186 4133
4187 if (!reason) { 4134 if (!reason) {
4188 /* The interrupt was not raised by Xena. */ 4135 /* The interrupt was not raised by us. */
4136 atomic_dec(&sp->isr_cnt);
4137 return IRQ_NONE;
4138 }
4139 else if (unlikely(reason == S2IO_MINUS_ONE) ) {
4140 /* Disable device and get out */
4189 atomic_dec(&sp->isr_cnt); 4141 atomic_dec(&sp->isr_cnt);
4190 return IRQ_NONE; 4142 return IRQ_NONE;
4191 } 4143 }
4192 4144
4193 val64 = 0xFFFFFFFFFFFFFFFFULL; 4145 if (napi) {
4194 /* Store current mask before masking all interrupts */ 4146 if (reason & GEN_INTR_RXTRAFFIC) {
4195 org_mask = readq(&bar0->general_int_mask); 4147 if ( likely ( netif_rx_schedule_prep(dev)) ) {
4196 writeq(val64, &bar0->general_int_mask); 4148 __netif_rx_schedule(dev);
4149 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4150 }
4151 else
4152 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4153 }
4154 } else {
4155 /*
4156 * Rx handler is called by default, without checking for the
4157 * cause of interrupt.
4158 * rx_traffic_int reg is an R1 register, writing all 1's
4159 * will ensure that the actual interrupt causing bit get's
4160 * cleared and hence a read can be avoided.
4161 */
4162 if (reason & GEN_INTR_RXTRAFFIC)
4163 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4197 4164
4198#ifdef CONFIG_S2IO_NAPI 4165 for (i = 0; i < config->rx_ring_num; i++) {
4199 if (reason & GEN_INTR_RXTRAFFIC) { 4166 rx_intr_handler(&mac_control->rings[i]);
4200 if (netif_rx_schedule_prep(dev)) {
4201 writeq(val64, &bar0->rx_traffic_mask);
4202 __netif_rx_schedule(dev);
4203 } 4167 }
4204 } 4168 }
4205#else
4206 /*
4207 * Rx handler is called by default, without checking for the
4208 * cause of interrupt.
4209 * rx_traffic_int reg is an R1 register, writing all 1's
4210 * will ensure that the actual interrupt causing bit get's
4211 * cleared and hence a read can be avoided.
4212 */
4213 writeq(val64, &bar0->rx_traffic_int);
4214 for (i = 0; i < config->rx_ring_num; i++) {
4215 rx_intr_handler(&mac_control->rings[i]);
4216 }
4217#endif
4218 4169
4219 /* 4170 /*
4220 * tx_traffic_int reg is an R1 register, writing all 1's 4171 * tx_traffic_int reg is an R1 register, writing all 1's
4221 * will ensure that the actual interrupt causing bit get's 4172 * will ensure that the actual interrupt causing bit get's
4222 * cleared and hence a read can be avoided. 4173 * cleared and hence a read can be avoided.
4223 */ 4174 */
4224 writeq(val64, &bar0->tx_traffic_int); 4175 if (reason & GEN_INTR_TXTRAFFIC)
4176 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4225 4177
4226 for (i = 0; i < config->tx_fifo_num; i++) 4178 for (i = 0; i < config->tx_fifo_num; i++)
4227 tx_intr_handler(&mac_control->fifos[i]); 4179 tx_intr_handler(&mac_control->fifos[i]);
@@ -4233,11 +4185,14 @@ static irqreturn_t s2io_isr(int irq, void *dev_id)
4233 * reallocate the buffers from the interrupt handler itself, 4185 * reallocate the buffers from the interrupt handler itself,
4234 * else schedule a tasklet to reallocate the buffers. 4186 * else schedule a tasklet to reallocate the buffers.
4235 */ 4187 */
4236#ifndef CONFIG_S2IO_NAPI 4188 if (!napi) {
4237 for (i = 0; i < config->rx_ring_num; i++) 4189 for (i = 0; i < config->rx_ring_num; i++)
4238 s2io_chk_rx_buffers(sp, i); 4190 s2io_chk_rx_buffers(sp, i);
4239#endif 4191 }
4240 writeq(org_mask, &bar0->general_int_mask); 4192
4193 writeq(0, &bar0->general_int_mask);
4194 readl(&bar0->general_int_status);
4195
4241 atomic_dec(&sp->isr_cnt); 4196 atomic_dec(&sp->isr_cnt);
4242 return IRQ_HANDLED; 4197 return IRQ_HANDLED;
4243} 4198}
@@ -4245,9 +4200,9 @@ static irqreturn_t s2io_isr(int irq, void *dev_id)
4245/** 4200/**
4246 * s2io_updt_stats - 4201 * s2io_updt_stats -
4247 */ 4202 */
4248static void s2io_updt_stats(nic_t *sp) 4203static void s2io_updt_stats(struct s2io_nic *sp)
4249{ 4204{
4250 XENA_dev_config_t __iomem *bar0 = sp->bar0; 4205 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4251 u64 val64; 4206 u64 val64;
4252 int cnt = 0; 4207 int cnt = 0;
4253 4208
@@ -4266,7 +4221,7 @@ static void s2io_updt_stats(nic_t *sp)
4266 break; /* Updt failed */ 4221 break; /* Updt failed */
4267 } while(1); 4222 } while(1);
4268 } else { 4223 } else {
4269 memset(sp->mac_control.stats_info, 0, sizeof(StatInfo_t)); 4224 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
4270 } 4225 }
4271} 4226}
4272 4227
@@ -4282,8 +4237,8 @@ static void s2io_updt_stats(nic_t *sp)
4282 4237
4283static struct net_device_stats *s2io_get_stats(struct net_device *dev) 4238static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4284{ 4239{
4285 nic_t *sp = dev->priv; 4240 struct s2io_nic *sp = dev->priv;
4286 mac_info_t *mac_control; 4241 struct mac_info *mac_control;
4287 struct config_param *config; 4242 struct config_param *config;
4288 4243
4289 4244
@@ -4324,8 +4279,8 @@ static void s2io_set_multicast(struct net_device *dev)
4324{ 4279{
4325 int i, j, prev_cnt; 4280 int i, j, prev_cnt;
4326 struct dev_mc_list *mclist; 4281 struct dev_mc_list *mclist;
4327 nic_t *sp = dev->priv; 4282 struct s2io_nic *sp = dev->priv;
4328 XENA_dev_config_t __iomem *bar0 = sp->bar0; 4283 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4329 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask = 4284 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4330 0xfeffffffffffULL; 4285 0xfeffffffffffULL;
4331 u64 dis_addr = 0xffffffffffffULL, mac_addr = 0; 4286 u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
@@ -4478,8 +4433,8 @@ static void s2io_set_multicast(struct net_device *dev)
4478 4433
4479static int s2io_set_mac_addr(struct net_device *dev, u8 * addr) 4434static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4480{ 4435{
4481 nic_t *sp = dev->priv; 4436 struct s2io_nic *sp = dev->priv;
4482 XENA_dev_config_t __iomem *bar0 = sp->bar0; 4437 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4483 register u64 val64, mac_addr = 0; 4438 register u64 val64, mac_addr = 0;
4484 int i; 4439 int i;
4485 4440
@@ -4525,7 +4480,7 @@ static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4525static int s2io_ethtool_sset(struct net_device *dev, 4480static int s2io_ethtool_sset(struct net_device *dev,
4526 struct ethtool_cmd *info) 4481 struct ethtool_cmd *info)
4527{ 4482{
4528 nic_t *sp = dev->priv; 4483 struct s2io_nic *sp = dev->priv;
4529 if ((info->autoneg == AUTONEG_ENABLE) || 4484 if ((info->autoneg == AUTONEG_ENABLE) ||
4530 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL)) 4485 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4531 return -EINVAL; 4486 return -EINVAL;
@@ -4551,7 +4506,7 @@ static int s2io_ethtool_sset(struct net_device *dev,
4551 4506
4552static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info) 4507static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4553{ 4508{
4554 nic_t *sp = dev->priv; 4509 struct s2io_nic *sp = dev->priv;
4555 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE); 4510 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4556 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE); 4511 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4557 info->port = PORT_FIBRE; 4512 info->port = PORT_FIBRE;
@@ -4584,7 +4539,7 @@ static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4584static void s2io_ethtool_gdrvinfo(struct net_device *dev, 4539static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4585 struct ethtool_drvinfo *info) 4540 struct ethtool_drvinfo *info)
4586{ 4541{
4587 nic_t *sp = dev->priv; 4542 struct s2io_nic *sp = dev->priv;
4588 4543
4589 strncpy(info->driver, s2io_driver_name, sizeof(info->driver)); 4544 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4590 strncpy(info->version, s2io_driver_version, sizeof(info->version)); 4545 strncpy(info->version, s2io_driver_version, sizeof(info->version));
@@ -4616,7 +4571,7 @@ static void s2io_ethtool_gregs(struct net_device *dev,
4616 int i; 4571 int i;
4617 u64 reg; 4572 u64 reg;
4618 u8 *reg_space = (u8 *) space; 4573 u8 *reg_space = (u8 *) space;
4619 nic_t *sp = dev->priv; 4574 struct s2io_nic *sp = dev->priv;
4620 4575
4621 regs->len = XENA_REG_SPACE; 4576 regs->len = XENA_REG_SPACE;
4622 regs->version = sp->pdev->subsystem_device; 4577 regs->version = sp->pdev->subsystem_device;
@@ -4638,8 +4593,8 @@ static void s2io_ethtool_gregs(struct net_device *dev,
4638*/ 4593*/
4639static void s2io_phy_id(unsigned long data) 4594static void s2io_phy_id(unsigned long data)
4640{ 4595{
4641 nic_t *sp = (nic_t *) data; 4596 struct s2io_nic *sp = (struct s2io_nic *) data;
4642 XENA_dev_config_t __iomem *bar0 = sp->bar0; 4597 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4643 u64 val64 = 0; 4598 u64 val64 = 0;
4644 u16 subid; 4599 u16 subid;
4645 4600
@@ -4676,8 +4631,8 @@ static void s2io_phy_id(unsigned long data)
4676static int s2io_ethtool_idnic(struct net_device *dev, u32 data) 4631static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4677{ 4632{
4678 u64 val64 = 0, last_gpio_ctrl_val; 4633 u64 val64 = 0, last_gpio_ctrl_val;
4679 nic_t *sp = dev->priv; 4634 struct s2io_nic *sp = dev->priv;
4680 XENA_dev_config_t __iomem *bar0 = sp->bar0; 4635 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4681 u16 subid; 4636 u16 subid;
4682 4637
4683 subid = sp->pdev->subsystem_device; 4638 subid = sp->pdev->subsystem_device;
@@ -4725,8 +4680,8 @@ static void s2io_ethtool_getpause_data(struct net_device *dev,
4725 struct ethtool_pauseparam *ep) 4680 struct ethtool_pauseparam *ep)
4726{ 4681{
4727 u64 val64; 4682 u64 val64;
4728 nic_t *sp = dev->priv; 4683 struct s2io_nic *sp = dev->priv;
4729 XENA_dev_config_t __iomem *bar0 = sp->bar0; 4684 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4730 4685
4731 val64 = readq(&bar0->rmac_pause_cfg); 4686 val64 = readq(&bar0->rmac_pause_cfg);
4732 if (val64 & RMAC_PAUSE_GEN_ENABLE) 4687 if (val64 & RMAC_PAUSE_GEN_ENABLE)
@@ -4752,8 +4707,8 @@ static int s2io_ethtool_setpause_data(struct net_device *dev,
4752 struct ethtool_pauseparam *ep) 4707 struct ethtool_pauseparam *ep)
4753{ 4708{
4754 u64 val64; 4709 u64 val64;
4755 nic_t *sp = dev->priv; 4710 struct s2io_nic *sp = dev->priv;
4756 XENA_dev_config_t __iomem *bar0 = sp->bar0; 4711 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4757 4712
4758 val64 = readq(&bar0->rmac_pause_cfg); 4713 val64 = readq(&bar0->rmac_pause_cfg);
4759 if (ep->tx_pause) 4714 if (ep->tx_pause)
@@ -4785,12 +4740,12 @@ static int s2io_ethtool_setpause_data(struct net_device *dev,
4785 */ 4740 */
4786 4741
4787#define S2IO_DEV_ID 5 4742#define S2IO_DEV_ID 5
4788static int read_eeprom(nic_t * sp, int off, u64 * data) 4743static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
4789{ 4744{
4790 int ret = -1; 4745 int ret = -1;
4791 u32 exit_cnt = 0; 4746 u32 exit_cnt = 0;
4792 u64 val64; 4747 u64 val64;
4793 XENA_dev_config_t __iomem *bar0 = sp->bar0; 4748 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4794 4749
4795 if (sp->device_type == XFRAME_I_DEVICE) { 4750 if (sp->device_type == XFRAME_I_DEVICE) {
4796 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) | 4751 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
@@ -4850,11 +4805,11 @@ static int read_eeprom(nic_t * sp, int off, u64 * data)
4850 * 0 on success, -1 on failure. 4805 * 0 on success, -1 on failure.
4851 */ 4806 */
4852 4807
4853static int write_eeprom(nic_t * sp, int off, u64 data, int cnt) 4808static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
4854{ 4809{
4855 int exit_cnt = 0, ret = -1; 4810 int exit_cnt = 0, ret = -1;
4856 u64 val64; 4811 u64 val64;
4857 XENA_dev_config_t __iomem *bar0 = sp->bar0; 4812 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4858 4813
4859 if (sp->device_type == XFRAME_I_DEVICE) { 4814 if (sp->device_type == XFRAME_I_DEVICE) {
4860 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) | 4815 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
@@ -4899,7 +4854,7 @@ static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
4899 } 4854 }
4900 return ret; 4855 return ret;
4901} 4856}
4902static void s2io_vpd_read(nic_t *nic) 4857static void s2io_vpd_read(struct s2io_nic *nic)
4903{ 4858{
4904 u8 *vpd_data; 4859 u8 *vpd_data;
4905 u8 data; 4860 u8 data;
@@ -4914,6 +4869,7 @@ static void s2io_vpd_read(nic_t *nic)
4914 strcpy(nic->product_name, "Xframe I 10GbE network adapter"); 4869 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
4915 vpd_addr = 0x50; 4870 vpd_addr = 0x50;
4916 } 4871 }
4872 strcpy(nic->serial_num, "NOT AVAILABLE");
4917 4873
4918 vpd_data = kmalloc(256, GFP_KERNEL); 4874 vpd_data = kmalloc(256, GFP_KERNEL);
4919 if (!vpd_data) 4875 if (!vpd_data)
@@ -4937,7 +4893,22 @@ static void s2io_vpd_read(nic_t *nic)
4937 pci_read_config_dword(nic->pdev, (vpd_addr + 4), 4893 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
4938 (u32 *)&vpd_data[i]); 4894 (u32 *)&vpd_data[i]);
4939 } 4895 }
4940 if ((!fail) && (vpd_data[1] < VPD_PRODUCT_NAME_LEN)) { 4896
4897 if(!fail) {
4898 /* read serial number of adapter */
4899 for (cnt = 0; cnt < 256; cnt++) {
4900 if ((vpd_data[cnt] == 'S') &&
4901 (vpd_data[cnt+1] == 'N') &&
4902 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
4903 memset(nic->serial_num, 0, VPD_STRING_LEN);
4904 memcpy(nic->serial_num, &vpd_data[cnt + 3],
4905 vpd_data[cnt+2]);
4906 break;
4907 }
4908 }
4909 }
4910
4911 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
4941 memset(nic->product_name, 0, vpd_data[1]); 4912 memset(nic->product_name, 0, vpd_data[1]);
4942 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]); 4913 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
4943 } 4914 }
@@ -4962,7 +4933,7 @@ static int s2io_ethtool_geeprom(struct net_device *dev,
4962{ 4933{
4963 u32 i, valid; 4934 u32 i, valid;
4964 u64 data; 4935 u64 data;
4965 nic_t *sp = dev->priv; 4936 struct s2io_nic *sp = dev->priv;
4966 4937
4967 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16); 4938 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
4968 4939
@@ -5000,7 +4971,7 @@ static int s2io_ethtool_seeprom(struct net_device *dev,
5000{ 4971{
5001 int len = eeprom->len, cnt = 0; 4972 int len = eeprom->len, cnt = 0;
5002 u64 valid = 0, data; 4973 u64 valid = 0, data;
5003 nic_t *sp = dev->priv; 4974 struct s2io_nic *sp = dev->priv;
5004 4975
5005 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) { 4976 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5006 DBG_PRINT(ERR_DBG, 4977 DBG_PRINT(ERR_DBG,
@@ -5044,9 +5015,9 @@ static int s2io_ethtool_seeprom(struct net_device *dev,
5044 * 0 on success. 5015 * 0 on success.
5045 */ 5016 */
5046 5017
5047static int s2io_register_test(nic_t * sp, uint64_t * data) 5018static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
5048{ 5019{
5049 XENA_dev_config_t __iomem *bar0 = sp->bar0; 5020 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5050 u64 val64 = 0, exp_val; 5021 u64 val64 = 0, exp_val;
5051 int fail = 0; 5022 int fail = 0;
5052 5023
@@ -5111,7 +5082,7 @@ static int s2io_register_test(nic_t * sp, uint64_t * data)
5111 * 0 on success. 5082 * 0 on success.
5112 */ 5083 */
5113 5084
5114static int s2io_eeprom_test(nic_t * sp, uint64_t * data) 5085static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
5115{ 5086{
5116 int fail = 0; 5087 int fail = 0;
5117 u64 ret_data, org_4F0, org_7F0; 5088 u64 ret_data, org_4F0, org_7F0;
@@ -5213,7 +5184,7 @@ static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
5213 * 0 on success and -1 on failure. 5184 * 0 on success and -1 on failure.
5214 */ 5185 */
5215 5186
5216static int s2io_bist_test(nic_t * sp, uint64_t * data) 5187static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
5217{ 5188{
5218 u8 bist = 0; 5189 u8 bist = 0;
5219 int cnt = 0, ret = -1; 5190 int cnt = 0, ret = -1;
@@ -5249,9 +5220,9 @@ static int s2io_bist_test(nic_t * sp, uint64_t * data)
5249 * 0 on success. 5220 * 0 on success.
5250 */ 5221 */
5251 5222
5252static int s2io_link_test(nic_t * sp, uint64_t * data) 5223static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
5253{ 5224{
5254 XENA_dev_config_t __iomem *bar0 = sp->bar0; 5225 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5255 u64 val64; 5226 u64 val64;
5256 5227
5257 val64 = readq(&bar0->adapter_status); 5228 val64 = readq(&bar0->adapter_status);
@@ -5276,9 +5247,9 @@ static int s2io_link_test(nic_t * sp, uint64_t * data)
5276 * 0 on success. 5247 * 0 on success.
5277 */ 5248 */
5278 5249
5279static int s2io_rldram_test(nic_t * sp, uint64_t * data) 5250static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
5280{ 5251{
5281 XENA_dev_config_t __iomem *bar0 = sp->bar0; 5252 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5282 u64 val64; 5253 u64 val64;
5283 int cnt, iteration = 0, test_fail = 0; 5254 int cnt, iteration = 0, test_fail = 0;
5284 5255
@@ -5380,7 +5351,7 @@ static void s2io_ethtool_test(struct net_device *dev,
5380 struct ethtool_test *ethtest, 5351 struct ethtool_test *ethtest,
5381 uint64_t * data) 5352 uint64_t * data)
5382{ 5353{
5383 nic_t *sp = dev->priv; 5354 struct s2io_nic *sp = dev->priv;
5384 int orig_state = netif_running(sp->dev); 5355 int orig_state = netif_running(sp->dev);
5385 5356
5386 if (ethtest->flags == ETH_TEST_FL_OFFLINE) { 5357 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
@@ -5436,8 +5407,8 @@ static void s2io_get_ethtool_stats(struct net_device *dev,
5436 u64 * tmp_stats) 5407 u64 * tmp_stats)
5437{ 5408{
5438 int i = 0; 5409 int i = 0;
5439 nic_t *sp = dev->priv; 5410 struct s2io_nic *sp = dev->priv;
5440 StatInfo_t *stat_info = sp->mac_control.stats_info; 5411 struct stat_block *stat_info = sp->mac_control.stats_info;
5441 5412
5442 s2io_updt_stats(sp); 5413 s2io_updt_stats(sp);
5443 tmp_stats[i++] = 5414 tmp_stats[i++] =
@@ -5664,14 +5635,14 @@ static int s2io_ethtool_get_regs_len(struct net_device *dev)
5664 5635
5665static u32 s2io_ethtool_get_rx_csum(struct net_device * dev) 5636static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
5666{ 5637{
5667 nic_t *sp = dev->priv; 5638 struct s2io_nic *sp = dev->priv;
5668 5639
5669 return (sp->rx_csum); 5640 return (sp->rx_csum);
5670} 5641}
5671 5642
5672static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data) 5643static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
5673{ 5644{
5674 nic_t *sp = dev->priv; 5645 struct s2io_nic *sp = dev->priv;
5675 5646
5676 if (data) 5647 if (data)
5677 sp->rx_csum = 1; 5648 sp->rx_csum = 1;
@@ -5750,10 +5721,8 @@ static const struct ethtool_ops netdev_ethtool_ops = {
5750 .set_tx_csum = s2io_ethtool_op_set_tx_csum, 5721 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5751 .get_sg = ethtool_op_get_sg, 5722 .get_sg = ethtool_op_get_sg,
5752 .set_sg = ethtool_op_set_sg, 5723 .set_sg = ethtool_op_set_sg,
5753#ifdef NETIF_F_TSO
5754 .get_tso = s2io_ethtool_op_get_tso, 5724 .get_tso = s2io_ethtool_op_get_tso,
5755 .set_tso = s2io_ethtool_op_set_tso, 5725 .set_tso = s2io_ethtool_op_set_tso,
5756#endif
5757 .get_ufo = ethtool_op_get_ufo, 5726 .get_ufo = ethtool_op_get_ufo,
5758 .set_ufo = ethtool_op_set_ufo, 5727 .set_ufo = ethtool_op_set_ufo,
5759 .self_test_count = s2io_ethtool_self_test_count, 5728 .self_test_count = s2io_ethtool_self_test_count,
@@ -5794,7 +5763,7 @@ static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5794 5763
5795static int s2io_change_mtu(struct net_device *dev, int new_mtu) 5764static int s2io_change_mtu(struct net_device *dev, int new_mtu)
5796{ 5765{
5797 nic_t *sp = dev->priv; 5766 struct s2io_nic *sp = dev->priv;
5798 5767
5799 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) { 5768 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
5800 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", 5769 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
@@ -5813,7 +5782,7 @@ static int s2io_change_mtu(struct net_device *dev, int new_mtu)
5813 if (netif_queue_stopped(dev)) 5782 if (netif_queue_stopped(dev))
5814 netif_wake_queue(dev); 5783 netif_wake_queue(dev);
5815 } else { /* Device is down */ 5784 } else { /* Device is down */
5816 XENA_dev_config_t __iomem *bar0 = sp->bar0; 5785 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5817 u64 val64 = new_mtu; 5786 u64 val64 = new_mtu;
5818 5787
5819 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); 5788 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
@@ -5838,9 +5807,9 @@ static int s2io_change_mtu(struct net_device *dev, int new_mtu)
5838static void s2io_tasklet(unsigned long dev_addr) 5807static void s2io_tasklet(unsigned long dev_addr)
5839{ 5808{
5840 struct net_device *dev = (struct net_device *) dev_addr; 5809 struct net_device *dev = (struct net_device *) dev_addr;
5841 nic_t *sp = dev->priv; 5810 struct s2io_nic *sp = dev->priv;
5842 int i, ret; 5811 int i, ret;
5843 mac_info_t *mac_control; 5812 struct mac_info *mac_control;
5844 struct config_param *config; 5813 struct config_param *config;
5845 5814
5846 mac_control = &sp->mac_control; 5815 mac_control = &sp->mac_control;
@@ -5873,9 +5842,9 @@ static void s2io_tasklet(unsigned long dev_addr)
5873 5842
5874static void s2io_set_link(struct work_struct *work) 5843static void s2io_set_link(struct work_struct *work)
5875{ 5844{
5876 nic_t *nic = container_of(work, nic_t, set_link_task); 5845 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
5877 struct net_device *dev = nic->dev; 5846 struct net_device *dev = nic->dev;
5878 XENA_dev_config_t __iomem *bar0 = nic->bar0; 5847 struct XENA_dev_config __iomem *bar0 = nic->bar0;
5879 register u64 val64; 5848 register u64 val64;
5880 u16 subid; 5849 u16 subid;
5881 5850
@@ -5894,57 +5863,53 @@ static void s2io_set_link(struct work_struct *work)
5894 } 5863 }
5895 5864
5896 val64 = readq(&bar0->adapter_status); 5865 val64 = readq(&bar0->adapter_status);
5897 if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) { 5866 if (LINK_IS_UP(val64)) {
5898 if (LINK_IS_UP(val64)) { 5867 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
5899 val64 = readq(&bar0->adapter_control); 5868 if (verify_xena_quiescence(nic)) {
5900 val64 |= ADAPTER_CNTL_EN; 5869 val64 = readq(&bar0->adapter_control);
5901 writeq(val64, &bar0->adapter_control); 5870 val64 |= ADAPTER_CNTL_EN;
5902 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5903 subid)) {
5904 val64 = readq(&bar0->gpio_control);
5905 val64 |= GPIO_CTRL_GPIO_0;
5906 writeq(val64, &bar0->gpio_control);
5907 val64 = readq(&bar0->gpio_control);
5908 } else {
5909 val64 |= ADAPTER_LED_ON;
5910 writeq(val64, &bar0->adapter_control); 5871 writeq(val64, &bar0->adapter_control);
5911 } 5872 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
5912 if (s2io_link_fault_indication(nic) == 5873 nic->device_type, subid)) {
5913 MAC_RMAC_ERR_TIMER) { 5874 val64 = readq(&bar0->gpio_control);
5914 val64 = readq(&bar0->adapter_status); 5875 val64 |= GPIO_CTRL_GPIO_0;
5915 if (!LINK_IS_UP(val64)) { 5876 writeq(val64, &bar0->gpio_control);
5916 DBG_PRINT(ERR_DBG, "%s:", dev->name); 5877 val64 = readq(&bar0->gpio_control);
5917 DBG_PRINT(ERR_DBG, " Link down"); 5878 } else {
5918 DBG_PRINT(ERR_DBG, "after "); 5879 val64 |= ADAPTER_LED_ON;
5919 DBG_PRINT(ERR_DBG, "enabling "); 5880 writeq(val64, &bar0->adapter_control);
5920 DBG_PRINT(ERR_DBG, "device \n");
5921 } 5881 }
5922 }
5923 if (nic->device_enabled_once == FALSE) {
5924 nic->device_enabled_once = TRUE; 5882 nic->device_enabled_once = TRUE;
5883 } else {
5884 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
5885 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
5886 netif_stop_queue(dev);
5925 } 5887 }
5888 }
5889 val64 = readq(&bar0->adapter_status);
5890 if (!LINK_IS_UP(val64)) {
5891 DBG_PRINT(ERR_DBG, "%s:", dev->name);
5892 DBG_PRINT(ERR_DBG, " Link down after enabling ");
5893 DBG_PRINT(ERR_DBG, "device \n");
5894 } else
5926 s2io_link(nic, LINK_UP); 5895 s2io_link(nic, LINK_UP);
5927 } else { 5896 } else {
5928 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type, 5897 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5929 subid)) { 5898 subid)) {
5930 val64 = readq(&bar0->gpio_control); 5899 val64 = readq(&bar0->gpio_control);
5931 val64 &= ~GPIO_CTRL_GPIO_0; 5900 val64 &= ~GPIO_CTRL_GPIO_0;
5932 writeq(val64, &bar0->gpio_control); 5901 writeq(val64, &bar0->gpio_control);
5933 val64 = readq(&bar0->gpio_control); 5902 val64 = readq(&bar0->gpio_control);
5934 }
5935 s2io_link(nic, LINK_DOWN);
5936 } 5903 }
5937 } else { /* NIC is not Quiescent. */ 5904 s2io_link(nic, LINK_DOWN);
5938 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
5939 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
5940 netif_stop_queue(dev);
5941 } 5905 }
5942 clear_bit(0, &(nic->link_state)); 5906 clear_bit(0, &(nic->link_state));
5943} 5907}
5944 5908
5945static int set_rxd_buffer_pointer(nic_t *sp, RxD_t *rxdp, buffAdd_t *ba, 5909static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
5946 struct sk_buff **skb, u64 *temp0, u64 *temp1, 5910 struct buffAdd *ba,
5947 u64 *temp2, int size) 5911 struct sk_buff **skb, u64 *temp0, u64 *temp1,
5912 u64 *temp2, int size)
5948{ 5913{
5949 struct net_device *dev = sp->dev; 5914 struct net_device *dev = sp->dev;
5950 struct sk_buff *frag_list; 5915 struct sk_buff *frag_list;
@@ -5958,7 +5923,7 @@ static int set_rxd_buffer_pointer(nic_t *sp, RxD_t *rxdp, buffAdd_t *ba,
5958 * using same mapped address for the Rxd 5923 * using same mapped address for the Rxd
5959 * buffer pointer 5924 * buffer pointer
5960 */ 5925 */
5961 ((RxD1_t*)rxdp)->Buffer0_ptr = *temp0; 5926 ((struct RxD1*)rxdp)->Buffer0_ptr = *temp0;
5962 } else { 5927 } else {
5963 *skb = dev_alloc_skb(size); 5928 *skb = dev_alloc_skb(size);
5964 if (!(*skb)) { 5929 if (!(*skb)) {
@@ -5970,7 +5935,7 @@ static int set_rxd_buffer_pointer(nic_t *sp, RxD_t *rxdp, buffAdd_t *ba,
5970 * such it will be used for next rxd whose 5935 * such it will be used for next rxd whose
5971 * Host Control is NULL 5936 * Host Control is NULL
5972 */ 5937 */
5973 ((RxD1_t*)rxdp)->Buffer0_ptr = *temp0 = 5938 ((struct RxD1*)rxdp)->Buffer0_ptr = *temp0 =
5974 pci_map_single( sp->pdev, (*skb)->data, 5939 pci_map_single( sp->pdev, (*skb)->data,
5975 size - NET_IP_ALIGN, 5940 size - NET_IP_ALIGN,
5976 PCI_DMA_FROMDEVICE); 5941 PCI_DMA_FROMDEVICE);
@@ -5979,36 +5944,36 @@ static int set_rxd_buffer_pointer(nic_t *sp, RxD_t *rxdp, buffAdd_t *ba,
5979 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) { 5944 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
5980 /* Two buffer Mode */ 5945 /* Two buffer Mode */
5981 if (*skb) { 5946 if (*skb) {
5982 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2; 5947 ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2;
5983 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0; 5948 ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0;
5984 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1; 5949 ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1;
5985 } else { 5950 } else {
5986 *skb = dev_alloc_skb(size); 5951 *skb = dev_alloc_skb(size);
5987 if (!(*skb)) { 5952 if (!(*skb)) {
5988 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n", 5953 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n",
5989 dev->name); 5954 dev->name);
5990 return -ENOMEM; 5955 return -ENOMEM;
5991 } 5956 }
5992 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 = 5957 ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2 =
5993 pci_map_single(sp->pdev, (*skb)->data, 5958 pci_map_single(sp->pdev, (*skb)->data,
5994 dev->mtu + 4, 5959 dev->mtu + 4,
5995 PCI_DMA_FROMDEVICE); 5960 PCI_DMA_FROMDEVICE);
5996 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0 = 5961 ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0 =
5997 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN, 5962 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
5998 PCI_DMA_FROMDEVICE); 5963 PCI_DMA_FROMDEVICE);
5999 rxdp->Host_Control = (unsigned long) (*skb); 5964 rxdp->Host_Control = (unsigned long) (*skb);
6000 5965
6001 /* Buffer-1 will be dummy buffer not used */ 5966 /* Buffer-1 will be dummy buffer not used */
6002 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1 = 5967 ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1 =
6003 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN, 5968 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6004 PCI_DMA_FROMDEVICE); 5969 PCI_DMA_FROMDEVICE);
6005 } 5970 }
6006 } else if ((rxdp->Host_Control == 0)) { 5971 } else if ((rxdp->Host_Control == 0)) {
6007 /* Three buffer mode */ 5972 /* Three buffer mode */
6008 if (*skb) { 5973 if (*skb) {
6009 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0; 5974 ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0;
6010 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1; 5975 ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1;
6011 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2; 5976 ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2;
6012 } else { 5977 } else {
6013 *skb = dev_alloc_skb(size); 5978 *skb = dev_alloc_skb(size);
6014 if (!(*skb)) { 5979 if (!(*skb)) {
@@ -6016,11 +5981,11 @@ static int set_rxd_buffer_pointer(nic_t *sp, RxD_t *rxdp, buffAdd_t *ba,
6016 dev->name); 5981 dev->name);
6017 return -ENOMEM; 5982 return -ENOMEM;
6018 } 5983 }
6019 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0 = 5984 ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0 =
6020 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN, 5985 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6021 PCI_DMA_FROMDEVICE); 5986 PCI_DMA_FROMDEVICE);
6022 /* Buffer-1 receives L3/L4 headers */ 5987 /* Buffer-1 receives L3/L4 headers */
6023 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1 = 5988 ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1 =
6024 pci_map_single( sp->pdev, (*skb)->data, 5989 pci_map_single( sp->pdev, (*skb)->data,
6025 l3l4hdr_size + 4, 5990 l3l4hdr_size + 4,
6026 PCI_DMA_FROMDEVICE); 5991 PCI_DMA_FROMDEVICE);
@@ -6040,14 +6005,15 @@ static int set_rxd_buffer_pointer(nic_t *sp, RxD_t *rxdp, buffAdd_t *ba,
6040 /* 6005 /*
6041 * Buffer-2 receives L4 data payload 6006 * Buffer-2 receives L4 data payload
6042 */ 6007 */
6043 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 = 6008 ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2 =
6044 pci_map_single( sp->pdev, frag_list->data, 6009 pci_map_single( sp->pdev, frag_list->data,
6045 dev->mtu, PCI_DMA_FROMDEVICE); 6010 dev->mtu, PCI_DMA_FROMDEVICE);
6046 } 6011 }
6047 } 6012 }
6048 return 0; 6013 return 0;
6049} 6014}
6050static void set_rxd_buffer_size(nic_t *sp, RxD_t *rxdp, int size) 6015static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6016 int size)
6051{ 6017{
6052 struct net_device *dev = sp->dev; 6018 struct net_device *dev = sp->dev;
6053 if (sp->rxd_mode == RXD_MODE_1) { 6019 if (sp->rxd_mode == RXD_MODE_1) {
@@ -6063,15 +6029,15 @@ static void set_rxd_buffer_size(nic_t *sp, RxD_t *rxdp, int size)
6063 } 6029 }
6064} 6030}
6065 6031
6066static int rxd_owner_bit_reset(nic_t *sp) 6032static int rxd_owner_bit_reset(struct s2io_nic *sp)
6067{ 6033{
6068 int i, j, k, blk_cnt = 0, size; 6034 int i, j, k, blk_cnt = 0, size;
6069 mac_info_t * mac_control = &sp->mac_control; 6035 struct mac_info * mac_control = &sp->mac_control;
6070 struct config_param *config = &sp->config; 6036 struct config_param *config = &sp->config;
6071 struct net_device *dev = sp->dev; 6037 struct net_device *dev = sp->dev;
6072 RxD_t *rxdp = NULL; 6038 struct RxD_t *rxdp = NULL;
6073 struct sk_buff *skb = NULL; 6039 struct sk_buff *skb = NULL;
6074 buffAdd_t *ba = NULL; 6040 struct buffAdd *ba = NULL;
6075 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0; 6041 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6076 6042
6077 /* Calculate the size based on ring mode */ 6043 /* Calculate the size based on ring mode */
@@ -6110,7 +6076,7 @@ static int rxd_owner_bit_reset(nic_t *sp)
6110 6076
6111} 6077}
6112 6078
6113static int s2io_add_isr(nic_t * sp) 6079static int s2io_add_isr(struct s2io_nic * sp)
6114{ 6080{
6115 int ret = 0; 6081 int ret = 0;
6116 struct net_device *dev = sp->dev; 6082 struct net_device *dev = sp->dev;
@@ -6125,7 +6091,7 @@ static int s2io_add_isr(nic_t * sp)
6125 sp->intr_type = INTA; 6091 sp->intr_type = INTA;
6126 } 6092 }
6127 6093
6128 /* Store the values of the MSIX table in the nic_t structure */ 6094 /* Store the values of the MSIX table in the struct s2io_nic structure */
6129 store_xmsi_data(sp); 6095 store_xmsi_data(sp);
6130 6096
6131 /* After proper initialization of H/W, register ISR */ 6097 /* After proper initialization of H/W, register ISR */
@@ -6180,7 +6146,7 @@ static int s2io_add_isr(nic_t * sp)
6180 } 6146 }
6181 return 0; 6147 return 0;
6182} 6148}
6183static void s2io_rem_isr(nic_t * sp) 6149static void s2io_rem_isr(struct s2io_nic * sp)
6184{ 6150{
6185 int cnt = 0; 6151 int cnt = 0;
6186 struct net_device *dev = sp->dev; 6152 struct net_device *dev = sp->dev;
@@ -6222,10 +6188,10 @@ static void s2io_rem_isr(nic_t * sp)
6222 } while(cnt < 5); 6188 } while(cnt < 5);
6223} 6189}
6224 6190
6225static void s2io_card_down(nic_t * sp) 6191static void s2io_card_down(struct s2io_nic * sp)
6226{ 6192{
6227 int cnt = 0; 6193 int cnt = 0;
6228 XENA_dev_config_t __iomem *bar0 = sp->bar0; 6194 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6229 unsigned long flags; 6195 unsigned long flags;
6230 register u64 val64 = 0; 6196 register u64 val64 = 0;
6231 6197
@@ -6256,7 +6222,8 @@ static void s2io_card_down(nic_t * sp)
6256 rxd_owner_bit_reset(sp); 6222 rxd_owner_bit_reset(sp);
6257 6223
6258 val64 = readq(&bar0->adapter_status); 6224 val64 = readq(&bar0->adapter_status);
6259 if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) { 6225 if (verify_xena_quiescence(sp)) {
6226 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
6260 break; 6227 break;
6261 } 6228 }
6262 6229
@@ -6285,10 +6252,10 @@ static void s2io_card_down(nic_t * sp)
6285 clear_bit(0, &(sp->link_state)); 6252 clear_bit(0, &(sp->link_state));
6286} 6253}
6287 6254
6288static int s2io_card_up(nic_t * sp) 6255static int s2io_card_up(struct s2io_nic * sp)
6289{ 6256{
6290 int i, ret = 0; 6257 int i, ret = 0;
6291 mac_info_t *mac_control; 6258 struct mac_info *mac_control;
6292 struct config_param *config; 6259 struct config_param *config;
6293 struct net_device *dev = (struct net_device *) sp->dev; 6260 struct net_device *dev = (struct net_device *) sp->dev;
6294 u16 interruptible; 6261 u16 interruptible;
@@ -6319,6 +6286,13 @@ static int s2io_card_up(nic_t * sp)
6319 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i, 6286 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6320 atomic_read(&sp->rx_bufs_left[i])); 6287 atomic_read(&sp->rx_bufs_left[i]));
6321 } 6288 }
6289 /* Maintain the state prior to the open */
6290 if (sp->promisc_flg)
6291 sp->promisc_flg = 0;
6292 if (sp->m_cast_flg) {
6293 sp->m_cast_flg = 0;
6294 sp->all_multi_pos= 0;
6295 }
6322 6296
6323 /* Setting its receive mode */ 6297 /* Setting its receive mode */
6324 s2io_set_multicast(dev); 6298 s2io_set_multicast(dev);
@@ -6380,7 +6354,7 @@ static int s2io_card_up(nic_t * sp)
6380 6354
6381static void s2io_restart_nic(struct work_struct *work) 6355static void s2io_restart_nic(struct work_struct *work)
6382{ 6356{
6383 nic_t *sp = container_of(work, nic_t, rst_timer_task); 6357 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
6384 struct net_device *dev = sp->dev; 6358 struct net_device *dev = sp->dev;
6385 6359
6386 s2io_card_down(sp); 6360 s2io_card_down(sp);
@@ -6409,7 +6383,7 @@ static void s2io_restart_nic(struct work_struct *work)
6409 6383
6410static void s2io_tx_watchdog(struct net_device *dev) 6384static void s2io_tx_watchdog(struct net_device *dev)
6411{ 6385{
6412 nic_t *sp = dev->priv; 6386 struct s2io_nic *sp = dev->priv;
6413 6387
6414 if (netif_carrier_ok(dev)) { 6388 if (netif_carrier_ok(dev)) {
6415 schedule_work(&sp->rst_timer_task); 6389 schedule_work(&sp->rst_timer_task);
@@ -6434,16 +6408,16 @@ static void s2io_tx_watchdog(struct net_device *dev)
6434 * Return value: 6408 * Return value:
6435 * SUCCESS on success and -1 on failure. 6409 * SUCCESS on success and -1 on failure.
6436 */ 6410 */
6437static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp) 6411static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
6438{ 6412{
6439 nic_t *sp = ring_data->nic; 6413 struct s2io_nic *sp = ring_data->nic;
6440 struct net_device *dev = (struct net_device *) sp->dev; 6414 struct net_device *dev = (struct net_device *) sp->dev;
6441 struct sk_buff *skb = (struct sk_buff *) 6415 struct sk_buff *skb = (struct sk_buff *)
6442 ((unsigned long) rxdp->Host_Control); 6416 ((unsigned long) rxdp->Host_Control);
6443 int ring_no = ring_data->ring_no; 6417 int ring_no = ring_data->ring_no;
6444 u16 l3_csum, l4_csum; 6418 u16 l3_csum, l4_csum;
6445 unsigned long long err = rxdp->Control_1 & RXD_T_CODE; 6419 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
6446 lro_t *lro; 6420 struct lro *lro;
6447 6421
6448 skb->dev = dev; 6422 skb->dev = dev;
6449 6423
@@ -6488,7 +6462,7 @@ static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
6488 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2); 6462 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
6489 unsigned char *buff = skb_push(skb, buf0_len); 6463 unsigned char *buff = skb_push(skb, buf0_len);
6490 6464
6491 buffAdd_t *ba = &ring_data->ba[get_block][get_off]; 6465 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
6492 sp->stats.rx_bytes += buf0_len + buf2_len; 6466 sp->stats.rx_bytes += buf0_len + buf2_len;
6493 memcpy(buff, ba->ba_0, buf0_len); 6467 memcpy(buff, ba->ba_0, buf0_len);
6494 6468
@@ -6498,7 +6472,6 @@ static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
6498 skb_put(skb, buf1_len); 6472 skb_put(skb, buf1_len);
6499 skb->len += buf2_len; 6473 skb->len += buf2_len;
6500 skb->data_len += buf2_len; 6474 skb->data_len += buf2_len;
6501 skb->truesize += buf2_len;
6502 skb_put(skb_shinfo(skb)->frag_list, buf2_len); 6475 skb_put(skb_shinfo(skb)->frag_list, buf2_len);
6503 sp->stats.rx_bytes += buf1_len; 6476 sp->stats.rx_bytes += buf1_len;
6504 6477
@@ -6582,23 +6555,20 @@ static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
6582 6555
6583 if (!sp->lro) { 6556 if (!sp->lro) {
6584 skb->protocol = eth_type_trans(skb, dev); 6557 skb->protocol = eth_type_trans(skb, dev);
6585#ifdef CONFIG_S2IO_NAPI
6586 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
6587 /* Queueing the vlan frame to the upper layer */
6588 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
6589 RXD_GET_VLAN_TAG(rxdp->Control_2));
6590 } else {
6591 netif_receive_skb(skb);
6592 }
6593#else
6594 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) { 6558 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
6595 /* Queueing the vlan frame to the upper layer */ 6559 /* Queueing the vlan frame to the upper layer */
6596 vlan_hwaccel_rx(skb, sp->vlgrp, 6560 if (napi)
6597 RXD_GET_VLAN_TAG(rxdp->Control_2)); 6561 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
6562 RXD_GET_VLAN_TAG(rxdp->Control_2));
6563 else
6564 vlan_hwaccel_rx(skb, sp->vlgrp,
6565 RXD_GET_VLAN_TAG(rxdp->Control_2));
6598 } else { 6566 } else {
6599 netif_rx(skb); 6567 if (napi)
6568 netif_receive_skb(skb);
6569 else
6570 netif_rx(skb);
6600 } 6571 }
6601#endif
6602 } else { 6572 } else {
6603send_up: 6573send_up:
6604 queue_rx_frame(skb); 6574 queue_rx_frame(skb);
@@ -6622,7 +6592,7 @@ aggregate:
6622 * void. 6592 * void.
6623 */ 6593 */
6624 6594
6625static void s2io_link(nic_t * sp, int link) 6595static void s2io_link(struct s2io_nic * sp, int link)
6626{ 6596{
6627 struct net_device *dev = (struct net_device *) sp->dev; 6597 struct net_device *dev = (struct net_device *) sp->dev;
6628 6598
@@ -6666,7 +6636,7 @@ static int get_xena_rev_id(struct pci_dev *pdev)
6666 * void 6636 * void
6667 */ 6637 */
6668 6638
6669static void s2io_init_pci(nic_t * sp) 6639static void s2io_init_pci(struct s2io_nic * sp)
6670{ 6640{
6671 u16 pci_cmd = 0, pcix_cmd = 0; 6641 u16 pci_cmd = 0, pcix_cmd = 0;
6672 6642
@@ -6699,13 +6669,9 @@ static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
6699 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n"); 6669 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
6700 rx_ring_num = 8; 6670 rx_ring_num = 8;
6701 } 6671 }
6702#ifdef CONFIG_S2IO_NAPI 6672 if (*dev_intr_type != INTA)
6703 if (*dev_intr_type != INTA) { 6673 napi = 0;
6704 DBG_PRINT(ERR_DBG, "s2io: NAPI cannot be enabled when " 6674
6705 "MSI/MSI-X is enabled. Defaulting to INTA\n");
6706 *dev_intr_type = INTA;
6707 }
6708#endif
6709#ifndef CONFIG_PCI_MSI 6675#ifndef CONFIG_PCI_MSI
6710 if (*dev_intr_type != INTA) { 6676 if (*dev_intr_type != INTA) {
6711 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support" 6677 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
@@ -6726,6 +6692,8 @@ static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
6726 "Defaulting to INTA\n"); 6692 "Defaulting to INTA\n");
6727 *dev_intr_type = INTA; 6693 *dev_intr_type = INTA;
6728 } 6694 }
6695 if ( (rx_ring_num > 1) && (*dev_intr_type != INTA) )
6696 napi = 0;
6729 if (rx_ring_mode > 3) { 6697 if (rx_ring_mode > 3) {
6730 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n"); 6698 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6731 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 3-buffer mode\n"); 6699 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 3-buffer mode\n");
@@ -6751,15 +6719,15 @@ static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
6751static int __devinit 6719static int __devinit
6752s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre) 6720s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6753{ 6721{
6754 nic_t *sp; 6722 struct s2io_nic *sp;
6755 struct net_device *dev; 6723 struct net_device *dev;
6756 int i, j, ret; 6724 int i, j, ret;
6757 int dma_flag = FALSE; 6725 int dma_flag = FALSE;
6758 u32 mac_up, mac_down; 6726 u32 mac_up, mac_down;
6759 u64 val64 = 0, tmp64 = 0; 6727 u64 val64 = 0, tmp64 = 0;
6760 XENA_dev_config_t __iomem *bar0 = NULL; 6728 struct XENA_dev_config __iomem *bar0 = NULL;
6761 u16 subid; 6729 u16 subid;
6762 mac_info_t *mac_control; 6730 struct mac_info *mac_control;
6763 struct config_param *config; 6731 struct config_param *config;
6764 int mode; 6732 int mode;
6765 u8 dev_intr_type = intr_type; 6733 u8 dev_intr_type = intr_type;
@@ -6814,7 +6782,7 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6814 } 6782 }
6815 } 6783 }
6816 6784
6817 dev = alloc_etherdev(sizeof(nic_t)); 6785 dev = alloc_etherdev(sizeof(struct s2io_nic));
6818 if (dev == NULL) { 6786 if (dev == NULL) {
6819 DBG_PRINT(ERR_DBG, "Device allocation failed\n"); 6787 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
6820 pci_disable_device(pdev); 6788 pci_disable_device(pdev);
@@ -6829,7 +6797,7 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6829 6797
6830 /* Private member variable initialized to s2io NIC structure */ 6798 /* Private member variable initialized to s2io NIC structure */
6831 sp = dev->priv; 6799 sp = dev->priv;
6832 memset(sp, 0, sizeof(nic_t)); 6800 memset(sp, 0, sizeof(struct s2io_nic));
6833 sp->dev = dev; 6801 sp->dev = dev;
6834 sp->pdev = pdev; 6802 sp->pdev = pdev;
6835 sp->high_dma_flag = dma_flag; 6803 sp->high_dma_flag = dma_flag;
@@ -6925,7 +6893,7 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6925 sp->bar0 = ioremap(pci_resource_start(pdev, 0), 6893 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
6926 pci_resource_len(pdev, 0)); 6894 pci_resource_len(pdev, 0));
6927 if (!sp->bar0) { 6895 if (!sp->bar0) {
6928 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n", 6896 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
6929 dev->name); 6897 dev->name);
6930 ret = -ENOMEM; 6898 ret = -ENOMEM;
6931 goto bar0_remap_failed; 6899 goto bar0_remap_failed;
@@ -6934,7 +6902,7 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6934 sp->bar1 = ioremap(pci_resource_start(pdev, 2), 6902 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
6935 pci_resource_len(pdev, 2)); 6903 pci_resource_len(pdev, 2));
6936 if (!sp->bar1) { 6904 if (!sp->bar1) {
6937 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n", 6905 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
6938 dev->name); 6906 dev->name);
6939 ret = -ENOMEM; 6907 ret = -ENOMEM;
6940 goto bar1_remap_failed; 6908 goto bar1_remap_failed;
@@ -6945,7 +6913,7 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6945 6913
6946 /* Initializing the BAR1 address as the start of the FIFO pointer. */ 6914 /* Initializing the BAR1 address as the start of the FIFO pointer. */
6947 for (j = 0; j < MAX_TX_FIFOS; j++) { 6915 for (j = 0; j < MAX_TX_FIFOS; j++) {
6948 mac_control->tx_FIFO_start[j] = (TxFIFO_element_t __iomem *) 6916 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
6949 (sp->bar1 + (j * 0x00020000)); 6917 (sp->bar1 + (j * 0x00020000));
6950 } 6918 }
6951 6919
@@ -6966,10 +6934,8 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6966 * will use eth_mac_addr() for dev->set_mac_address 6934 * will use eth_mac_addr() for dev->set_mac_address
6967 * mac address will be set every time dev->open() is called 6935 * mac address will be set every time dev->open() is called
6968 */ 6936 */
6969#if defined(CONFIG_S2IO_NAPI)
6970 dev->poll = s2io_poll; 6937 dev->poll = s2io_poll;
6971 dev->weight = 32; 6938 dev->weight = 32;
6972#endif
6973 6939
6974#ifdef CONFIG_NET_POLL_CONTROLLER 6940#ifdef CONFIG_NET_POLL_CONTROLLER
6975 dev->poll_controller = s2io_netpoll; 6941 dev->poll_controller = s2io_netpoll;
@@ -6978,13 +6944,9 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6978 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; 6944 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
6979 if (sp->high_dma_flag == TRUE) 6945 if (sp->high_dma_flag == TRUE)
6980 dev->features |= NETIF_F_HIGHDMA; 6946 dev->features |= NETIF_F_HIGHDMA;
6981#ifdef NETIF_F_TSO
6982 dev->features |= NETIF_F_TSO; 6947 dev->features |= NETIF_F_TSO;
6983#endif
6984#ifdef NETIF_F_TSO6
6985 dev->features |= NETIF_F_TSO6; 6948 dev->features |= NETIF_F_TSO6;
6986#endif 6949 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
6987 if (sp->device_type & XFRAME_II_DEVICE) {
6988 dev->features |= NETIF_F_UFO; 6950 dev->features |= NETIF_F_UFO;
6989 dev->features |= NETIF_F_HW_CSUM; 6951 dev->features |= NETIF_F_HW_CSUM;
6990 } 6952 }
@@ -7065,9 +7027,9 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7065 7027
7066 /* Initialize spinlocks */ 7028 /* Initialize spinlocks */
7067 spin_lock_init(&sp->tx_lock); 7029 spin_lock_init(&sp->tx_lock);
7068#ifndef CONFIG_S2IO_NAPI 7030
7069 spin_lock_init(&sp->put_lock); 7031 if (!napi)
7070#endif 7032 spin_lock_init(&sp->put_lock);
7071 spin_lock_init(&sp->rx_lock); 7033 spin_lock_init(&sp->rx_lock);
7072 7034
7073 /* 7035 /*
@@ -7098,13 +7060,14 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7098 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name, 7060 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7099 s2io_driver_version); 7061 s2io_driver_version);
7100 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: " 7062 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
7101 "%02x:%02x:%02x:%02x:%02x:%02x\n", dev->name, 7063 "%02x:%02x:%02x:%02x:%02x:%02x", dev->name,
7102 sp->def_mac_addr[0].mac_addr[0], 7064 sp->def_mac_addr[0].mac_addr[0],
7103 sp->def_mac_addr[0].mac_addr[1], 7065 sp->def_mac_addr[0].mac_addr[1],
7104 sp->def_mac_addr[0].mac_addr[2], 7066 sp->def_mac_addr[0].mac_addr[2],
7105 sp->def_mac_addr[0].mac_addr[3], 7067 sp->def_mac_addr[0].mac_addr[3],
7106 sp->def_mac_addr[0].mac_addr[4], 7068 sp->def_mac_addr[0].mac_addr[4],
7107 sp->def_mac_addr[0].mac_addr[5]); 7069 sp->def_mac_addr[0].mac_addr[5]);
7070 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
7108 if (sp->device_type & XFRAME_II_DEVICE) { 7071 if (sp->device_type & XFRAME_II_DEVICE) {
7109 mode = s2io_print_pci_mode(sp); 7072 mode = s2io_print_pci_mode(sp);
7110 if (mode < 0) { 7073 if (mode < 0) {
@@ -7128,9 +7091,9 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7128 dev->name); 7091 dev->name);
7129 break; 7092 break;
7130 } 7093 }
7131#ifdef CONFIG_S2IO_NAPI 7094
7132 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name); 7095 if (napi)
7133#endif 7096 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
7134 switch(sp->intr_type) { 7097 switch(sp->intr_type) {
7135 case INTA: 7098 case INTA:
7136 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name); 7099 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
@@ -7145,7 +7108,9 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7145 if (sp->lro) 7108 if (sp->lro)
7146 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n", 7109 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
7147 dev->name); 7110 dev->name);
7148 7111 if (ufo)
7112 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
7113 " enabled\n", dev->name);
7149 /* Initialize device name */ 7114 /* Initialize device name */
7150 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name); 7115 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7151 7116
@@ -7202,7 +7167,7 @@ static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7202{ 7167{
7203 struct net_device *dev = 7168 struct net_device *dev =
7204 (struct net_device *) pci_get_drvdata(pdev); 7169 (struct net_device *) pci_get_drvdata(pdev);
7205 nic_t *sp; 7170 struct s2io_nic *sp;
7206 7171
7207 if (dev == NULL) { 7172 if (dev == NULL) {
7208 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n"); 7173 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
@@ -7215,7 +7180,6 @@ static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7215 free_shared_mem(sp); 7180 free_shared_mem(sp);
7216 iounmap(sp->bar0); 7181 iounmap(sp->bar0);
7217 iounmap(sp->bar1); 7182 iounmap(sp->bar1);
7218 pci_disable_device(pdev);
7219 if (sp->intr_type != MSI_X) 7183 if (sp->intr_type != MSI_X)
7220 pci_release_regions(pdev); 7184 pci_release_regions(pdev);
7221 else { 7185 else {
@@ -7226,6 +7190,7 @@ static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7226 } 7190 }
7227 pci_set_drvdata(pdev, NULL); 7191 pci_set_drvdata(pdev, NULL);
7228 free_netdev(dev); 7192 free_netdev(dev);
7193 pci_disable_device(pdev);
7229} 7194}
7230 7195
7231/** 7196/**
@@ -7244,7 +7209,7 @@ int __init s2io_starter(void)
7244 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver. 7209 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7245 */ 7210 */
7246 7211
7247static void s2io_closer(void) 7212static __exit void s2io_closer(void)
7248{ 7213{
7249 pci_unregister_driver(&s2io_driver); 7214 pci_unregister_driver(&s2io_driver);
7250 DBG_PRINT(INIT_DBG, "cleanup done\n"); 7215 DBG_PRINT(INIT_DBG, "cleanup done\n");
@@ -7254,7 +7219,7 @@ module_init(s2io_starter);
7254module_exit(s2io_closer); 7219module_exit(s2io_closer);
7255 7220
7256static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip, 7221static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
7257 struct tcphdr **tcp, RxD_t *rxdp) 7222 struct tcphdr **tcp, struct RxD_t *rxdp)
7258{ 7223{
7259 int ip_off; 7224 int ip_off;
7260 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len; 7225 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
@@ -7288,7 +7253,7 @@ static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
7288 return 0; 7253 return 0;
7289} 7254}
7290 7255
7291static int check_for_socket_match(lro_t *lro, struct iphdr *ip, 7256static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7292 struct tcphdr *tcp) 7257 struct tcphdr *tcp)
7293{ 7258{
7294 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__); 7259 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
@@ -7303,7 +7268,7 @@ static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7303 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2)); 7268 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7304} 7269}
7305 7270
7306static void initiate_new_session(lro_t *lro, u8 *l2h, 7271static void initiate_new_session(struct lro *lro, u8 *l2h,
7307 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len) 7272 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7308{ 7273{
7309 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__); 7274 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
@@ -7329,12 +7294,12 @@ static void initiate_new_session(lro_t *lro, u8 *l2h,
7329 lro->in_use = 1; 7294 lro->in_use = 1;
7330} 7295}
7331 7296
7332static void update_L3L4_header(nic_t *sp, lro_t *lro) 7297static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7333{ 7298{
7334 struct iphdr *ip = lro->iph; 7299 struct iphdr *ip = lro->iph;
7335 struct tcphdr *tcp = lro->tcph; 7300 struct tcphdr *tcp = lro->tcph;
7336 u16 nchk; 7301 u16 nchk;
7337 StatInfo_t *statinfo = sp->mac_control.stats_info; 7302 struct stat_block *statinfo = sp->mac_control.stats_info;
7338 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__); 7303 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7339 7304
7340 /* Update L3 header */ 7305 /* Update L3 header */
@@ -7360,7 +7325,7 @@ static void update_L3L4_header(nic_t *sp, lro_t *lro)
7360 statinfo->sw_stat.num_aggregations++; 7325 statinfo->sw_stat.num_aggregations++;
7361} 7326}
7362 7327
7363static void aggregate_new_rx(lro_t *lro, struct iphdr *ip, 7328static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7364 struct tcphdr *tcp, u32 l4_pyld) 7329 struct tcphdr *tcp, u32 l4_pyld)
7365{ 7330{
7366 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__); 7331 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
@@ -7382,7 +7347,7 @@ static void aggregate_new_rx(lro_t *lro, struct iphdr *ip,
7382 } 7347 }
7383} 7348}
7384 7349
7385static int verify_l3_l4_lro_capable(lro_t *l_lro, struct iphdr *ip, 7350static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7386 struct tcphdr *tcp, u32 tcp_pyld_len) 7351 struct tcphdr *tcp, u32 tcp_pyld_len)
7387{ 7352{
7388 u8 *ptr; 7353 u8 *ptr;
@@ -7440,8 +7405,8 @@ static int verify_l3_l4_lro_capable(lro_t *l_lro, struct iphdr *ip,
7440} 7405}
7441 7406
7442static int 7407static int
7443s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro, 7408s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
7444 RxD_t *rxdp, nic_t *sp) 7409 struct RxD_t *rxdp, struct s2io_nic *sp)
7445{ 7410{
7446 struct iphdr *ip; 7411 struct iphdr *ip;
7447 struct tcphdr *tcph; 7412 struct tcphdr *tcph;
@@ -7458,7 +7423,7 @@ s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro,
7458 tcph = (struct tcphdr *)*tcp; 7423 tcph = (struct tcphdr *)*tcp;
7459 *tcp_len = get_l4_pyld_length(ip, tcph); 7424 *tcp_len = get_l4_pyld_length(ip, tcph);
7460 for (i=0; i<MAX_LRO_SESSIONS; i++) { 7425 for (i=0; i<MAX_LRO_SESSIONS; i++) {
7461 lro_t *l_lro = &sp->lro0_n[i]; 7426 struct lro *l_lro = &sp->lro0_n[i];
7462 if (l_lro->in_use) { 7427 if (l_lro->in_use) {
7463 if (check_for_socket_match(l_lro, ip, tcph)) 7428 if (check_for_socket_match(l_lro, ip, tcph))
7464 continue; 7429 continue;
@@ -7496,7 +7461,7 @@ s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro,
7496 } 7461 }
7497 7462
7498 for (i=0; i<MAX_LRO_SESSIONS; i++) { 7463 for (i=0; i<MAX_LRO_SESSIONS; i++) {
7499 lro_t *l_lro = &sp->lro0_n[i]; 7464 struct lro *l_lro = &sp->lro0_n[i];
7500 if (!(l_lro->in_use)) { 7465 if (!(l_lro->in_use)) {
7501 *lro = l_lro; 7466 *lro = l_lro;
7502 ret = 3; /* Begin anew */ 7467 ret = 3; /* Begin anew */
@@ -7535,9 +7500,9 @@ s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro,
7535 return ret; 7500 return ret;
7536} 7501}
7537 7502
7538static void clear_lro_session(lro_t *lro) 7503static void clear_lro_session(struct lro *lro)
7539{ 7504{
7540 static u16 lro_struct_size = sizeof(lro_t); 7505 static u16 lro_struct_size = sizeof(struct lro);
7541 7506
7542 memset(lro, 0, lro_struct_size); 7507 memset(lro, 0, lro_struct_size);
7543} 7508}
@@ -7547,14 +7512,14 @@ static void queue_rx_frame(struct sk_buff *skb)
7547 struct net_device *dev = skb->dev; 7512 struct net_device *dev = skb->dev;
7548 7513
7549 skb->protocol = eth_type_trans(skb, dev); 7514 skb->protocol = eth_type_trans(skb, dev);
7550#ifdef CONFIG_S2IO_NAPI 7515 if (napi)
7551 netif_receive_skb(skb); 7516 netif_receive_skb(skb);
7552#else 7517 else
7553 netif_rx(skb); 7518 netif_rx(skb);
7554#endif
7555} 7519}
7556 7520
7557static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb, 7521static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
7522 struct sk_buff *skb,
7558 u32 tcp_len) 7523 u32 tcp_len)
7559{ 7524{
7560 struct sk_buff *first = lro->parent; 7525 struct sk_buff *first = lro->parent;
@@ -7566,6 +7531,7 @@ static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb,
7566 lro->last_frag->next = skb; 7531 lro->last_frag->next = skb;
7567 else 7532 else
7568 skb_shinfo(first)->frag_list = skb; 7533 skb_shinfo(first)->frag_list = skb;
7534 first->truesize += skb->truesize;
7569 lro->last_frag = skb; 7535 lro->last_frag = skb;
7570 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++; 7536 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
7571 return; 7537 return;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 06:32:07 -0500