1 files changed, 106 insertions, 10 deletions

diff --git a/drivers/net/s2io-regs.h b/drivers/net/s2io-regs.h
index 83e3e47a9e3d..aef66e2d98d2 100644
--- a/drivers/net/s2io-regs.h
+++ b/drivers/net/s2io-regs.h
@@ -325,33 +325,66 @@ struct XENA_dev_config {
 #define TXDMA_TPA_INT                  BIT(5)
 #define TXDMA_SM_INT                   BIT(6)
         u64 pfc_err_reg;
+#define PFC_ECC_SG_ERR                  BIT(7)
+#define PFC_ECC_DB_ERR                  BIT(15)
+#define PFC_SM_ERR_ALARM                BIT(23)
+#define PFC_MISC_0_ERR                  BIT(31)
+#define PFC_MISC_1_ERR                  BIT(32)
+#define PFC_PCIX_ERR                    BIT(39)
         u64 pfc_err_mask;
         u64 pfc_err_alarm;
 
         u64 tda_err_reg;
+#define TDA_Fn_ECC_SG_ERR               vBIT(0xff,0,8)
+#define TDA_Fn_ECC_DB_ERR               vBIT(0xff,8,8)
+#define TDA_SM0_ERR_ALARM               BIT(22)
+#define TDA_SM1_ERR_ALARM               BIT(23)
+#define TDA_PCIX_ERR                    BIT(39)
         u64 tda_err_mask;
         u64 tda_err_alarm;
 
         u64 pcc_err_reg;
-#define PCC_FB_ECC_DB_ERR               vBIT(0xFF, 16, 8)
+#define PCC_FB_ECC_SG_ERR               vBIT(0xFF,0,8)
+#define PCC_TXB_ECC_SG_ERR              vBIT(0xFF,8,8)
+#define PCC_FB_ECC_DB_ERR               vBIT(0xFF,16, 8)
+#define PCC_TXB_ECC_DB_ERR              vBIT(0xff,24,8)
+#define PCC_SM_ERR_ALARM                vBIT(0xff,32,8)
+#define PCC_WR_ERR_ALARM                vBIT(0xff,40,8)
+#define PCC_N_SERR                      vBIT(0xff,48,8)
+#define PCC_6_COF_OV_ERR                BIT(56)
+#define PCC_7_COF_OV_ERR                BIT(57)
+#define PCC_6_LSO_OV_ERR                BIT(58)
+#define PCC_7_LSO_OV_ERR                BIT(59)
 #define PCC_ENABLE_FOUR                 vBIT(0x0F,0,8)
-
         u64 pcc_err_mask;
         u64 pcc_err_alarm;
 
         u64 tti_err_reg;
+#define TTI_ECC_SG_ERR                  BIT(7)
+#define TTI_ECC_DB_ERR                  BIT(15)
+#define TTI_SM_ERR_ALARM                BIT(23)
         u64 tti_err_mask;
         u64 tti_err_alarm;
 
         u64 lso_err_reg;
+#define LSO6_SEND_OFLOW                 BIT(12)
+#define LSO7_SEND_OFLOW                 BIT(13)
+#define LSO6_ABORT                      BIT(14)
+#define LSO7_ABORT                      BIT(15)
+#define LSO6_SM_ERR_ALARM               BIT(22)
+#define LSO7_SM_ERR_ALARM               BIT(23)
         u64 lso_err_mask;
         u64 lso_err_alarm;
 
         u64 tpa_err_reg;
+#define TPA_TX_FRM_DROP                 BIT(7)
+#define TPA_SM_ERR_ALARM                BIT(23)
+
         u64 tpa_err_mask;
         u64 tpa_err_alarm;
 
         u64 sm_err_reg;
+#define SM_SM_ERR_ALARM                 BIT(15)
         u64 sm_err_mask;
         u64 sm_err_alarm;
 
@@ -450,22 +483,52 @@ struct XENA_dev_config {
 #define RXDMA_INT_RTI_INT_M            BIT(3)
 
         u64 rda_err_reg;
+#define RDA_RXDn_ECC_SG_ERR             vBIT(0xFF,0,8)
+#define RDA_RXDn_ECC_DB_ERR             vBIT(0xFF,8,8)
+#define RDA_FRM_ECC_SG_ERR              BIT(23)
+#define RDA_FRM_ECC_DB_N_AERR           BIT(31)
+#define RDA_SM1_ERR_ALARM               BIT(38)
+#define RDA_SM0_ERR_ALARM               BIT(39)
+#define RDA_MISC_ERR                    BIT(47)
+#define RDA_PCIX_ERR                    BIT(55)
+#define RDA_RXD_ECC_DB_SERR             BIT(63)
         u64 rda_err_mask;
         u64 rda_err_alarm;
 
         u64 rc_err_reg;
+#define RC_PRCn_ECC_SG_ERR              vBIT(0xFF,0,8)
+#define RC_PRCn_ECC_DB_ERR              vBIT(0xFF,8,8)
+#define RC_FTC_ECC_SG_ERR               BIT(23)
+#define RC_FTC_ECC_DB_ERR               BIT(31)
+#define RC_PRCn_SM_ERR_ALARM            vBIT(0xFF,32,8)
+#define RC_FTC_SM_ERR_ALARM             BIT(47)
+#define RC_RDA_FAIL_WR_Rn               vBIT(0xFF,48,8)
         u64 rc_err_mask;
         u64 rc_err_alarm;
 
         u64 prc_pcix_err_reg;
+#define PRC_PCI_AB_RD_Rn                vBIT(0xFF,0,8)
+#define PRC_PCI_DP_RD_Rn                vBIT(0xFF,8,8)
+#define PRC_PCI_AB_WR_Rn                vBIT(0xFF,16,8)
+#define PRC_PCI_DP_WR_Rn                vBIT(0xFF,24,8)
+#define PRC_PCI_AB_F_WR_Rn              vBIT(0xFF,32,8)
+#define PRC_PCI_DP_F_WR_Rn              vBIT(0xFF,40,8)
         u64 prc_pcix_err_mask;
         u64 prc_pcix_err_alarm;
 
         u64 rpa_err_reg;
+#define RPA_ECC_SG_ERR                  BIT(7)
+#define RPA_ECC_DB_ERR                  BIT(15)
+#define RPA_FLUSH_REQUEST               BIT(22)
+#define RPA_SM_ERR_ALARM                BIT(23)
+#define RPA_CREDIT_ERR                  BIT(31)
         u64 rpa_err_mask;
         u64 rpa_err_alarm;
 
         u64 rti_err_reg;
+#define RTI_ECC_SG_ERR                  BIT(7)
+#define RTI_ECC_DB_ERR                  BIT(15)
+#define RTI_SM_ERR_ALARM                BIT(23)
         u64 rti_err_mask;
         u64 rti_err_alarm;
 
@@ -582,17 +645,43 @@ struct XENA_dev_config {
 #define MAC_INT_STATUS_RMAC_INT            BIT(1)
 
         u64 mac_tmac_err_reg;
-#define TMAC_ERR_REG_TMAC_ECC_DB_ERR       BIT(15)
-#define TMAC_ERR_REG_TMAC_TX_BUF_OVRN      BIT(23)
-#define TMAC_ERR_REG_TMAC_TX_CRI_ERR       BIT(31)
+#define TMAC_ECC_SG_ERR                         BIT(7)
+#define TMAC_ECC_DB_ERR                         BIT(15)
+#define TMAC_TX_BUF_OVRN                        BIT(23)
+#define TMAC_TX_CRI_ERR                         BIT(31)
+#define TMAC_TX_SM_ERR                          BIT(39)
+#define TMAC_DESC_ECC_SG_ERR                    BIT(47)
+#define TMAC_DESC_ECC_DB_ERR                    BIT(55)
+
         u64 mac_tmac_err_mask;
         u64 mac_tmac_err_alarm;
 
         u64 mac_rmac_err_reg;
-#define RMAC_ERR_REG_RX_BUFF_OVRN          BIT(0)
-#define RMAC_ERR_REG_RTS_ECC_DB_ERR        BIT(14)
-#define RMAC_ERR_REG_ECC_DB_ERR            BIT(15)
-#define RMAC_LINK_STATE_CHANGE_INT         BIT(31)
+#define RMAC_RX_BUFF_OVRN                       BIT(0)
+#define RMAC_FRM_RCVD_INT                       BIT(1)
+#define RMAC_UNUSED_INT                         BIT(2)
+#define RMAC_RTS_PNUM_ECC_SG_ERR                BIT(5)
+#define RMAC_RTS_DS_ECC_SG_ERR                  BIT(6)
+#define RMAC_RD_BUF_ECC_SG_ERR                  BIT(7)
+#define RMAC_RTH_MAP_ECC_SG_ERR                 BIT(8)
+#define RMAC_RTH_SPDM_ECC_SG_ERR                BIT(9)
+#define RMAC_RTS_VID_ECC_SG_ERR                 BIT(10)
+#define RMAC_DA_SHADOW_ECC_SG_ERR               BIT(11)
+#define RMAC_RTS_PNUM_ECC_DB_ERR                BIT(13)
+#define RMAC_RTS_DS_ECC_DB_ERR                  BIT(14)
+#define RMAC_RD_BUF_ECC_DB_ERR                  BIT(15)
+#define RMAC_RTH_MAP_ECC_DB_ERR                 BIT(16)
+#define RMAC_RTH_SPDM_ECC_DB_ERR                BIT(17)
+#define RMAC_RTS_VID_ECC_DB_ERR                 BIT(18)
+#define RMAC_DA_SHADOW_ECC_DB_ERR               BIT(19)
+#define RMAC_LINK_STATE_CHANGE_INT              BIT(31)
+#define RMAC_RX_SM_ERR                          BIT(39)
+#define RMAC_SINGLE_ECC_ERR                     (BIT(5) | BIT(6) | BIT(7) |\
+                                                BIT(8)  | BIT(9) | BIT(10)|\
+                                                BIT(11))
+#define RMAC_DOUBLE_ECC_ERR                     (BIT(13) | BIT(14) | BIT(15) |\
+                                                BIT(16)  | BIT(17) | BIT(18)|\
+                                                BIT(19))
         u64 mac_rmac_err_mask;
         u64 mac_rmac_err_alarm;
 
@@ -750,6 +839,7 @@ struct XENA_dev_config {
                                         BIT(17) | BIT(19))
 #define MC_ERR_REG_ECC_ALL_DBL             (BIT(10) | BIT(11) | BIT(12) |\
                                         BIT(13) | BIT(18) | BIT(20))
+#define PLL_LOCK_N                      BIT(39)
         u64 mc_err_mask;
         u64 mc_err_alarm;
 
@@ -823,11 +913,17 @@ struct XENA_dev_config {
 #define XGXS_INT_MASK_RXGXS                BIT(1)
 
         u64 xgxs_txgxs_err_reg;
-#define TXGXS_ECC_DB_ERR                   BIT(15)
+#define TXGXS_ECC_SG_ERR                BIT(7)
+#define TXGXS_ECC_DB_ERR                BIT(15)
+#define TXGXS_ESTORE_UFLOW              BIT(31)
+#define TXGXS_TX_SM_ERR                 BIT(39)
+
         u64 xgxs_txgxs_err_mask;
         u64 xgxs_txgxs_err_alarm;
 
         u64 xgxs_rxgxs_err_reg;
+#define RXGXS_ESTORE_OFLOW              BIT(7)
+#define RXGXS_RX_SM_ERR                 BIT(39)
         u64 xgxs_rxgxs_err_mask;
         u64 xgxs_rxgxs_err_alarm;