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-rw-r--r--drivers/net/s2io-regs.h778
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diff --git a/drivers/net/s2io-regs.h b/drivers/net/s2io-regs.h
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1/************************************************************************
2 * regs.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
3 * Copyright(c) 2002-2005 Neterion Inc.
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
13#ifndef _REGS_H
14#define _REGS_H
15
16#define TBD 0
17
18typedef struct _XENA_dev_config {
19/* Convention: mHAL_XXX is mask, vHAL_XXX is value */
20
21/* General Control-Status Registers */
22 u64 general_int_status;
23#define GEN_INTR_TXPIC BIT(0)
24#define GEN_INTR_TXDMA BIT(1)
25#define GEN_INTR_TXMAC BIT(2)
26#define GEN_INTR_TXXGXS BIT(3)
27#define GEN_INTR_TXTRAFFIC BIT(8)
28#define GEN_INTR_RXPIC BIT(32)
29#define GEN_INTR_RXDMA BIT(33)
30#define GEN_INTR_RXMAC BIT(34)
31#define GEN_INTR_MC BIT(35)
32#define GEN_INTR_RXXGXS BIT(36)
33#define GEN_INTR_RXTRAFFIC BIT(40)
34#define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \
35 GEN_INTR_TXDMA | GEN_INTR_RXDMA | \
36 GEN_INTR_TXMAC | GEN_INTR_RXMAC | \
37 GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \
38 GEN_INTR_MC
39
40 u64 general_int_mask;
41
42 u8 unused0[0x100 - 0x10];
43
44 u64 sw_reset;
45/* XGXS must be removed from reset only once. */
46#define SW_RESET_XENA vBIT(0xA5,0,8)
47#define SW_RESET_FLASH vBIT(0xA5,8,8)
48#define SW_RESET_EOI vBIT(0xA5,16,8)
49#define SW_RESET_ALL (SW_RESET_XENA | \
50 SW_RESET_FLASH | \
51 SW_RESET_EOI)
52/* The SW_RESET register must read this value after a successful reset. */
53#define SW_RESET_RAW_VAL 0xA5000000
54
55
56 u64 adapter_status;
57#define ADAPTER_STATUS_TDMA_READY BIT(0)
58#define ADAPTER_STATUS_RDMA_READY BIT(1)
59#define ADAPTER_STATUS_PFC_READY BIT(2)
60#define ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3)
61#define ADAPTER_STATUS_PIC_QUIESCENT BIT(5)
62#define ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6)
63#define ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7)
64#define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
65#define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
66#define ADAPTER_STATUS_MC_DRAM_READY BIT(24)
67#define ADAPTER_STATUS_MC_QUEUES_READY BIT(25)
68#define ADAPTER_STATUS_M_PLL_LOCK BIT(30)
69#define ADAPTER_STATUS_P_PLL_LOCK BIT(31)
70
71 u64 adapter_control;
72#define ADAPTER_CNTL_EN BIT(7)
73#define ADAPTER_EOI_TX_ON BIT(15)
74#define ADAPTER_LED_ON BIT(23)
75#define ADAPTER_UDPI(val) vBIT(val,36,4)
76#define ADAPTER_WAIT_INT BIT(48)
77#define ADAPTER_ECC_EN BIT(55)
78
79 u64 serr_source;
80#define SERR_SOURCE_PIC BIT(0)
81#define SERR_SOURCE_TXDMA BIT(1)
82#define SERR_SOURCE_RXDMA BIT(2)
83#define SERR_SOURCE_MAC BIT(3)
84#define SERR_SOURCE_MC BIT(4)
85#define SERR_SOURCE_XGXS BIT(5)
86#define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \
87 SERR_SOURCE_TXDMA | \
88 SERR_SOURCE_RXDMA | \
89 SERR_SOURCE_MAC | \
90 SERR_SOURCE_MC | \
91 SERR_SOURCE_XGXS)
92
93
94 u8 unused_0[0x800 - 0x120];
95
96/* PCI-X Controller registers */
97 u64 pic_int_status;
98 u64 pic_int_mask;
99#define PIC_INT_TX BIT(0)
100#define PIC_INT_FLSH BIT(1)
101#define PIC_INT_MDIO BIT(2)
102#define PIC_INT_IIC BIT(3)
103#define PIC_INT_GPIO BIT(4)
104#define PIC_INT_RX BIT(32)
105
106 u64 txpic_int_reg;
107 u64 txpic_int_mask;
108#define PCIX_INT_REG_ECC_SG_ERR BIT(0)
109#define PCIX_INT_REG_ECC_DB_ERR BIT(1)
110#define PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8)
111#define PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9)
112#define PCIX_INT_REG_INI_TX_FSM_SERR BIT(10)
113#define PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11)
114#define PCIX_INT_REG_TRT_FSM_SERR BIT(13)
115#define PCIX_INT_REG_SRT_FSM_SERR BIT(14)
116#define PCIX_INT_REG_PIFR_FSM_SERR BIT(15)
117#define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21)
118#define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23)
119#define PCIX_INT_REG_INI_RX_FSM_SERR BIT(48)
120#define PCIX_INT_REG_RA_RX_FSM_SERR BIT(50)
121/*
122#define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52)
123#define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54)
124#define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58)
125*/
126 u64 txpic_alarms;
127 u64 rxpic_int_reg;
128 u64 rxpic_int_mask;
129 u64 rxpic_alarms;
130
131 u64 flsh_int_reg;
132 u64 flsh_int_mask;
133#define PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63)
134#define PIC_FLSH_INT_REG_ERR BIT(62)
135 u64 flash_alarms;
136
137 u64 mdio_int_reg;
138 u64 mdio_int_mask;
139#define MDIO_INT_REG_MDIO_BUS_ERR BIT(0)
140#define MDIO_INT_REG_DTX_BUS_ERR BIT(8)
141#define MDIO_INT_REG_LASI BIT(39)
142 u64 mdio_alarms;
143
144 u64 iic_int_reg;
145 u64 iic_int_mask;
146#define IIC_INT_REG_BUS_FSM_ERR BIT(4)
147#define IIC_INT_REG_BIT_FSM_ERR BIT(5)
148#define IIC_INT_REG_CYCLE_FSM_ERR BIT(6)
149#define IIC_INT_REG_REQ_FSM_ERR BIT(7)
150#define IIC_INT_REG_ACK_ERR BIT(8)
151 u64 iic_alarms;
152
153 u8 unused4[0x08];
154
155 u64 gpio_int_reg;
156 u64 gpio_int_mask;
157 u64 gpio_alarms;
158
159 u8 unused5[0x38];
160
161 u64 tx_traffic_int;
162#define TX_TRAFFIC_INT_n(n) BIT(n)
163 u64 tx_traffic_mask;
164
165 u64 rx_traffic_int;
166#define RX_TRAFFIC_INT_n(n) BIT(n)
167 u64 rx_traffic_mask;
168
169/* PIC Control registers */
170 u64 pic_control;
171#define PIC_CNTL_RX_ALARM_MAP_1 BIT(0)
172#define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,4)
173
174 u64 swapper_ctrl;
175#define SWAPPER_CTRL_PIF_R_FE BIT(0)
176#define SWAPPER_CTRL_PIF_R_SE BIT(1)
177#define SWAPPER_CTRL_PIF_W_FE BIT(8)
178#define SWAPPER_CTRL_PIF_W_SE BIT(9)
179#define SWAPPER_CTRL_TXP_FE BIT(16)
180#define SWAPPER_CTRL_TXP_SE BIT(17)
181#define SWAPPER_CTRL_TXD_R_FE BIT(18)
182#define SWAPPER_CTRL_TXD_R_SE BIT(19)
183#define SWAPPER_CTRL_TXD_W_FE BIT(20)
184#define SWAPPER_CTRL_TXD_W_SE BIT(21)
185#define SWAPPER_CTRL_TXF_R_FE BIT(22)
186#define SWAPPER_CTRL_TXF_R_SE BIT(23)
187#define SWAPPER_CTRL_RXD_R_FE BIT(32)
188#define SWAPPER_CTRL_RXD_R_SE BIT(33)
189#define SWAPPER_CTRL_RXD_W_FE BIT(34)
190#define SWAPPER_CTRL_RXD_W_SE BIT(35)
191#define SWAPPER_CTRL_RXF_W_FE BIT(36)
192#define SWAPPER_CTRL_RXF_W_SE BIT(37)
193#define SWAPPER_CTRL_XMSI_FE BIT(40)
194#define SWAPPER_CTRL_XMSI_SE BIT(41)
195#define SWAPPER_CTRL_STATS_FE BIT(48)
196#define SWAPPER_CTRL_STATS_SE BIT(49)
197
198 u64 pif_rd_swapper_fb;
199#define IF_RD_SWAPPER_FB 0x0123456789ABCDEF
200
201 u64 scheduled_int_ctrl;
202#define SCHED_INT_CTRL_TIMER_EN BIT(0)
203#define SCHED_INT_CTRL_ONE_SHOT BIT(1)
204#define SCHED_INT_CTRL_INT2MSI TBD
205#define SCHED_INT_PERIOD TBD
206
207 u64 txreqtimeout;
208#define TXREQTO_VAL(val) vBIT(val,0,32)
209#define TXREQTO_EN BIT(63)
210
211 u64 statsreqtimeout;
212#define STATREQTO_VAL(n) TBD
213#define STATREQTO_EN BIT(63)
214
215 u64 read_retry_delay;
216 u64 read_retry_acceleration;
217 u64 write_retry_delay;
218 u64 write_retry_acceleration;
219
220 u64 xmsi_control;
221 u64 xmsi_access;
222 u64 xmsi_address;
223 u64 xmsi_data;
224
225 u64 rx_mat;
226
227 u8 unused6[0x8];
228
229 u64 tx_mat0_7;
230 u64 tx_mat8_15;
231 u64 tx_mat16_23;
232 u64 tx_mat24_31;
233 u64 tx_mat32_39;
234 u64 tx_mat40_47;
235 u64 tx_mat48_55;
236 u64 tx_mat56_63;
237
238 u8 unused_1[0x10];
239
240 /* Automated statistics collection */
241 u64 stat_cfg;
242#define STAT_CFG_STAT_EN BIT(0)
243#define STAT_CFG_ONE_SHOT_EN BIT(1)
244#define STAT_CFG_STAT_NS_EN BIT(8)
245#define STAT_CFG_STAT_RO BIT(9)
246#define STAT_TRSF_PER(n) TBD
247#define PER_SEC 0x208d5
248#define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32)
249
250 u64 stat_addr;
251
252 /* General Configuration */
253 u64 mdio_control;
254
255 u64 dtx_control;
256
257 u64 i2c_control;
258#define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3)
259#define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11)
260#define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2)
261#define I2C_CONTROL_READ BIT(24)
262#define I2C_CONTROL_NACK BIT(25)
263#define I2C_CONTROL_CNTL_START vBIT(0xE,28,4)
264#define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))
265#define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF)
266#define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32)
267
268 u64 gpio_control;
269#define GPIO_CTRL_GPIO_0 BIT(8)
270
271 u8 unused7[0x600];
272
273/* TxDMA registers */
274 u64 txdma_int_status;
275 u64 txdma_int_mask;
276#define TXDMA_PFC_INT BIT(0)
277#define TXDMA_TDA_INT BIT(1)
278#define TXDMA_PCC_INT BIT(2)
279#define TXDMA_TTI_INT BIT(3)
280#define TXDMA_LSO_INT BIT(4)
281#define TXDMA_TPA_INT BIT(5)
282#define TXDMA_SM_INT BIT(6)
283 u64 pfc_err_reg;
284 u64 pfc_err_mask;
285 u64 pfc_err_alarm;
286
287 u64 tda_err_reg;
288 u64 tda_err_mask;
289 u64 tda_err_alarm;
290
291 u64 pcc_err_reg;
292#define PCC_FB_ECC_DB_ERR vBIT(0xFF, 16, 8)
293
294 u64 pcc_err_mask;
295 u64 pcc_err_alarm;
296
297 u64 tti_err_reg;
298 u64 tti_err_mask;
299 u64 tti_err_alarm;
300
301 u64 lso_err_reg;
302 u64 lso_err_mask;
303 u64 lso_err_alarm;
304
305 u64 tpa_err_reg;
306 u64 tpa_err_mask;
307 u64 tpa_err_alarm;
308
309 u64 sm_err_reg;
310 u64 sm_err_mask;
311 u64 sm_err_alarm;
312
313 u8 unused8[0x100 - 0xB8];
314
315/* TxDMA arbiter */
316 u64 tx_dma_wrap_stat;
317
318/* Tx FIFO controller */
319#define X_MAX_FIFOS 8
320#define X_FIFO_MAX_LEN 0x1FFF /*8191 */
321 u64 tx_fifo_partition_0;
322#define TX_FIFO_PARTITION_EN BIT(0)
323#define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)
324#define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)
325#define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)
326#define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 )
327
328 u64 tx_fifo_partition_1;
329#define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)
330#define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)
331#define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)
332#define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13)
333
334 u64 tx_fifo_partition_2;
335#define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)
336#define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)
337#define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)
338#define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13)
339
340 u64 tx_fifo_partition_3;
341#define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)
342#define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)
343#define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)
344#define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)
345
346#define TX_FIFO_PARTITION_PRI_0 0 /* highest */
347#define TX_FIFO_PARTITION_PRI_1 1
348#define TX_FIFO_PARTITION_PRI_2 2
349#define TX_FIFO_PARTITION_PRI_3 3
350#define TX_FIFO_PARTITION_PRI_4 4
351#define TX_FIFO_PARTITION_PRI_5 5
352#define TX_FIFO_PARTITION_PRI_6 6
353#define TX_FIFO_PARTITION_PRI_7 7 /* lowest */
354
355 u64 tx_w_round_robin_0;
356 u64 tx_w_round_robin_1;
357 u64 tx_w_round_robin_2;
358 u64 tx_w_round_robin_3;
359 u64 tx_w_round_robin_4;
360
361 u64 tti_command_mem;
362#define TTI_CMD_MEM_WE BIT(7)
363#define TTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
364#define TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15)
365#define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6)
366
367 u64 tti_data1_mem;
368#define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26)
369#define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2)
370#define TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38)
371#define TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39)
372#define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7)
373#define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7)
374#define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7)
375
376 u64 tti_data2_mem;
377#define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16)
378#define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16)
379#define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16)
380#define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16)
381
382/* Tx Protocol assist */
383 u64 tx_pa_cfg;
384#define TX_PA_CFG_IGNORE_FRM_ERR BIT(1)
385#define TX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
386#define TX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
387#define TX_PA_CFG_IGNORE_L2_ERR BIT(6)
388
389/* Recent add, used only debug purposes. */
390 u64 pcc_enable;
391
392 u8 unused9[0x700 - 0x178];
393
394 u64 txdma_debug_ctrl;
395
396 u8 unused10[0x1800 - 0x1708];
397
398/* RxDMA Registers */
399 u64 rxdma_int_status;
400 u64 rxdma_int_mask;
401#define RXDMA_INT_RC_INT_M BIT(0)
402#define RXDMA_INT_RPA_INT_M BIT(1)
403#define RXDMA_INT_RDA_INT_M BIT(2)
404#define RXDMA_INT_RTI_INT_M BIT(3)
405
406 u64 rda_err_reg;
407 u64 rda_err_mask;
408 u64 rda_err_alarm;
409
410 u64 rc_err_reg;
411 u64 rc_err_mask;
412 u64 rc_err_alarm;
413
414 u64 prc_pcix_err_reg;
415 u64 prc_pcix_err_mask;
416 u64 prc_pcix_err_alarm;
417
418 u64 rpa_err_reg;
419 u64 rpa_err_mask;
420 u64 rpa_err_alarm;
421
422 u64 rti_err_reg;
423 u64 rti_err_mask;
424 u64 rti_err_alarm;
425
426 u8 unused11[0x100 - 0x88];
427
428/* DMA arbiter */
429 u64 rx_queue_priority;
430#define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3)
431#define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3)
432#define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3)
433#define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3)
434#define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3)
435#define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3)
436#define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3)
437#define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3)
438
439#define RX_QUEUE_PRI_0 0 /* highest */
440#define RX_QUEUE_PRI_1 1
441#define RX_QUEUE_PRI_2 2
442#define RX_QUEUE_PRI_3 3
443#define RX_QUEUE_PRI_4 4
444#define RX_QUEUE_PRI_5 5
445#define RX_QUEUE_PRI_6 6
446#define RX_QUEUE_PRI_7 7 /* lowest */
447
448 u64 rx_w_round_robin_0;
449 u64 rx_w_round_robin_1;
450 u64 rx_w_round_robin_2;
451 u64 rx_w_round_robin_3;
452 u64 rx_w_round_robin_4;
453
454 /* Per-ring controller regs */
455#define RX_MAX_RINGS 8
456#if 0
457#define RX_MAX_RINGS_SZ 0xFFFF /* 65536 */
458#define RX_MIN_RINGS_SZ 0x3F /* 63 */
459#endif
460 u64 prc_rxd0_n[RX_MAX_RINGS];
461 u64 prc_ctrl_n[RX_MAX_RINGS];
462#define PRC_CTRL_RC_ENABLED BIT(7)
463#define PRC_CTRL_RING_MODE (BIT(14)|BIT(15))
464#define PRC_CTRL_RING_MODE_1 vBIT(0,14,2)
465#define PRC_CTRL_RING_MODE_3 vBIT(1,14,2)
466#define PRC_CTRL_RING_MODE_5 vBIT(2,14,2)
467#define PRC_CTRL_RING_MODE_x vBIT(3,14,2)
468#define PRC_CTRL_NO_SNOOP (BIT(22)|BIT(23))
469#define PRC_CTRL_NO_SNOOP_DESC BIT(22)
470#define PRC_CTRL_NO_SNOOP_BUFF BIT(23)
471#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
472
473 u64 prc_alarm_action;
474#define PRC_ALARM_ACTION_RR_R0_STOP BIT(3)
475#define PRC_ALARM_ACTION_RW_R0_STOP BIT(7)
476#define PRC_ALARM_ACTION_RR_R1_STOP BIT(11)
477#define PRC_ALARM_ACTION_RW_R1_STOP BIT(15)
478#define PRC_ALARM_ACTION_RR_R2_STOP BIT(19)
479#define PRC_ALARM_ACTION_RW_R2_STOP BIT(23)
480#define PRC_ALARM_ACTION_RR_R3_STOP BIT(27)
481#define PRC_ALARM_ACTION_RW_R3_STOP BIT(31)
482#define PRC_ALARM_ACTION_RR_R4_STOP BIT(35)
483#define PRC_ALARM_ACTION_RW_R4_STOP BIT(39)
484#define PRC_ALARM_ACTION_RR_R5_STOP BIT(43)
485#define PRC_ALARM_ACTION_RW_R5_STOP BIT(47)
486#define PRC_ALARM_ACTION_RR_R6_STOP BIT(51)
487#define PRC_ALARM_ACTION_RW_R6_STOP BIT(55)
488#define PRC_ALARM_ACTION_RR_R7_STOP BIT(59)
489#define PRC_ALARM_ACTION_RW_R7_STOP BIT(63)
490
491/* Receive traffic interrupts */
492 u64 rti_command_mem;
493#define RTI_CMD_MEM_WE BIT(7)
494#define RTI_CMD_MEM_STROBE BIT(15)
495#define RTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
496#define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15)
497#define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3)
498
499 u64 rti_data1_mem;
500#define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29)
501#define RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38)
502#define RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39)
503#define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7)
504#define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7)
505#define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7)
506
507 u64 rti_data2_mem;
508#define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16)
509#define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16)
510#define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16)
511#define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16)
512
513 u64 rx_pa_cfg;
514#define RX_PA_CFG_IGNORE_FRM_ERR BIT(1)
515#define RX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
516#define RX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
517#define RX_PA_CFG_IGNORE_L2_ERR BIT(6)
518
519 u8 unused12[0x700 - 0x1D8];
520
521 u64 rxdma_debug_ctrl;
522
523 u8 unused13[0x2000 - 0x1f08];
524
525/* Media Access Controller Register */
526 u64 mac_int_status;
527 u64 mac_int_mask;
528#define MAC_INT_STATUS_TMAC_INT BIT(0)
529#define MAC_INT_STATUS_RMAC_INT BIT(1)
530
531 u64 mac_tmac_err_reg;
532#define TMAC_ERR_REG_TMAC_ECC_DB_ERR BIT(15)
533#define TMAC_ERR_REG_TMAC_TX_BUF_OVRN BIT(23)
534#define TMAC_ERR_REG_TMAC_TX_CRI_ERR BIT(31)
535 u64 mac_tmac_err_mask;
536 u64 mac_tmac_err_alarm;
537
538 u64 mac_rmac_err_reg;
539#define RMAC_ERR_REG_RX_BUFF_OVRN BIT(0)
540#define RMAC_ERR_REG_RTS_ECC_DB_ERR BIT(14)
541#define RMAC_ERR_REG_ECC_DB_ERR BIT(15)
542#define RMAC_LINK_STATE_CHANGE_INT BIT(31)
543 u64 mac_rmac_err_mask;
544 u64 mac_rmac_err_alarm;
545
546 u8 unused14[0x100 - 0x40];
547
548 u64 mac_cfg;
549#define MAC_CFG_TMAC_ENABLE BIT(0)
550#define MAC_CFG_RMAC_ENABLE BIT(1)
551#define MAC_CFG_LAN_NOT_WAN BIT(2)
552#define MAC_CFG_TMAC_LOOPBACK BIT(3)
553#define MAC_CFG_TMAC_APPEND_PAD BIT(4)
554#define MAC_CFG_RMAC_STRIP_FCS BIT(5)
555#define MAC_CFG_RMAC_STRIP_PAD BIT(6)
556#define MAC_CFG_RMAC_PROM_ENABLE BIT(7)
557#define MAC_RMAC_DISCARD_PFRM BIT(8)
558#define MAC_RMAC_BCAST_ENABLE BIT(9)
559#define MAC_RMAC_ALL_ADDR_ENABLE BIT(10)
560#define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8)
561
562 u64 tmac_avg_ipg;
563#define TMAC_AVG_IPG(val) vBIT(val,0,8)
564
565 u64 rmac_max_pyld_len;
566#define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14)
567#define RMAC_MAX_PYLD_LEN_DEF vBIT(1500,2,14)
568#define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14)
569
570 u64 rmac_err_cfg;
571#define RMAC_ERR_FCS BIT(0)
572#define RMAC_ERR_FCS_ACCEPT BIT(1)
573#define RMAC_ERR_TOO_LONG BIT(1)
574#define RMAC_ERR_TOO_LONG_ACCEPT BIT(1)
575#define RMAC_ERR_RUNT BIT(2)
576#define RMAC_ERR_RUNT_ACCEPT BIT(2)
577#define RMAC_ERR_LEN_MISMATCH BIT(3)
578#define RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3)
579
580 u64 rmac_cfg_key;
581#define RMAC_CFG_KEY(val) vBIT(val,0,16)
582
583#define MAX_MAC_ADDRESSES 16
584#define MAX_MC_ADDRESSES 32 /* Multicast addresses */
585#define MAC_MAC_ADDR_START_OFFSET 0
586#define MAC_MC_ADDR_START_OFFSET 16
587#define MAC_MC_ALL_MC_ADDR_OFFSET 63 /* enables all multicast pkts */
588 u64 rmac_addr_cmd_mem;
589#define RMAC_ADDR_CMD_MEM_WE BIT(7)
590#define RMAC_ADDR_CMD_MEM_RD 0
591#define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15)
592#define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15)
593#define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6)
594
595 u64 rmac_addr_data0_mem;
596#define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48)
597#define RMAC_ADDR_DATA0_MEM_USER BIT(48)
598
599 u64 rmac_addr_data1_mem;
600#define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48)
601
602 u8 unused15[0x8];
603
604/*
605 u64 rmac_addr_cfg;
606#define RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n)
607#define RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n)
608#define RMAC_ADDR_BCAST_EN vBIT(0)_48
609#define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49
610*/
611 u64 tmac_ipg_cfg;
612
613 u64 rmac_pause_cfg;
614#define RMAC_PAUSE_GEN BIT(0)
615#define RMAC_PAUSE_GEN_ENABLE BIT(0)
616#define RMAC_PAUSE_RX BIT(1)
617#define RMAC_PAUSE_RX_ENABLE BIT(1)
618#define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16)
619#define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16)
620
621 u64 rmac_red_cfg;
622
623 u64 rmac_red_rate_q0q3;
624 u64 rmac_red_rate_q4q7;
625
626 u64 mac_link_util;
627#define MAC_TX_LINK_UTIL vBIT(0xFE,1,7)
628#define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4)
629#define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4)
630#define MAC_RX_LINK_UTIL vBIT(0xFE,33,7)
631#define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4)
632#define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4)
633
634#define MAC_LINK_UTIL_DISABLE MAC_TX_LINK_UTIL_DISABLE | \
635 MAC_RX_LINK_UTIL_DISABLE
636
637 u64 rmac_invalid_ipg;
638
639/* rx traffic steering */
640#define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14)
641 u64 rts_frm_len_n[8];
642
643 u64 rts_qos_steering;
644
645#define MAX_DIX_MAP 4
646 u64 rts_dix_map_n[MAX_DIX_MAP];
647#define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16)
648#define RTS_DIX_MAP_SCW(val) BIT(val,21)
649
650 u64 rts_q_alternates;
651 u64 rts_default_q;
652
653 u64 rts_ctrl;
654#define RTS_CTRL_IGNORE_SNAP_OUI BIT(2)
655#define RTS_CTRL_IGNORE_LLC_CTRL BIT(3)
656
657 u64 rts_pn_cam_ctrl;
658#define RTS_PN_CAM_CTRL_WE BIT(7)
659#define RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15)
660#define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15)
661#define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8)
662 u64 rts_pn_cam_data;
663#define RTS_PN_CAM_DATA_TCP_SELECT BIT(7)
664#define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16)
665#define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8)
666
667 u64 rts_ds_mem_ctrl;
668#define RTS_DS_MEM_CTRL_WE BIT(7)
669#define RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15)
670#define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15)
671#define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6)
672 u64 rts_ds_mem_data;
673#define RTS_DS_MEM_DATA(n) vBIT(n,0,8)
674
675 u8 unused16[0x700 - 0x220];
676
677 u64 mac_debug_ctrl;
678#define MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL
679
680 u8 unused17[0x2800 - 0x2708];
681
682/* memory controller registers */
683 u64 mc_int_status;
684#define MC_INT_STATUS_MC_INT BIT(0)
685 u64 mc_int_mask;
686#define MC_INT_MASK_MC_INT BIT(0)
687
688 u64 mc_err_reg;
689#define MC_ERR_REG_ECC_DB_ERR_L BIT(14)
690#define MC_ERR_REG_ECC_DB_ERR_U BIT(15)
691#define MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22)
692#define MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23)
693#define MC_ERR_REG_SM_ERR BIT(31)
694 u64 mc_err_mask;
695 u64 mc_err_alarm;
696
697 u8 unused18[0x100 - 0x28];
698
699/* MC configuration */
700 u64 rx_queue_cfg;
701#define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8)
702#define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8)
703#define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8)
704#define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8)
705#define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8)
706#define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8)
707#define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8)
708#define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8)
709
710 u64 mc_rldram_mrs;
711#define MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39)
712#define MC_RLDRAM_MRS_ENABLE BIT(47)
713
714 u64 mc_rldram_interleave;
715
716 u64 mc_pause_thresh_q0q3;
717 u64 mc_pause_thresh_q4q7;
718
719 u64 mc_red_thresh_q[8];
720
721 u8 unused19[0x200 - 0x168];
722 u64 mc_rldram_ref_per;
723 u8 unused20[0x220 - 0x208];
724 u64 mc_rldram_test_ctrl;
725#define MC_RLDRAM_TEST_MODE BIT(47)
726#define MC_RLDRAM_TEST_WRITE BIT(7)
727#define MC_RLDRAM_TEST_GO BIT(15)
728#define MC_RLDRAM_TEST_DONE BIT(23)
729#define MC_RLDRAM_TEST_PASS BIT(31)
730
731 u8 unused21[0x240 - 0x228];
732 u64 mc_rldram_test_add;
733 u8 unused22[0x260 - 0x248];
734 u64 mc_rldram_test_d0;
735 u8 unused23[0x280 - 0x268];
736 u64 mc_rldram_test_d1;
737 u8 unused24[0x300 - 0x288];
738 u64 mc_rldram_test_d2;
739 u8 unused25[0x700 - 0x308];
740 u64 mc_debug_ctrl;
741
742 u8 unused26[0x3000 - 0x2f08];
743
744/* XGXG */
745 /* XGXS control registers */
746
747 u64 xgxs_int_status;
748#define XGXS_INT_STATUS_TXGXS BIT(0)
749#define XGXS_INT_STATUS_RXGXS BIT(1)
750 u64 xgxs_int_mask;
751#define XGXS_INT_MASK_TXGXS BIT(0)
752#define XGXS_INT_MASK_RXGXS BIT(1)
753
754 u64 xgxs_txgxs_err_reg;
755#define TXGXS_ECC_DB_ERR BIT(15)
756 u64 xgxs_txgxs_err_mask;
757 u64 xgxs_txgxs_err_alarm;
758
759 u64 xgxs_rxgxs_err_reg;
760 u64 xgxs_rxgxs_err_mask;
761 u64 xgxs_rxgxs_err_alarm;
762
763 u8 unused27[0x100 - 0x40];
764
765 u64 xgxs_cfg;
766 u64 xgxs_status;
767
768 u64 xgxs_cfg_key;
769 u64 xgxs_efifo_cfg; /* CHANGED */
770 u64 rxgxs_ber_0; /* CHANGED */
771 u64 rxgxs_ber_1; /* CHANGED */
772
773} XENA_dev_config_t;
774
775#define XENA_REG_SPACE sizeof(XENA_dev_config_t)
776#define XENA_EEPROM_SPACE (0x01 << 11)
777
778#endif /* _REGS_H */