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Diffstat (limited to 'drivers/net/r8169.c')
-rw-r--r--drivers/net/r8169.c660
1 files changed, 382 insertions, 278 deletions
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index d9b960aa9b0d..4c47c5b10ba0 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -6,26 +6,26 @@
6 History: 6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>. 7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support. 8 May 20 2002 - Add link status force-mode and TBI mode support.
9 2004 - Massive updates. See kernel SCM system for details. 9 2004 - Massive updates. See kernel SCM system for details.
10========================================================================= 10=========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes. 11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA' 12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex. 13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
14 14
15 SET_MEDIA can be: 15 SET_MEDIA can be:
16 _10_Half = 0x01 16 _10_Half = 0x01
17 _10_Full = 0x02 17 _10_Full = 0x02
18 _100_Half = 0x04 18 _100_Half = 0x04
19 _100_Full = 0x08 19 _100_Full = 0x08
20 _1000_Full = 0x10 20 _1000_Full = 0x10
21 21
22 2. Support TBI mode. 22 2. Support TBI mode.
23========================================================================= 23=========================================================================
24VERSION 1.1 <2002/10/4> 24VERSION 1.1 <2002/10/4>
25 25
26 The bit4:0 of MII register 4 is called "selector field", and have to be 26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of 27 00001b to indicate support of IEEE std 802.3 during NWay process of
28 exchanging Link Code Word (FLP). 28 exchanging Link Code Word (FLP).
29 29
30VERSION 1.2 <2002/11/30> 30VERSION 1.2 <2002/11/30>
31 31
@@ -81,10 +81,10 @@ VERSION 2.2LK <2005/01/25>
81 81
82#ifdef RTL8169_DEBUG 82#ifdef RTL8169_DEBUG
83#define assert(expr) \ 83#define assert(expr) \
84 if(!(expr)) { \ 84 if (!(expr)) { \
85 printk( "Assertion failed! %s,%s,%s,line=%d\n", \ 85 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
86 #expr,__FILE__,__FUNCTION__,__LINE__); \ 86 #expr,__FILE__,__FUNCTION__,__LINE__); \
87 } 87 }
88#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0) 88#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
89#else 89#else
90#define assert(expr) do {} while (0) 90#define assert(expr) do {} while (0)
@@ -150,11 +150,16 @@ static const int multicast_filter_limit = 32;
150#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) 150#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
151 151
152enum mac_version { 152enum mac_version {
153 RTL_GIGA_MAC_VER_B = 0x00, 153 RTL_GIGA_MAC_VER_01 = 0x00,
154 /* RTL_GIGA_MAC_VER_C = 0x03, */ 154 RTL_GIGA_MAC_VER_02 = 0x01,
155 RTL_GIGA_MAC_VER_D = 0x01, 155 RTL_GIGA_MAC_VER_03 = 0x02,
156 RTL_GIGA_MAC_VER_E = 0x02, 156 RTL_GIGA_MAC_VER_04 = 0x03,
157 RTL_GIGA_MAC_VER_X = 0x04 /* Greater than RTL_GIGA_MAC_VER_E */ 157 RTL_GIGA_MAC_VER_05 = 0x04,
158 RTL_GIGA_MAC_VER_11 = 0x0b,
159 RTL_GIGA_MAC_VER_12 = 0x0c,
160 RTL_GIGA_MAC_VER_13 = 0x0d,
161 RTL_GIGA_MAC_VER_14 = 0x0e,
162 RTL_GIGA_MAC_VER_15 = 0x0f
158}; 163};
159 164
160enum phy_version { 165enum phy_version {
@@ -166,7 +171,6 @@ enum phy_version {
166 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */ 171 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
167}; 172};
168 173
169
170#define _R(NAME,MAC,MASK) \ 174#define _R(NAME,MAC,MASK) \
171 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } 175 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
172 176
@@ -175,19 +179,44 @@ static const struct {
175 u8 mac_version; 179 u8 mac_version;
176 u32 RxConfigMask; /* Clears the bits supported by this chip */ 180 u32 RxConfigMask; /* Clears the bits supported by this chip */
177} rtl_chip_info[] = { 181} rtl_chip_info[] = {
178 _R("RTL8169", RTL_GIGA_MAC_VER_B, 0xff7e1880), 182 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880),
179 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_D, 0xff7e1880), 183 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_02, 0xff7e1880),
180 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_E, 0xff7e1880), 184 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880),
181 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_X, 0xff7e1880), 185 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880),
186 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880),
187 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
188 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
189 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
190 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
191 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
182}; 192};
183#undef _R 193#undef _R
184 194
195enum cfg_version {
196 RTL_CFG_0 = 0x00,
197 RTL_CFG_1,
198 RTL_CFG_2
199};
200
201static const struct {
202 unsigned int region;
203 unsigned int align;
204} rtl_cfg_info[] = {
205 [RTL_CFG_0] = { 1, NET_IP_ALIGN },
206 [RTL_CFG_1] = { 2, NET_IP_ALIGN },
207 [RTL_CFG_2] = { 2, 8 }
208};
209
185static struct pci_device_id rtl8169_pci_tbl[] = { 210static struct pci_device_id rtl8169_pci_tbl[] = {
186 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), }, 211 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
187 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), }, 212 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
188 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), }, 213 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
189 { PCI_DEVICE(0x16ec, 0x0116), }, 214 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_2 },
190 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024, }, 215 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
216 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
217 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
218 { PCI_VENDOR_ID_LINKSYS, 0x1032,
219 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
191 {0,}, 220 {0,},
192}; 221};
193 222
@@ -257,10 +286,11 @@ enum RTL8169_register_content {
257 RxOK = 0x01, 286 RxOK = 0x01,
258 287
259 /* RxStatusDesc */ 288 /* RxStatusDesc */
260 RxRES = 0x00200000, 289 RxFOVF = (1 << 23),
261 RxCRC = 0x00080000, 290 RxRWT = (1 << 22),
262 RxRUNT = 0x00100000, 291 RxRES = (1 << 21),
263 RxRWT = 0x00400000, 292 RxRUNT = (1 << 20),
293 RxCRC = (1 << 19),
264 294
265 /* ChipCmdBits */ 295 /* ChipCmdBits */
266 CmdReset = 0x10, 296 CmdReset = 0x10,
@@ -326,30 +356,6 @@ enum RTL8169_register_content {
326 LinkStatus = 0x02, 356 LinkStatus = 0x02,
327 FullDup = 0x01, 357 FullDup = 0x01,
328 358
329 /* GIGABIT_PHY_registers */
330 PHY_CTRL_REG = 0,
331 PHY_STAT_REG = 1,
332 PHY_AUTO_NEGO_REG = 4,
333 PHY_1000_CTRL_REG = 9,
334
335 /* GIGABIT_PHY_REG_BIT */
336 PHY_Restart_Auto_Nego = 0x0200,
337 PHY_Enable_Auto_Nego = 0x1000,
338
339 /* PHY_STAT_REG = 1 */
340 PHY_Auto_Neco_Comp = 0x0020,
341
342 /* PHY_AUTO_NEGO_REG = 4 */
343 PHY_Cap_10_Half = 0x0020,
344 PHY_Cap_10_Full = 0x0040,
345 PHY_Cap_100_Half = 0x0080,
346 PHY_Cap_100_Full = 0x0100,
347
348 /* PHY_1000_CTRL_REG = 9 */
349 PHY_Cap_1000_Full = 0x0200,
350
351 PHY_Cap_Null = 0x0,
352
353 /* _MediaType */ 359 /* _MediaType */
354 _10_Half = 0x01, 360 _10_Half = 0x01,
355 _10_Full = 0x02, 361 _10_Full = 0x02,
@@ -433,6 +439,7 @@ struct rtl8169_private {
433 dma_addr_t RxPhyAddr; 439 dma_addr_t RxPhyAddr;
434 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */ 440 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
435 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 441 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
442 unsigned align;
436 unsigned rx_buf_sz; 443 unsigned rx_buf_sz;
437 struct timer_list timer; 444 struct timer_list timer;
438 u16 cp_cmd; 445 u16 cp_cmd;
@@ -488,12 +495,7 @@ static const u16 rtl8169_intr_mask =
488static const u16 rtl8169_napi_event = 495static const u16 rtl8169_napi_event =
489 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr; 496 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
490static const unsigned int rtl8169_rx_config = 497static const unsigned int rtl8169_rx_config =
491 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 498 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
492
493#define PHY_Cap_10_Half_Or_Less PHY_Cap_10_Half
494#define PHY_Cap_10_Full_Or_Less PHY_Cap_10_Full | PHY_Cap_10_Half_Or_Less
495#define PHY_Cap_100_Half_Or_Less PHY_Cap_100_Half | PHY_Cap_10_Full_Or_Less
496#define PHY_Cap_100_Full_Or_Less PHY_Cap_100_Full | PHY_Cap_100_Half_Or_Less
497 499
498static void mdio_write(void __iomem *ioaddr, int RegAddr, int value) 500static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
499{ 501{
@@ -503,7 +505,7 @@ static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
503 505
504 for (i = 20; i > 0; i--) { 506 for (i = 20; i > 0; i--) {
505 /* Check if the RTL8169 has completed writing to the specified MII register */ 507 /* Check if the RTL8169 has completed writing to the specified MII register */
506 if (!(RTL_R32(PHYAR) & 0x80000000)) 508 if (!(RTL_R32(PHYAR) & 0x80000000))
507 break; 509 break;
508 udelay(25); 510 udelay(25);
509 } 511 }
@@ -547,7 +549,7 @@ static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
547 549
548static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr) 550static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
549{ 551{
550 return mdio_read(ioaddr, 0) & 0x8000; 552 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
551} 553}
552 554
553static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) 555static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
@@ -569,8 +571,8 @@ static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
569{ 571{
570 unsigned int val; 572 unsigned int val;
571 573
572 val = (mdio_read(ioaddr, PHY_CTRL_REG) | 0x8000) & 0xffff; 574 val = (mdio_read(ioaddr, MII_BMCR) | BMCR_RESET) & 0xffff;
573 mdio_write(ioaddr, PHY_CTRL_REG, val); 575 mdio_write(ioaddr, MII_BMCR, val);
574} 576}
575 577
576static void rtl8169_check_link_status(struct net_device *dev, 578static void rtl8169_check_link_status(struct net_device *dev,
@@ -608,7 +610,7 @@ static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
608 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff } 610 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
609 }, *p; 611 }, *p;
610 unsigned char option; 612 unsigned char option;
611 613
612 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff; 614 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
613 615
614 if ((option != 0xff) && !idx && netif_msg_drv(&debug)) 616 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
@@ -650,9 +652,9 @@ static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
650 if (options & UWF) 652 if (options & UWF)
651 wol->wolopts |= WAKE_UCAST; 653 wol->wolopts |= WAKE_UCAST;
652 if (options & BWF) 654 if (options & BWF)
653 wol->wolopts |= WAKE_BCAST; 655 wol->wolopts |= WAKE_BCAST;
654 if (options & MWF) 656 if (options & MWF)
655 wol->wolopts |= WAKE_MCAST; 657 wol->wolopts |= WAKE_MCAST;
656 658
657out_unlock: 659out_unlock:
658 spin_unlock_irq(&tp->lock); 660 spin_unlock_irq(&tp->lock);
@@ -745,38 +747,57 @@ static int rtl8169_set_speed_xmii(struct net_device *dev,
745 void __iomem *ioaddr = tp->mmio_addr; 747 void __iomem *ioaddr = tp->mmio_addr;
746 int auto_nego, giga_ctrl; 748 int auto_nego, giga_ctrl;
747 749
748 auto_nego = mdio_read(ioaddr, PHY_AUTO_NEGO_REG); 750 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
749 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_10_Full | 751 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
750 PHY_Cap_100_Half | PHY_Cap_100_Full); 752 ADVERTISE_100HALF | ADVERTISE_100FULL);
751 giga_ctrl = mdio_read(ioaddr, PHY_1000_CTRL_REG); 753 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
752 giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_Null); 754 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
753 755
754 if (autoneg == AUTONEG_ENABLE) { 756 if (autoneg == AUTONEG_ENABLE) {
755 auto_nego |= (PHY_Cap_10_Half | PHY_Cap_10_Full | 757 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
756 PHY_Cap_100_Half | PHY_Cap_100_Full); 758 ADVERTISE_100HALF | ADVERTISE_100FULL);
757 giga_ctrl |= PHY_Cap_1000_Full; 759 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
758 } else { 760 } else {
759 if (speed == SPEED_10) 761 if (speed == SPEED_10)
760 auto_nego |= PHY_Cap_10_Half | PHY_Cap_10_Full; 762 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
761 else if (speed == SPEED_100) 763 else if (speed == SPEED_100)
762 auto_nego |= PHY_Cap_100_Half | PHY_Cap_100_Full; 764 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
763 else if (speed == SPEED_1000) 765 else if (speed == SPEED_1000)
764 giga_ctrl |= PHY_Cap_1000_Full; 766 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
765 767
766 if (duplex == DUPLEX_HALF) 768 if (duplex == DUPLEX_HALF)
767 auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full); 769 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
768 770
769 if (duplex == DUPLEX_FULL) 771 if (duplex == DUPLEX_FULL)
770 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_100_Half); 772 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
773
774 /* This tweak comes straight from Realtek's driver. */
775 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
776 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
777 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
778 }
779 }
780
781 /* The 8100e/8101e do Fast Ethernet only. */
782 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
783 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
784 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
785 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
786 netif_msg_link(tp)) {
787 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
788 dev->name);
789 }
790 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
771 } 791 }
772 792
793 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
794
773 tp->phy_auto_nego_reg = auto_nego; 795 tp->phy_auto_nego_reg = auto_nego;
774 tp->phy_1000_ctrl_reg = giga_ctrl; 796 tp->phy_1000_ctrl_reg = giga_ctrl;
775 797
776 mdio_write(ioaddr, PHY_AUTO_NEGO_REG, auto_nego); 798 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
777 mdio_write(ioaddr, PHY_1000_CTRL_REG, giga_ctrl); 799 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
778 mdio_write(ioaddr, PHY_CTRL_REG, PHY_Enable_Auto_Nego | 800 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
779 PHY_Restart_Auto_Nego);
780 return 0; 801 return 0;
781} 802}
782 803
@@ -788,7 +809,7 @@ static int rtl8169_set_speed(struct net_device *dev,
788 809
789 ret = tp->set_speed(dev, autoneg, speed, duplex); 810 ret = tp->set_speed(dev, autoneg, speed, duplex);
790 811
791 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full)) 812 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
792 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); 813 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
793 814
794 return ret; 815 return ret;
@@ -803,7 +824,7 @@ static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
803 spin_lock_irqsave(&tp->lock, flags); 824 spin_lock_irqsave(&tp->lock, flags);
804 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex); 825 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
805 spin_unlock_irqrestore(&tp->lock, flags); 826 spin_unlock_irqrestore(&tp->lock, flags);
806 827
807 return ret; 828 return ret;
808} 829}
809 830
@@ -936,20 +957,20 @@ static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
936 SUPPORTED_100baseT_Full | 957 SUPPORTED_100baseT_Full |
937 SUPPORTED_1000baseT_Full | 958 SUPPORTED_1000baseT_Full |
938 SUPPORTED_Autoneg | 959 SUPPORTED_Autoneg |
939 SUPPORTED_TP; 960 SUPPORTED_TP;
940 961
941 cmd->autoneg = 1; 962 cmd->autoneg = 1;
942 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg; 963 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
943 964
944 if (tp->phy_auto_nego_reg & PHY_Cap_10_Half) 965 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
945 cmd->advertising |= ADVERTISED_10baseT_Half; 966 cmd->advertising |= ADVERTISED_10baseT_Half;
946 if (tp->phy_auto_nego_reg & PHY_Cap_10_Full) 967 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
947 cmd->advertising |= ADVERTISED_10baseT_Full; 968 cmd->advertising |= ADVERTISED_10baseT_Full;
948 if (tp->phy_auto_nego_reg & PHY_Cap_100_Half) 969 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
949 cmd->advertising |= ADVERTISED_100baseT_Half; 970 cmd->advertising |= ADVERTISED_100baseT_Half;
950 if (tp->phy_auto_nego_reg & PHY_Cap_100_Full) 971 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
951 cmd->advertising |= ADVERTISED_100baseT_Full; 972 cmd->advertising |= ADVERTISED_100baseT_Full;
952 if (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full) 973 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
953 cmd->advertising |= ADVERTISED_1000baseT_Full; 974 cmd->advertising |= ADVERTISED_1000baseT_Full;
954 975
955 status = RTL_R8(PHYstatus); 976 status = RTL_R8(PHYstatus);
@@ -961,6 +982,11 @@ static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
961 else if (status & _10bps) 982 else if (status & _10bps)
962 cmd->speed = SPEED_10; 983 cmd->speed = SPEED_10;
963 984
985 if (status & TxFlowCtrl)
986 cmd->advertising |= ADVERTISED_Asym_Pause;
987 if (status & RxFlowCtrl)
988 cmd->advertising |= ADVERTISED_Pause;
989
964 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ? 990 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
965 DUPLEX_FULL : DUPLEX_HALF; 991 DUPLEX_FULL : DUPLEX_HALF;
966} 992}
@@ -981,15 +1007,15 @@ static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
981static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1007static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
982 void *p) 1008 void *p)
983{ 1009{
984 struct rtl8169_private *tp = netdev_priv(dev); 1010 struct rtl8169_private *tp = netdev_priv(dev);
985 unsigned long flags; 1011 unsigned long flags;
986 1012
987 if (regs->len > R8169_REGS_SIZE) 1013 if (regs->len > R8169_REGS_SIZE)
988 regs->len = R8169_REGS_SIZE; 1014 regs->len = R8169_REGS_SIZE;
989 1015
990 spin_lock_irqsave(&tp->lock, flags); 1016 spin_lock_irqsave(&tp->lock, flags);
991 memcpy_fromio(p, tp->mmio_addr, regs->len); 1017 memcpy_fromio(p, tp->mmio_addr, regs->len);
992 spin_unlock_irqrestore(&tp->lock, flags); 1018 spin_unlock_irqrestore(&tp->lock, flags);
993} 1019}
994 1020
995static u32 rtl8169_get_msglevel(struct net_device *dev) 1021static u32 rtl8169_get_msglevel(struct net_device *dev)
@@ -1071,7 +1097,7 @@ static void rtl8169_get_ethtool_stats(struct net_device *dev,
1071 RTL_W32(CounterAddrLow, 0); 1097 RTL_W32(CounterAddrLow, 0);
1072 RTL_W32(CounterAddrHigh, 0); 1098 RTL_W32(CounterAddrHigh, 0);
1073 1099
1074 data[0] = le64_to_cpu(counters->tx_packets); 1100 data[0] = le64_to_cpu(counters->tx_packets);
1075 data[1] = le64_to_cpu(counters->rx_packets); 1101 data[1] = le64_to_cpu(counters->rx_packets);
1076 data[2] = le64_to_cpu(counters->tx_errors); 1102 data[2] = le64_to_cpu(counters->tx_errors);
1077 data[3] = le32_to_cpu(counters->rx_errors); 1103 data[3] = le32_to_cpu(counters->rx_errors);
@@ -1098,7 +1124,7 @@ static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1098} 1124}
1099 1125
1100 1126
1101static struct ethtool_ops rtl8169_ethtool_ops = { 1127static const struct ethtool_ops rtl8169_ethtool_ops = {
1102 .get_drvinfo = rtl8169_get_drvinfo, 1128 .get_drvinfo = rtl8169_get_drvinfo,
1103 .get_regs_len = rtl8169_get_regs_len, 1129 .get_regs_len = rtl8169_get_regs_len,
1104 .get_link = ethtool_op_get_link, 1130 .get_link = ethtool_op_get_link,
@@ -1131,7 +1157,7 @@ static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum
1131 val = mdio_read(ioaddr, reg); 1157 val = mdio_read(ioaddr, reg);
1132 val = (bitval == 1) ? 1158 val = (bitval == 1) ?
1133 val | (bitval << bitnum) : val & ~(0x0001 << bitnum); 1159 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1134 mdio_write(ioaddr, reg, val & 0xffff); 1160 mdio_write(ioaddr, reg, val & 0xffff);
1135} 1161}
1136 1162
1137static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr) 1163static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
@@ -1140,10 +1166,16 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *io
1140 u32 mask; 1166 u32 mask;
1141 int mac_version; 1167 int mac_version;
1142 } mac_info[] = { 1168 } mac_info[] = {
1143 { 0x1 << 28, RTL_GIGA_MAC_VER_X }, 1169 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1144 { 0x1 << 26, RTL_GIGA_MAC_VER_E }, 1170 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1145 { 0x1 << 23, RTL_GIGA_MAC_VER_D }, 1171 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1146 { 0x00000000, RTL_GIGA_MAC_VER_B } /* Catch-all */ 1172 { 0x30800000, RTL_GIGA_MAC_VER_14 },
1173 { 0x30000000, RTL_GIGA_MAC_VER_11 },
1174 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1175 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1176 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1177 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1178 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1147 }, *p = mac_info; 1179 }, *p = mac_info;
1148 u32 reg; 1180 u32 reg;
1149 1181
@@ -1155,24 +1187,7 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *io
1155 1187
1156static void rtl8169_print_mac_version(struct rtl8169_private *tp) 1188static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1157{ 1189{
1158 struct { 1190 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1159 int version;
1160 char *msg;
1161 } mac_print[] = {
1162 { RTL_GIGA_MAC_VER_E, "RTL_GIGA_MAC_VER_E" },
1163 { RTL_GIGA_MAC_VER_D, "RTL_GIGA_MAC_VER_D" },
1164 { RTL_GIGA_MAC_VER_B, "RTL_GIGA_MAC_VER_B" },
1165 { 0, NULL }
1166 }, *p;
1167
1168 for (p = mac_print; p->msg; p++) {
1169 if (tp->mac_version == p->version) {
1170 dprintk("mac_version == %s (%04d)\n", p->msg,
1171 p->version);
1172 return;
1173 }
1174 }
1175 dprintk("mac_version == Unknown\n");
1176} 1191}
1177 1192
1178static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr) 1193static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
@@ -1189,7 +1204,7 @@ static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *io
1189 }, *p = phy_info; 1204 }, *p = phy_info;
1190 u16 reg; 1205 u16 reg;
1191 1206
1192 reg = mdio_read(ioaddr, 3) & 0xffff; 1207 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1193 while ((reg & p->mask) != p->set) 1208 while ((reg & p->mask) != p->set)
1194 p++; 1209 p++;
1195 tp->phy_version = p->phy_version; 1210 tp->phy_version = p->phy_version;
@@ -1257,7 +1272,7 @@ static void rtl8169_hw_phy_config(struct net_device *dev)
1257 rtl8169_print_mac_version(tp); 1272 rtl8169_print_mac_version(tp);
1258 rtl8169_print_phy_version(tp); 1273 rtl8169_print_phy_version(tp);
1259 1274
1260 if (tp->mac_version <= RTL_GIGA_MAC_VER_B) 1275 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1261 return; 1276 return;
1262 if (tp->phy_version >= RTL_GIGA_PHY_VER_H) 1277 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1263 return; 1278 return;
@@ -1267,7 +1282,7 @@ static void rtl8169_hw_phy_config(struct net_device *dev)
1267 1282
1268 /* Shazam ! */ 1283 /* Shazam ! */
1269 1284
1270 if (tp->mac_version == RTL_GIGA_MAC_VER_X) { 1285 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1271 mdio_write(ioaddr, 31, 0x0001); 1286 mdio_write(ioaddr, 31, 0x0001);
1272 mdio_write(ioaddr, 9, 0x273a); 1287 mdio_write(ioaddr, 9, 0x273a);
1273 mdio_write(ioaddr, 14, 0x7bfb); 1288 mdio_write(ioaddr, 14, 0x7bfb);
@@ -1306,16 +1321,16 @@ static void rtl8169_phy_timer(unsigned long __opaque)
1306 void __iomem *ioaddr = tp->mmio_addr; 1321 void __iomem *ioaddr = tp->mmio_addr;
1307 unsigned long timeout = RTL8169_PHY_TIMEOUT; 1322 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1308 1323
1309 assert(tp->mac_version > RTL_GIGA_MAC_VER_B); 1324 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1310 assert(tp->phy_version < RTL_GIGA_PHY_VER_H); 1325 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1311 1326
1312 if (!(tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full)) 1327 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1313 return; 1328 return;
1314 1329
1315 spin_lock_irq(&tp->lock); 1330 spin_lock_irq(&tp->lock);
1316 1331
1317 if (tp->phy_reset_pending(ioaddr)) { 1332 if (tp->phy_reset_pending(ioaddr)) {
1318 /* 1333 /*
1319 * A busy loop could burn quite a few cycles on nowadays CPU. 1334 * A busy loop could burn quite a few cycles on nowadays CPU.
1320 * Let's delay the execution of the timer for a few ticks. 1335 * Let's delay the execution of the timer for a few ticks.
1321 */ 1336 */
@@ -1342,7 +1357,7 @@ static inline void rtl8169_delete_timer(struct net_device *dev)
1342 struct rtl8169_private *tp = netdev_priv(dev); 1357 struct rtl8169_private *tp = netdev_priv(dev);
1343 struct timer_list *timer = &tp->timer; 1358 struct timer_list *timer = &tp->timer;
1344 1359
1345 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) || 1360 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1346 (tp->phy_version >= RTL_GIGA_PHY_VER_H)) 1361 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1347 return; 1362 return;
1348 1363
@@ -1354,7 +1369,7 @@ static inline void rtl8169_request_timer(struct net_device *dev)
1354 struct rtl8169_private *tp = netdev_priv(dev); 1369 struct rtl8169_private *tp = netdev_priv(dev);
1355 struct timer_list *timer = &tp->timer; 1370 struct timer_list *timer = &tp->timer;
1356 1371
1357 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) || 1372 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1358 (tp->phy_version >= RTL_GIGA_PHY_VER_H)) 1373 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1359 return; 1374 return;
1360 1375
@@ -1382,6 +1397,41 @@ static void rtl8169_netpoll(struct net_device *dev)
1382} 1397}
1383#endif 1398#endif
1384 1399
1400static void __rtl8169_set_mac_addr(struct net_device *dev, void __iomem *ioaddr)
1401{
1402 unsigned int i, j;
1403
1404 RTL_W8(Cfg9346, Cfg9346_Unlock);
1405 for (i = 0; i < 2; i++) {
1406 __le32 l = 0;
1407
1408 for (j = 0; j < 4; j++) {
1409 l <<= 8;
1410 l |= dev->dev_addr[4*i + j];
1411 }
1412 RTL_W32(MAC0 + 4*i, cpu_to_be32(l));
1413 }
1414 RTL_W8(Cfg9346, Cfg9346_Lock);
1415}
1416
1417static int rtl8169_set_mac_addr(struct net_device *dev, void *p)
1418{
1419 struct rtl8169_private *tp = netdev_priv(dev);
1420 struct sockaddr *addr = p;
1421
1422 if (!is_valid_ether_addr(addr->sa_data))
1423 return -EINVAL;
1424
1425 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1426
1427 if (netif_running(dev)) {
1428 spin_lock_irq(&tp->lock);
1429 __rtl8169_set_mac_addr(dev, tp->mmio_addr);
1430 spin_unlock_irq(&tp->lock);
1431 }
1432 return 0;
1433}
1434
1385static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, 1435static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1386 void __iomem *ioaddr) 1436 void __iomem *ioaddr)
1387{ 1437{
@@ -1391,23 +1441,87 @@ static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1391 free_netdev(dev); 1441 free_netdev(dev);
1392} 1442}
1393 1443
1444static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1445{
1446 void __iomem *ioaddr = tp->mmio_addr;
1447 static int board_idx = -1;
1448 u8 autoneg, duplex;
1449 u16 speed;
1450
1451 board_idx++;
1452
1453 rtl8169_hw_phy_config(dev);
1454
1455 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1456 RTL_W8(0x82, 0x01);
1457
1458 if (tp->mac_version < RTL_GIGA_MAC_VER_03) {
1459 dprintk("Set PCI Latency=0x40\n");
1460 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1461 }
1462
1463 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1464 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1465 RTL_W8(0x82, 0x01);
1466 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1467 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1468 }
1469
1470 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1471
1472 rtl8169_set_speed(dev, autoneg, speed, duplex);
1473
1474 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1475 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1476}
1477
1478static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1479{
1480 struct rtl8169_private *tp = netdev_priv(dev);
1481 struct mii_ioctl_data *data = if_mii(ifr);
1482
1483 if (!netif_running(dev))
1484 return -ENODEV;
1485
1486 switch (cmd) {
1487 case SIOCGMIIPHY:
1488 data->phy_id = 32; /* Internal PHY */
1489 return 0;
1490
1491 case SIOCGMIIREG:
1492 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1493 return 0;
1494
1495 case SIOCSMIIREG:
1496 if (!capable(CAP_NET_ADMIN))
1497 return -EPERM;
1498 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1499 return 0;
1500 }
1501 return -EOPNOTSUPP;
1502}
1503
1394static int __devinit 1504static int __devinit
1395rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out, 1505rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1396 void __iomem **ioaddr_out)
1397{ 1506{
1398 void __iomem *ioaddr; 1507 const unsigned int region = rtl_cfg_info[ent->driver_data].region;
1399 struct net_device *dev;
1400 struct rtl8169_private *tp; 1508 struct rtl8169_private *tp;
1401 int rc = -ENOMEM, i, acpi_idle_state = 0, pm_cap; 1509 struct net_device *dev;
1510 void __iomem *ioaddr;
1511 unsigned int i, pm_cap;
1512 int rc;
1402 1513
1403 assert(ioaddr_out != NULL); 1514 if (netif_msg_drv(&debug)) {
1515 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1516 MODULENAME, RTL8169_VERSION);
1517 }
1404 1518
1405 /* dev zeroed in alloc_etherdev */
1406 dev = alloc_etherdev(sizeof (*tp)); 1519 dev = alloc_etherdev(sizeof (*tp));
1407 if (dev == NULL) { 1520 if (!dev) {
1408 if (netif_msg_drv(&debug)) 1521 if (netif_msg_drv(&debug))
1409 dev_err(&pdev->dev, "unable to alloc new ethernet\n"); 1522 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1410 goto err_out; 1523 rc = -ENOMEM;
1524 goto out;
1411 } 1525 }
1412 1526
1413 SET_MODULE_OWNER(dev); 1527 SET_MODULE_OWNER(dev);
@@ -1420,48 +1534,53 @@ rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1420 if (rc < 0) { 1534 if (rc < 0) {
1421 if (netif_msg_probe(tp)) 1535 if (netif_msg_probe(tp))
1422 dev_err(&pdev->dev, "enable failure\n"); 1536 dev_err(&pdev->dev, "enable failure\n");
1423 goto err_out_free_dev; 1537 goto err_out_free_dev_1;
1424 } 1538 }
1425 1539
1426 rc = pci_set_mwi(pdev); 1540 rc = pci_set_mwi(pdev);
1427 if (rc < 0) 1541 if (rc < 0)
1428 goto err_out_disable; 1542 goto err_out_disable_2;
1429 1543
1430 /* save power state before pci_enable_device overwrites it */ 1544 /* save power state before pci_enable_device overwrites it */
1431 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 1545 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1432 if (pm_cap) { 1546 if (pm_cap) {
1433 u16 pwr_command; 1547 u16 pwr_command, acpi_idle_state;
1434 1548
1435 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command); 1549 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1436 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK; 1550 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1437 } else { 1551 } else {
1438 if (netif_msg_probe(tp)) 1552 if (netif_msg_probe(tp)) {
1439 dev_err(&pdev->dev, 1553 dev_err(&pdev->dev,
1440 "PowerManagement capability not found.\n"); 1554 "PowerManagement capability not found.\n");
1555 }
1441 } 1556 }
1442 1557
1443 /* make sure PCI base addr 1 is MMIO */ 1558 /* make sure PCI base addr 1 is MMIO */
1444 if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) { 1559 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1445 if (netif_msg_probe(tp)) 1560 if (netif_msg_probe(tp)) {
1446 dev_err(&pdev->dev, 1561 dev_err(&pdev->dev,
1447 "region #1 not an MMIO resource, aborting\n"); 1562 "region #%d not an MMIO resource, aborting\n",
1563 region);
1564 }
1448 rc = -ENODEV; 1565 rc = -ENODEV;
1449 goto err_out_mwi; 1566 goto err_out_mwi_3;
1450 } 1567 }
1568
1451 /* check for weird/broken PCI region reporting */ 1569 /* check for weird/broken PCI region reporting */
1452 if (pci_resource_len(pdev, 1) < R8169_REGS_SIZE) { 1570 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1453 if (netif_msg_probe(tp)) 1571 if (netif_msg_probe(tp)) {
1454 dev_err(&pdev->dev, 1572 dev_err(&pdev->dev,
1455 "Invalid PCI region size(s), aborting\n"); 1573 "Invalid PCI region size(s), aborting\n");
1574 }
1456 rc = -ENODEV; 1575 rc = -ENODEV;
1457 goto err_out_mwi; 1576 goto err_out_mwi_3;
1458 } 1577 }
1459 1578
1460 rc = pci_request_regions(pdev, MODULENAME); 1579 rc = pci_request_regions(pdev, MODULENAME);
1461 if (rc < 0) { 1580 if (rc < 0) {
1462 if (netif_msg_probe(tp)) 1581 if (netif_msg_probe(tp))
1463 dev_err(&pdev->dev, "could not request regions.\n"); 1582 dev_err(&pdev->dev, "could not request regions.\n");
1464 goto err_out_mwi; 1583 goto err_out_mwi_3;
1465 } 1584 }
1466 1585
1467 tp->cp_cmd = PCIMulRW | RxChkSum; 1586 tp->cp_cmd = PCIMulRW | RxChkSum;
@@ -1473,22 +1592,23 @@ rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1473 } else { 1592 } else {
1474 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 1593 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1475 if (rc < 0) { 1594 if (rc < 0) {
1476 if (netif_msg_probe(tp)) 1595 if (netif_msg_probe(tp)) {
1477 dev_err(&pdev->dev, 1596 dev_err(&pdev->dev,
1478 "DMA configuration failed.\n"); 1597 "DMA configuration failed.\n");
1479 goto err_out_free_res; 1598 }
1599 goto err_out_free_res_4;
1480 } 1600 }
1481 } 1601 }
1482 1602
1483 pci_set_master(pdev); 1603 pci_set_master(pdev);
1484 1604
1485 /* ioremap MMIO region */ 1605 /* ioremap MMIO region */
1486 ioaddr = ioremap(pci_resource_start(pdev, 1), R8169_REGS_SIZE); 1606 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1487 if (ioaddr == NULL) { 1607 if (!ioaddr) {
1488 if (netif_msg_probe(tp)) 1608 if (netif_msg_probe(tp))
1489 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 1609 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1490 rc = -EIO; 1610 rc = -EIO;
1491 goto err_out_free_res; 1611 goto err_out_free_res_4;
1492 } 1612 }
1493 1613
1494 /* Unneeded ? Don't mess with Mrs. Murphy. */ 1614 /* Unneeded ? Don't mess with Mrs. Murphy. */
@@ -1498,10 +1618,10 @@ rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1498 RTL_W8(ChipCmd, CmdReset); 1618 RTL_W8(ChipCmd, CmdReset);
1499 1619
1500 /* Check that the chip has finished the reset. */ 1620 /* Check that the chip has finished the reset. */
1501 for (i = 1000; i > 0; i--) { 1621 for (i = 100; i > 0; i--) {
1502 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 1622 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1503 break; 1623 break;
1504 udelay(10); 1624 msleep_interruptible(1);
1505 } 1625 }
1506 1626
1507 /* Identify chip attached to board */ 1627 /* Identify chip attached to board */
@@ -1519,8 +1639,8 @@ rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1519 /* Unknown chip: assume array element #0, original RTL-8169 */ 1639 /* Unknown chip: assume array element #0, original RTL-8169 */
1520 if (netif_msg_probe(tp)) { 1640 if (netif_msg_probe(tp)) {
1521 dev_printk(KERN_DEBUG, &pdev->dev, 1641 dev_printk(KERN_DEBUG, &pdev->dev,
1522 "unknown chip version, assuming %s\n", 1642 "unknown chip version, assuming %s\n",
1523 rtl_chip_info[0].name); 1643 rtl_chip_info[0].name);
1524 } 1644 }
1525 i++; 1645 i++;
1526 } 1646 }
@@ -1531,56 +1651,6 @@ rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1531 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); 1651 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1532 RTL_W8(Cfg9346, Cfg9346_Lock); 1652 RTL_W8(Cfg9346, Cfg9346_Lock);
1533 1653
1534 *ioaddr_out = ioaddr;
1535 *dev_out = dev;
1536out:
1537 return rc;
1538
1539err_out_free_res:
1540 pci_release_regions(pdev);
1541
1542err_out_mwi:
1543 pci_clear_mwi(pdev);
1544
1545err_out_disable:
1546 pci_disable_device(pdev);
1547
1548err_out_free_dev:
1549 free_netdev(dev);
1550err_out:
1551 *ioaddr_out = NULL;
1552 *dev_out = NULL;
1553 goto out;
1554}
1555
1556static int __devinit
1557rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1558{
1559 struct net_device *dev = NULL;
1560 struct rtl8169_private *tp;
1561 void __iomem *ioaddr = NULL;
1562 static int board_idx = -1;
1563 u8 autoneg, duplex;
1564 u16 speed;
1565 int i, rc;
1566
1567 assert(pdev != NULL);
1568 assert(ent != NULL);
1569
1570 board_idx++;
1571
1572 if (netif_msg_drv(&debug)) {
1573 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1574 MODULENAME, RTL8169_VERSION);
1575 }
1576
1577 rc = rtl8169_init_board(pdev, &dev, &ioaddr);
1578 if (rc)
1579 return rc;
1580
1581 tp = netdev_priv(dev);
1582 assert(ioaddr != NULL);
1583
1584 if (RTL_R8(PHYstatus) & TBI_Enable) { 1654 if (RTL_R8(PHYstatus) & TBI_Enable) {
1585 tp->set_speed = rtl8169_set_speed_tbi; 1655 tp->set_speed = rtl8169_set_speed_tbi;
1586 tp->get_settings = rtl8169_gset_tbi; 1656 tp->get_settings = rtl8169_gset_tbi;
@@ -1588,13 +1658,15 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1588 tp->phy_reset_pending = rtl8169_tbi_reset_pending; 1658 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1589 tp->link_ok = rtl8169_tbi_link_ok; 1659 tp->link_ok = rtl8169_tbi_link_ok;
1590 1660
1591 tp->phy_1000_ctrl_reg = PHY_Cap_1000_Full; /* Implied by TBI */ 1661 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1592 } else { 1662 } else {
1593 tp->set_speed = rtl8169_set_speed_xmii; 1663 tp->set_speed = rtl8169_set_speed_xmii;
1594 tp->get_settings = rtl8169_gset_xmii; 1664 tp->get_settings = rtl8169_gset_xmii;
1595 tp->phy_reset_enable = rtl8169_xmii_reset_enable; 1665 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1596 tp->phy_reset_pending = rtl8169_xmii_reset_pending; 1666 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1597 tp->link_ok = rtl8169_xmii_link_ok; 1667 tp->link_ok = rtl8169_xmii_link_ok;
1668
1669 dev->do_ioctl = rtl8169_ioctl;
1598 } 1670 }
1599 1671
1600 /* Get MAC address. FIXME: read EEPROM */ 1672 /* Get MAC address. FIXME: read EEPROM */
@@ -1609,6 +1681,7 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1609 dev->stop = rtl8169_close; 1681 dev->stop = rtl8169_close;
1610 dev->tx_timeout = rtl8169_tx_timeout; 1682 dev->tx_timeout = rtl8169_tx_timeout;
1611 dev->set_multicast_list = rtl8169_set_rx_mode; 1683 dev->set_multicast_list = rtl8169_set_rx_mode;
1684 dev->set_mac_address = rtl8169_set_mac_addr;
1612 dev->watchdog_timeo = RTL8169_TX_TIMEOUT; 1685 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1613 dev->irq = pdev->irq; 1686 dev->irq = pdev->irq;
1614 dev->base_addr = (unsigned long) ioaddr; 1687 dev->base_addr = (unsigned long) ioaddr;
@@ -1632,19 +1705,13 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1632 tp->intr_mask = 0xffff; 1705 tp->intr_mask = 0xffff;
1633 tp->pci_dev = pdev; 1706 tp->pci_dev = pdev;
1634 tp->mmio_addr = ioaddr; 1707 tp->mmio_addr = ioaddr;
1708 tp->align = rtl_cfg_info[ent->driver_data].align;
1635 1709
1636 spin_lock_init(&tp->lock); 1710 spin_lock_init(&tp->lock);
1637 1711
1638 rc = register_netdev(dev); 1712 rc = register_netdev(dev);
1639 if (rc) { 1713 if (rc < 0)
1640 rtl8169_release_board(pdev, dev, ioaddr); 1714 goto err_out_unmap_5;
1641 return rc;
1642 }
1643
1644 if (netif_msg_probe(tp)) {
1645 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n",
1646 dev->name, rtl_chip_info[tp->chipset].name);
1647 }
1648 1715
1649 pci_set_drvdata(pdev, dev); 1716 pci_set_drvdata(pdev, dev);
1650 1717
@@ -1653,38 +1720,29 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1653 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " 1720 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1654 "IRQ %d\n", 1721 "IRQ %d\n",
1655 dev->name, 1722 dev->name,
1656 rtl_chip_info[ent->driver_data].name, 1723 rtl_chip_info[tp->chipset].name,
1657 dev->base_addr, 1724 dev->base_addr,
1658 dev->dev_addr[0], dev->dev_addr[1], 1725 dev->dev_addr[0], dev->dev_addr[1],
1659 dev->dev_addr[2], dev->dev_addr[3], 1726 dev->dev_addr[2], dev->dev_addr[3],
1660 dev->dev_addr[4], dev->dev_addr[5], dev->irq); 1727 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1661 } 1728 }
1662 1729
1663 rtl8169_hw_phy_config(dev); 1730 rtl8169_init_phy(dev, tp);
1664
1665 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1666 RTL_W8(0x82, 0x01);
1667 1731
1668 if (tp->mac_version < RTL_GIGA_MAC_VER_E) { 1732out:
1669 dprintk("Set PCI Latency=0x40\n"); 1733 return rc;
1670 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
1671 }
1672
1673 if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
1674 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1675 RTL_W8(0x82, 0x01);
1676 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1677 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1678 }
1679
1680 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1681
1682 rtl8169_set_speed(dev, autoneg, speed, duplex);
1683
1684 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1685 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1686 1734
1687 return 0; 1735err_out_unmap_5:
1736 iounmap(ioaddr);
1737err_out_free_res_4:
1738 pci_release_regions(pdev);
1739err_out_mwi_3:
1740 pci_clear_mwi(pdev);
1741err_out_disable_2:
1742 pci_disable_device(pdev);
1743err_out_free_dev_1:
1744 free_netdev(dev);
1745 goto out;
1688} 1746}
1689 1747
1690static void __devexit 1748static void __devexit
@@ -1780,20 +1838,41 @@ rtl8169_hw_start(struct net_device *dev)
1780{ 1838{
1781 struct rtl8169_private *tp = netdev_priv(dev); 1839 struct rtl8169_private *tp = netdev_priv(dev);
1782 void __iomem *ioaddr = tp->mmio_addr; 1840 void __iomem *ioaddr = tp->mmio_addr;
1841 struct pci_dev *pdev = tp->pci_dev;
1783 u32 i; 1842 u32 i;
1784 1843
1785 /* Soft reset the chip. */ 1844 /* Soft reset the chip. */
1786 RTL_W8(ChipCmd, CmdReset); 1845 RTL_W8(ChipCmd, CmdReset);
1787 1846
1788 /* Check that the chip has finished the reset. */ 1847 /* Check that the chip has finished the reset. */
1789 for (i = 1000; i > 0; i--) { 1848 for (i = 100; i > 0; i--) {
1790 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 1849 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1791 break; 1850 break;
1792 udelay(10); 1851 msleep_interruptible(1);
1852 }
1853
1854 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
1855 pci_write_config_word(pdev, 0x68, 0x00);
1856 pci_write_config_word(pdev, 0x69, 0x08);
1857 }
1858
1859 /* Undocumented stuff. */
1860 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1861 u16 cmd;
1862
1863 /* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */
1864 if ((RTL_R8(Config2) & 0x07) & 0x01)
1865 RTL_W32(0x7c, 0x0007ffff);
1866
1867 RTL_W32(0x7c, 0x0007ff00);
1868
1869 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1870 cmd = cmd & 0xef;
1871 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1793 } 1872 }
1794 1873
1874
1795 RTL_W8(Cfg9346, Cfg9346_Unlock); 1875 RTL_W8(Cfg9346, Cfg9346_Unlock);
1796 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1797 RTL_W8(EarlyTxThres, EarlyTxThld); 1876 RTL_W8(EarlyTxThres, EarlyTxThld);
1798 1877
1799 /* Low hurts. Let's disable the filtering. */ 1878 /* Low hurts. Let's disable the filtering. */
@@ -1805,32 +1884,40 @@ rtl8169_hw_start(struct net_device *dev)
1805 RTL_W32(RxConfig, i); 1884 RTL_W32(RxConfig, i);
1806 1885
1807 /* Set DMA burst size and Interframe Gap Time */ 1886 /* Set DMA burst size and Interframe Gap Time */
1808 RTL_W32(TxConfig, 1887 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1809 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap << 1888 (InterFrameGap << TxInterFrameGapShift));
1810 TxInterFrameGapShift)); 1889
1811 tp->cp_cmd |= RTL_R16(CPlusCmd); 1890 tp->cp_cmd |= RTL_R16(CPlusCmd) | PCIMulRW;
1812 RTL_W16(CPlusCmd, tp->cp_cmd);
1813 1891
1814 if ((tp->mac_version == RTL_GIGA_MAC_VER_D) || 1892 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1815 (tp->mac_version == RTL_GIGA_MAC_VER_E)) { 1893 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1816 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. " 1894 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1817 "Bit-3 and bit-14 MUST be 1\n"); 1895 "Bit-3 and bit-14 MUST be 1\n");
1818 tp->cp_cmd |= (1 << 14) | PCIMulRW; 1896 tp->cp_cmd |= (1 << 14);
1819 RTL_W16(CPlusCmd, tp->cp_cmd);
1820 } 1897 }
1821 1898
1899 RTL_W16(CPlusCmd, tp->cp_cmd);
1900
1822 /* 1901 /*
1823 * Undocumented corner. Supposedly: 1902 * Undocumented corner. Supposedly:
1824 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets 1903 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1825 */ 1904 */
1826 RTL_W16(IntrMitigate, 0x0000); 1905 RTL_W16(IntrMitigate, 0x0000);
1827 1906
1828 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK)); 1907 /*
1908 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1909 * register to be written before TxDescAddrLow to work.
1910 * Switching from MMIO to I/O access fixes the issue as well.
1911 */
1829 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32)); 1912 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
1830 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK)); 1913 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1831 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32)); 1914 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1915 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1916 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1832 RTL_W8(Cfg9346, Cfg9346_Lock); 1917 RTL_W8(Cfg9346, Cfg9346_Lock);
1833 udelay(10); 1918
1919 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1920 RTL_R8(IntrMask);
1834 1921
1835 RTL_W32(RxMissed, 0); 1922 RTL_W32(RxMissed, 0);
1836 1923
@@ -1842,6 +1929,8 @@ rtl8169_hw_start(struct net_device *dev)
1842 /* Enable all known interrupts by setting the interrupt mask. */ 1929 /* Enable all known interrupts by setting the interrupt mask. */
1843 RTL_W16(IntrMask, rtl8169_intr_mask); 1930 RTL_W16(IntrMask, rtl8169_intr_mask);
1844 1931
1932 __rtl8169_set_mac_addr(dev, ioaddr);
1933
1845 netif_start_queue(dev); 1934 netif_start_queue(dev);
1846} 1935}
1847 1936
@@ -1910,17 +1999,18 @@ static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
1910} 1999}
1911 2000
1912static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff, 2001static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
1913 struct RxDesc *desc, int rx_buf_sz) 2002 struct RxDesc *desc, int rx_buf_sz,
2003 unsigned int align)
1914{ 2004{
1915 struct sk_buff *skb; 2005 struct sk_buff *skb;
1916 dma_addr_t mapping; 2006 dma_addr_t mapping;
1917 int ret = 0; 2007 int ret = 0;
1918 2008
1919 skb = dev_alloc_skb(rx_buf_sz + NET_IP_ALIGN); 2009 skb = dev_alloc_skb(rx_buf_sz + align);
1920 if (!skb) 2010 if (!skb)
1921 goto err_out; 2011 goto err_out;
1922 2012
1923 skb_reserve(skb, NET_IP_ALIGN); 2013 skb_reserve(skb, align);
1924 *sk_buff = skb; 2014 *sk_buff = skb;
1925 2015
1926 mapping = pci_map_single(pdev, skb->data, rx_buf_sz, 2016 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
@@ -1953,15 +2043,15 @@ static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
1953 u32 start, u32 end) 2043 u32 start, u32 end)
1954{ 2044{
1955 u32 cur; 2045 u32 cur;
1956 2046
1957 for (cur = start; end - cur > 0; cur++) { 2047 for (cur = start; end - cur > 0; cur++) {
1958 int ret, i = cur % NUM_RX_DESC; 2048 int ret, i = cur % NUM_RX_DESC;
1959 2049
1960 if (tp->Rx_skbuff[i]) 2050 if (tp->Rx_skbuff[i])
1961 continue; 2051 continue;
1962 2052
1963 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i, 2053 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
1964 tp->RxDescArray + i, tp->rx_buf_sz); 2054 tp->RxDescArray + i, tp->rx_buf_sz, tp->align);
1965 if (ret < 0) 2055 if (ret < 0)
1966 break; 2056 break;
1967 } 2057 }
@@ -2190,8 +2280,8 @@ static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2190 dma_addr_t mapping; 2280 dma_addr_t mapping;
2191 u32 status, len; 2281 u32 status, len;
2192 u32 opts1; 2282 u32 opts1;
2193 int ret = 0; 2283 int ret = NETDEV_TX_OK;
2194 2284
2195 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { 2285 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2196 if (netif_msg_drv(tp)) { 2286 if (netif_msg_drv(tp)) {
2197 printk(KERN_ERR 2287 printk(KERN_ERR
@@ -2255,7 +2345,7 @@ out:
2255 2345
2256err_stop: 2346err_stop:
2257 netif_stop_queue(dev); 2347 netif_stop_queue(dev);
2258 ret = 1; 2348 ret = NETDEV_TX_BUSY;
2259err_update_stats: 2349err_update_stats:
2260 tp->stats.tx_dropped++; 2350 tp->stats.tx_dropped++;
2261 goto out; 2351 goto out;
@@ -2372,16 +2462,17 @@ static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2372} 2462}
2373 2463
2374static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size, 2464static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
2375 struct RxDesc *desc, int rx_buf_sz) 2465 struct RxDesc *desc, int rx_buf_sz,
2466 unsigned int align)
2376{ 2467{
2377 int ret = -1; 2468 int ret = -1;
2378 2469
2379 if (pkt_size < rx_copybreak) { 2470 if (pkt_size < rx_copybreak) {
2380 struct sk_buff *skb; 2471 struct sk_buff *skb;
2381 2472
2382 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN); 2473 skb = dev_alloc_skb(pkt_size + align);
2383 if (skb) { 2474 if (skb) {
2384 skb_reserve(skb, NET_IP_ALIGN); 2475 skb_reserve(skb, align);
2385 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0); 2476 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
2386 *sk_buff = skb; 2477 *sk_buff = skb;
2387 rtl8169_mark_to_asic(desc, rx_buf_sz); 2478 rtl8169_mark_to_asic(desc, rx_buf_sz);
@@ -2427,6 +2518,10 @@ rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2427 tp->stats.rx_length_errors++; 2518 tp->stats.rx_length_errors++;
2428 if (status & RxCRC) 2519 if (status & RxCRC)
2429 tp->stats.rx_crc_errors++; 2520 tp->stats.rx_crc_errors++;
2521 if (status & RxFOVF) {
2522 rtl8169_schedule_work(dev, rtl8169_reset_task);
2523 tp->stats.rx_fifo_errors++;
2524 }
2430 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); 2525 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2431 } else { 2526 } else {
2432 struct sk_buff *skb = tp->Rx_skbuff[entry]; 2527 struct sk_buff *skb = tp->Rx_skbuff[entry];
@@ -2447,13 +2542,13 @@ rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2447 } 2542 }
2448 2543
2449 rtl8169_rx_csum(skb, desc); 2544 rtl8169_rx_csum(skb, desc);
2450 2545
2451 pci_dma_sync_single_for_cpu(tp->pci_dev, 2546 pci_dma_sync_single_for_cpu(tp->pci_dev,
2452 le64_to_cpu(desc->addr), tp->rx_buf_sz, 2547 le64_to_cpu(desc->addr), tp->rx_buf_sz,
2453 PCI_DMA_FROMDEVICE); 2548 PCI_DMA_FROMDEVICE);
2454 2549
2455 if (rtl8169_try_rx_copy(&skb, pkt_size, desc, 2550 if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
2456 tp->rx_buf_sz)) { 2551 tp->rx_buf_sz, tp->align)) {
2457 pci_action = pci_unmap_single; 2552 pci_action = pci_unmap_single;
2458 tp->Rx_skbuff[entry] = NULL; 2553 tp->Rx_skbuff[entry] = NULL;
2459 } 2554 }
@@ -2543,7 +2638,7 @@ rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
2543 __netif_rx_schedule(dev); 2638 __netif_rx_schedule(dev);
2544 else if (netif_msg_intr(tp)) { 2639 else if (netif_msg_intr(tp)) {
2545 printk(KERN_INFO "%s: interrupt %04x taken in poll\n", 2640 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2546 dev->name, status); 2641 dev->name, status);
2547 } 2642 }
2548 break; 2643 break;
2549#else 2644#else
@@ -2716,6 +2811,15 @@ rtl8169_set_rx_mode(struct net_device *dev)
2716 tmp = rtl8169_rx_config | rx_mode | 2811 tmp = rtl8169_rx_config | rx_mode |
2717 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); 2812 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2718 2813
2814 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2815 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2816 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2817 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2818 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2819 mc_filter[0] = 0xffffffff;
2820 mc_filter[1] = 0xffffffff;
2821 }
2822
2719 RTL_W32(RxConfig, tmp); 2823 RTL_W32(RxConfig, tmp);
2720 RTL_W32(MAR0 + 0, mc_filter[0]); 2824 RTL_W32(MAR0 + 0, mc_filter[0]);
2721 RTL_W32(MAR0 + 4, mc_filter[1]); 2825 RTL_W32(MAR0 + 4, mc_filter[1]);
@@ -2741,7 +2845,7 @@ static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2741 RTL_W32(RxMissed, 0); 2845 RTL_W32(RxMissed, 0);
2742 spin_unlock_irqrestore(&tp->lock, flags); 2846 spin_unlock_irqrestore(&tp->lock, flags);
2743 } 2847 }
2744 2848
2745 return &tp->stats; 2849 return &tp->stats;
2746} 2850}
2747 2851
@@ -2809,7 +2913,7 @@ static struct pci_driver rtl8169_pci_driver = {
2809static int __init 2913static int __init
2810rtl8169_init_module(void) 2914rtl8169_init_module(void)
2811{ 2915{
2812 return pci_module_init(&rtl8169_pci_driver); 2916 return pci_register_driver(&rtl8169_pci_driver);
2813} 2917}
2814 2918
2815static void __exit 2919static void __exit
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 04:06:45 -0500