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path: root/drivers/net/r8169.c
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Diffstat (limited to 'drivers/net/r8169.c')
-rw-r--r--drivers/net/r8169.c75
1 files changed, 75 insertions, 0 deletions
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index f929dbada84e..f0f842d7b941 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -2384,8 +2384,38 @@ static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2384 } 2384 }
2385} 2385}
2386 2386
2387static void rtl_disable_clock_request(struct pci_dev *pdev)
2388{
2389 struct net_device *dev = pci_get_drvdata(pdev);
2390 struct rtl8169_private *tp = netdev_priv(dev);
2391 int cap = tp->pcie_cap;
2392
2393 if (cap) {
2394 u16 ctl;
2395
2396 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2397 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2398 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2399 }
2400}
2401
2402#define R8168_CPCMD_QUIRK_MASK (\
2403 EnableBist | \
2404 Mac_dbgo_oe | \
2405 Force_half_dup | \
2406 Force_rxflow_en | \
2407 Force_txflow_en | \
2408 Cxpl_dbg_sel | \
2409 ASF | \
2410 PktCntrDisable | \
2411 Mac_dbgo_sel)
2412
2387static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) 2413static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2388{ 2414{
2415 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2416
2417 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2418
2389 rtl_tx_performance_tweak(pdev, 2419 rtl_tx_performance_tweak(pdev,
2390 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); 2420 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
2391} 2421}
@@ -2393,25 +2423,70 @@ static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2393static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) 2423static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2394{ 2424{
2395 rtl_hw_start_8168bb(ioaddr, pdev); 2425 rtl_hw_start_8168bb(ioaddr, pdev);
2426
2427 RTL_W8(EarlyTxThres, EarlyTxThld);
2428
2429 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
2396} 2430}
2397 2431
2398static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) 2432static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2399{ 2433{
2434 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2435
2436 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2437
2400 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); 2438 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2439
2440 rtl_disable_clock_request(pdev);
2441
2442 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2401} 2443}
2402 2444
2403static void rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) 2445static void rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2404{ 2446{
2447 static struct ephy_info e_info_8168cp[] = {
2448 { 0x01, 0, 0x0001 },
2449 { 0x02, 0x0800, 0x1000 },
2450 { 0x03, 0, 0x0042 },
2451 { 0x06, 0x0080, 0x0000 },
2452 { 0x07, 0, 0x2000 }
2453 };
2454
2455 rtl_csi_access_enable(ioaddr);
2456
2457 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2458
2405 __rtl_hw_start_8168cp(ioaddr, pdev); 2459 __rtl_hw_start_8168cp(ioaddr, pdev);
2406} 2460}
2407 2461
2408static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) 2462static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2409{ 2463{
2464 static struct ephy_info e_info_8168c_1[] = {
2465 { 0x02, 0x0800, 0x1000 },
2466 { 0x03, 0, 0x0002 },
2467 { 0x06, 0x0080, 0x0000 }
2468 };
2469
2470 rtl_csi_access_enable(ioaddr);
2471
2472 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2473
2474 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2475
2410 __rtl_hw_start_8168cp(ioaddr, pdev); 2476 __rtl_hw_start_8168cp(ioaddr, pdev);
2411} 2477}
2412 2478
2413static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) 2479static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2414{ 2480{
2481 static struct ephy_info e_info_8168c_2[] = {
2482 { 0x01, 0, 0x0001 },
2483 { 0x03, 0x0400, 0x0220 }
2484 };
2485
2486 rtl_csi_access_enable(ioaddr);
2487
2488 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2489
2415 __rtl_hw_start_8168cp(ioaddr, pdev); 2490 __rtl_hw_start_8168cp(ioaddr, pdev);
2416} 2491}
2417 2492